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kernel_optimize_test/arch/m68k/include/asm/m5272sim.h

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Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
/****************************************************************************/
/*
* m5272sim.h -- ColdFire 5272 System Integration Module support.
*
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*/
/****************************************************************************/
#ifndef m5272sim_h
#define m5272sim_h
/****************************************************************************/
m68knommu: fix clock rate value reported for ColdFire 54xx parts The instruction timings of the ColdFire 54xx family parts are different to other version 4 parts (or version 2 or 3 parts for that matter too). Move the instruction timing setting into the ColdFire part specific headers, and set the 54xx value appropriately. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-02 15:40:37 +08:00
#define CPU_NAME "COLDFIRE(m5272)"
#define CPU_INSTR_PER_JIFFY 3
m68knommu: remove ColdFire CLOCK_DIV config option The reality is that you do not need the abiltity to configure the clock divider for ColdFire CPUs. It is a fixed ratio on any given ColdFire family member. It is not the same for all ColdFire parts, but it is always the same in a model range. So hard define the divider for each supported ColdFire CPU type and remove the Kconfig option. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-09 12:19:08 +08:00
#define MCF_BUSCLK MCF_CLK
m68knommu: move ColdFire CPU names into their headers Move the ColdFire CPU names out of setup.c and into their repsective headers. That way when we add new ones we won't need to modify setup.c any more. Add the missing 548x CPU name. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-02 15:13:27 +08:00
m68knommu: create bit definitions for the version 2 ColdFire cache controller The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-09 08:12:29 +08:00
#include <asm/m52xxacr.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
/*
* Define the 5272 SIM register set addresses.
*/
m68knommu: make remaining ColdFire 5272 register definitions absolute addresses Make the remaining definitions of the 5272 ColdFire registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-14 14:25:12 +08:00
#define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */
#define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */
#define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */
#define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */
#define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
m68knommu: make ColdFire Interrupt Source register definitions absolute addresses Make all definitions of the ColdFire Interrupt Source registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-08-17 14:48:16 +08:00
#define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
m68knommu: make ColdFire IMR and IPR register definitions absolute addresses Make all definitions of the ColdFire Interrupt Mask and Pending registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-07-15 19:42:47 +08:00
#define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */
#define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */
#define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */
#define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
m68knommu: make ColdFire watchdog register definitions absolute addresses Make all definitions of the ColdFire Software watchdog registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-07-15 20:01:08 +08:00
#define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */
#define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */
#define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */
#define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
m68knommu: make ColdFire Chip Select register definitions absolute addresses Make all definitions of the ColdFire Chip Select registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-14 13:36:02 +08:00
#define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */
#define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */
#define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */
#define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */
#define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */
#define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */
#define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */
#define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */
#define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */
#define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */
#define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */
#define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */
#define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */
#define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */
#define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */
#define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
m68knommu: make remaining ColdFire 5272 register definitions absolute addresses Make the remaining definitions of the 5272 ColdFire registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-14 14:25:12 +08:00
#define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */
#define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */
#define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */
#define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */
#define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */
#define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
#define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
#define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
m68knommu: make 5272 UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 5272 UART addressing so that: . UARTs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-23 22:30:37 +08:00
#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
m68knommu: move UART addressing to part specific includes The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-03 10:50:30 +08:00
generic GPIO support for the Freescale Coldfire 5272. Add support for the 5272. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:07 +08:00
#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */
#define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */
#define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */
#define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */
#define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */
#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
m68knommu: move ColdFire DMA register addresses to per-cpu headers The base addresses of the ColdFire DMA unit registers belong with all the other address definitions in the per-cpu headers. The current definitions assume they are relative to an MBAR register. Not all ColdFire CPUs have an MBAR register. A clean address define can only be acheived in the per-cpu headers along with all the other chips peripheral base addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-05 22:54:36 +08:00
#define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
m68knommu: remove use of MBAR in old-style ColdFire timer Not all ColdFire CPUs that use the old style timer hardware module use an MBAR set peripheral region. Move the TIMER base address defines to the per-CPU header files where we can set it correctly based on how the peripherals are mapped - instead of using a fake MBAR for some platforms. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-09 07:57:14 +08:00
#define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
m68knommu: make 5272 FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 5272 FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 08:13:36 +08:00
#define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */
#define MCFFEC_SIZE0 0x1d0
m68knommu: simplify ColdFire "timers" clock initialization The ColdFire "timers" clock setup can be simplified. There is really no need for the flexible per-platform setup code. The clock interrupt can be hard defined per CPU platform (in CPU include files). This makes the actual timer code simpler. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-05-19 12:52:40 +08:00
/*
* Define system peripheral IRQ usage.
*/
m68knommu: create a speciailized ColdFire 5272 interrupt controller The ColdFire 5272 CPU has a very different interrupt controller than any of the other ColdFire parts. It needs its own controller code to correctly setup and ack interrupts. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-07-07 07:39:11 +08:00
#define MCFINT_VECBASE 64 /* Base of interrupts */
#define MCF_IRQ_SPURIOUS 64 /* User Spurious */
#define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
#define MCF_IRQ_EINT2 66 /* External Interrupt 2 */
#define MCF_IRQ_EINT3 67 /* External Interrupt 3 */
#define MCF_IRQ_EINT4 68 /* External Interrupt 4 */
#define MCF_IRQ_TIMER1 69 /* Timer 1 */
#define MCF_IRQ_TIMER2 70 /* Timer 2 */
#define MCF_IRQ_TIMER3 71 /* Timer 3 */
#define MCF_IRQ_TIMER4 72 /* Timer 4 */
m68knommu: make 5272 UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 5272 UART addressing so that: . UARTs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-23 22:30:37 +08:00
#define MCF_IRQ_UART0 73 /* UART 0 */
#define MCF_IRQ_UART1 74 /* UART 1 */
m68knommu: create a speciailized ColdFire 5272 interrupt controller The ColdFire 5272 CPU has a very different interrupt controller than any of the other ColdFire parts. It needs its own controller code to correctly setup and ack interrupts. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-07-07 07:39:11 +08:00
#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
#define MCF_IRQ_USB1 78 /* USB Endpoint 1 */
#define MCF_IRQ_USB2 79 /* USB Endpoint 2 */
#define MCF_IRQ_USB3 80 /* USB Endpoint 3 */
#define MCF_IRQ_USB4 81 /* USB Endpoint 4 */
#define MCF_IRQ_USB5 82 /* USB Endpoint 5 */
#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */
#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */
#define MCF_IRQ_DMA 85 /* DMA Controller */
m68knommu: make 5272 FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 5272 FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 08:13:36 +08:00
#define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */
#define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */
#define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */
m68knommu: create a speciailized ColdFire 5272 interrupt controller The ColdFire 5272 CPU has a very different interrupt controller than any of the other ColdFire parts. It needs its own controller code to correctly setup and ack interrupts. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-07-07 07:39:11 +08:00
#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */
#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */
#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */
#define MCF_IRQ_SWTO 92 /* Software Watchdog */
#define MCFINT_VECMAX 95 /* Maxmum interrupt */
#define MCF_IRQ_TIMER MCF_IRQ_TIMER1
#define MCF_IRQ_PROFILER MCF_IRQ_TIMER2
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
generic GPIO support for the Freescale Coldfire 5272. Add support for the 5272. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:07 +08:00
/*
* Generic GPIO support
*/
m68knommu: fix inconsistent formating in ColdFire 5272 definitions Fix tab broken defines to be consistent with others in this file. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-18 13:20:19 +08:00
#define MCFGPIO_PIN_MAX 48
#define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
/****************************************************************************/
#endif /* m5272sim_h */
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