forked from luck/tmp_suning_uos_patched
71 lines
2.7 KiB
C
71 lines
2.7 KiB
C
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#ifndef __LINUX_ATMEL_PWM_H
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#define __LINUX_ATMEL_PWM_H
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/**
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* struct pwm_channel - driver handle to a PWM channel
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* @regs: base of this channel's registers
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* @index: number of this channel (0..31)
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* @mck: base clock rate, which can be prescaled and maybe subdivided
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*
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* Drivers initialize a pwm_channel structure using pwm_channel_alloc().
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* Then they configure its clock rate (derived from MCK), alignment,
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* polarity, and duty cycle by writing directly to the channel registers,
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* before enabling the channel by calling pwm_channel_enable().
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*
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* After emitting a PWM signal for the desired length of time, drivers
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* may then pwm_channel_disable() or pwm_channel_free(). Both of these
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* disable the channel, but when it's freed the IRQ is deconfigured and
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* the channel must later be re-allocated and reconfigured.
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*
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* Note that if the period or duty cycle need to be changed while the
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* PWM channel is operating, drivers must use the PWM_CUPD double buffer
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* mechanism, either polling until they change or getting implicitly
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* notified through a once-per-period interrupt handler.
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*/
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struct pwm_channel {
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void __iomem *regs;
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unsigned index;
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unsigned long mck;
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};
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extern int pwm_channel_alloc(int index, struct pwm_channel *ch);
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extern int pwm_channel_free(struct pwm_channel *ch);
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extern int pwm_clk_alloc(unsigned prescale, unsigned div);
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extern void pwm_clk_free(unsigned clk);
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extern int __pwm_channel_onoff(struct pwm_channel *ch, int enabled);
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#define pwm_channel_enable(ch) __pwm_channel_onoff((ch), 1)
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#define pwm_channel_disable(ch) __pwm_channel_onoff((ch), 0)
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/* periodic interrupts, mostly for CUPD changes to period or cycle */
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extern int pwm_channel_handler(struct pwm_channel *ch,
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void (*handler)(struct pwm_channel *ch));
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/* per-channel registers (banked at pwm_channel->regs) */
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#define PWM_CMR 0x00 /* mode register */
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#define PWM_CPR_CPD (1 << 10) /* set: CUPD modifies period */
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#define PWM_CPR_CPOL (1 << 9) /* set: idle high */
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#define PWM_CPR_CALG (1 << 8) /* set: center align */
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#define PWM_CPR_CPRE (0xf << 0) /* mask: rate is mck/(2^pre) */
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#define PWM_CPR_CLKA (0xb << 0) /* rate CLKA */
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#define PWM_CPR_CLKB (0xc << 0) /* rate CLKB */
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#define PWM_CDTY 0x04 /* duty cycle (max of CPRD) */
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#define PWM_CPRD 0x08 /* period (count up from zero) */
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#define PWM_CCNT 0x0c /* counter (20 bits?) */
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#define PWM_CUPD 0x10 /* update CPRD (or CDTY) next period */
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static inline void
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pwm_channel_writel(struct pwm_channel *pwmc, unsigned offset, u32 val)
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{
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__raw_writel(val, pwmc->regs + offset);
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}
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static inline u32 pwm_channel_readl(struct pwm_channel *pwmc, unsigned offset)
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{
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return __raw_readl(pwmc->regs + offset);
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}
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#endif /* __LINUX_ATMEL_PWM_H */
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