2005-04-17 06:20:36 +08:00
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#ifndef __ASM_SH64_PGTABLE_H
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#define __ASM_SH64_PGTABLE_H
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#include <asm-generic/4level-fixup.h>
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* include/asm-sh64/pgtable.h
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*
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* Copyright (C) 2000, 2001 Paolo Alberelli
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* Copyright (C) 2003, 2004 Paul Mundt
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* Copyright (C) 2003, 2004 Richard Curnow
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*
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* This file contains the functions and defines necessary to modify and use
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* the SuperH page table tree.
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*/
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#ifndef __ASSEMBLY__
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <linux/threads.h>
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#include <linux/config.h>
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2005-11-07 16:59:43 +08:00
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struct vm_area_struct;
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2005-04-17 06:20:36 +08:00
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extern void paging_init(void);
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/* We provide our own get_unmapped_area to avoid cache synonym issue */
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#define HAVE_ARCH_UNMAPPED_AREA
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/*
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* Basically we have the same two-level (which is the logical three level
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* Linux page table layout folded) page tables as the i386.
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*/
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern unsigned char empty_zero_page[PAGE_SIZE];
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#define ZERO_PAGE(vaddr) (mem_map + MAP_NR(empty_zero_page))
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#endif /* !__ASSEMBLY__ */
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/*
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* NEFF and NPHYS related defines.
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* FIXME : These need to be model-dependent. For now this is OK, SH5-101 and SH5-103
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* implement 32 bits effective and 32 bits physical. But future implementations may
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* extend beyond this.
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*/
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#define NEFF 32
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#define NEFF_SIGN (1LL << (NEFF - 1))
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#define NEFF_MASK (-1LL << NEFF)
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#define NPHYS 32
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#define NPHYS_SIGN (1LL << (NPHYS - 1))
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#define NPHYS_MASK (-1LL << NPHYS)
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/* Typically 2-level is sufficient up to 32 bits of virtual address space, beyond
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that 3-level would be appropriate. */
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#if defined(CONFIG_SH64_PGTABLE_2_LEVEL)
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/* For 4k pages, this contains 512 entries, i.e. 9 bits worth of address. */
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#define PTRS_PER_PTE ((1<<PAGE_SHIFT)/sizeof(unsigned long long))
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#define PTE_MAGNITUDE 3 /* sizeof(unsigned long long) magnit. */
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#define PTE_SHIFT PAGE_SHIFT
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#define PTE_BITS (PAGE_SHIFT - PTE_MAGNITUDE)
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/* top level: PMD. */
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#define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
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#define PGD_BITS (NEFF - PGDIR_SHIFT)
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#define PTRS_PER_PGD (1<<PGD_BITS)
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/* middle level: PMD. This doesn't do anything for the 2-level case. */
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#define PTRS_PER_PMD (1)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define PMD_SHIFT PGDIR_SHIFT
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#define PMD_SIZE PGDIR_SIZE
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#define PMD_MASK PGDIR_MASK
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#elif defined(CONFIG_SH64_PGTABLE_3_LEVEL)
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/*
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* three-level asymmetric paging structure: PGD is top level.
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* The asymmetry comes from 32-bit pointers and 64-bit PTEs.
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*/
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/* bottom level: PTE. It's 9 bits = 512 pointers */
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#define PTRS_PER_PTE ((1<<PAGE_SHIFT)/sizeof(unsigned long long))
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#define PTE_MAGNITUDE 3 /* sizeof(unsigned long long) magnit. */
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#define PTE_SHIFT PAGE_SHIFT
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#define PTE_BITS (PAGE_SHIFT - PTE_MAGNITUDE)
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/* middle level: PMD. It's 10 bits = 1024 pointers */
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#define PTRS_PER_PMD ((1<<PAGE_SHIFT)/sizeof(unsigned long long *))
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#define PMD_MAGNITUDE 2 /* sizeof(unsigned long long *) magnit. */
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#define PMD_SHIFT (PTE_SHIFT + PTE_BITS)
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#define PMD_BITS (PAGE_SHIFT - PMD_MAGNITUDE)
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/* top level: PMD. It's 1 bit = 2 pointers */
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#define PGDIR_SHIFT (PMD_SHIFT + PMD_BITS)
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#define PGD_BITS (NEFF - PGDIR_SHIFT)
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#define PTRS_PER_PGD (1<<PGD_BITS)
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#else
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#error "No defined number of page table levels"
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#endif
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/*
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* Error outputs.
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*/
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
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#define pmd_ERROR(e) \
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printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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/*
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* Table setting routines. Used within arch/mm only.
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*/
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#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
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#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
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static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
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{
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unsigned long long x = ((unsigned long long) pteval.pte);
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unsigned long long *xp = (unsigned long long *) pteptr;
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/*
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* Sign-extend based on NPHYS.
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*/
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*(xp) = (x & NPHYS_SIGN) ? (x | NPHYS_MASK) : x;
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}
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#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep)
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{
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pmd_val(*pmdp) = (unsigned long) ptep;
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}
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/*
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* PGD defines. Top level.
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*/
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/* To find an entry in a generic PGD. */
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#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
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#define __pgd_offset(address) pgd_index(address)
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#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
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/* To find an entry in a kernel PGD. */
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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/*
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* PGD level access routines.
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*
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* Note1:
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* There's no need to use physical addresses since the tree walk is all
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* in performed in software, until the PTE translation.
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*
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* Note 2:
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* A PGD entry can be uninitialized (_PGD_UNUSED), generically bad,
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* clear (_PGD_EMPTY), present. When present, lower 3 nibbles contain
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* _KERNPG_TABLE. Being a kernel virtual pointer also bit 31 must
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* be 1. Assuming an arbitrary clear value of bit 31 set to 0 and
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* lower 3 nibbles set to 0xFFF (_PGD_EMPTY) any other value is a
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* bad pgd that must be notified via printk().
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*
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*/
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#define _PGD_EMPTY 0x0
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#if defined(CONFIG_SH64_PGTABLE_2_LEVEL)
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static inline int pgd_none(pgd_t pgd) { return 0; }
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static inline int pgd_bad(pgd_t pgd) { return 0; }
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#define pgd_present(pgd) ((pgd_val(pgd) & _PAGE_PRESENT) ? 1 : 0)
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#define pgd_clear(xx) do { } while(0)
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#elif defined(CONFIG_SH64_PGTABLE_3_LEVEL)
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#define pgd_present(pgd_entry) (1)
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#define pgd_none(pgd_entry) (pgd_val((pgd_entry)) == _PGD_EMPTY)
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/* TODO: Think later about what a useful definition of 'bad' would be now. */
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#define pgd_bad(pgd_entry) (0)
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#define pgd_clear(pgd_entry_p) (set_pgd((pgd_entry_p), __pgd(_PGD_EMPTY)))
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#endif
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#define pgd_page(pgd_entry) ((unsigned long) (pgd_val(pgd_entry) & PAGE_MASK))
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/*
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* PMD defines. Middle level.
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*/
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/* PGD to PMD dereferencing */
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#if defined(CONFIG_SH64_PGTABLE_2_LEVEL)
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static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
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{
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return (pmd_t *) dir;
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}
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#elif defined(CONFIG_SH64_PGTABLE_3_LEVEL)
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#define __pmd_offset(address) \
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(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
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#define pmd_offset(dir, addr) \
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((pmd_t *) ((pgd_val(*(dir))) & PAGE_MASK) + __pmd_offset((addr)))
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#endif
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/*
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* PMD level access routines. Same notes as above.
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*/
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#define _PMD_EMPTY 0x0
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/* Either the PMD is empty or present, it's not paged out */
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#define pmd_present(pmd_entry) (pmd_val(pmd_entry) & _PAGE_PRESENT)
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#define pmd_clear(pmd_entry_p) (set_pmd((pmd_entry_p), __pmd(_PMD_EMPTY)))
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#define pmd_none(pmd_entry) (pmd_val((pmd_entry)) == _PMD_EMPTY)
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#define pmd_bad(pmd_entry) ((pmd_val(pmd_entry) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
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#define pmd_page_kernel(pmd_entry) \
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((unsigned long) __va(pmd_val(pmd_entry) & PAGE_MASK))
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#define pmd_page(pmd) \
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(virt_to_page(pmd_val(pmd)))
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/* PMD to PTE dereferencing */
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#define pte_index(address) \
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((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset_kernel(dir, addr) \
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((pte_t *) ((pmd_val(*(dir))) & PAGE_MASK) + pte_index((addr)))
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#define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
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#define pte_offset_map_nested(dir,addr) pte_offset_kernel(dir, addr)
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#define pte_unmap(pte) do { } while (0)
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#define pte_unmap_nested(pte) do { } while (0)
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/* Round it up ! */
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#define USER_PTRS_PER_PGD ((TASK_SIZE+PGDIR_SIZE-1)/PGDIR_SIZE)
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2005-04-20 04:29:23 +08:00
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#define FIRST_USER_ADDRESS 0
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2005-04-17 06:20:36 +08:00
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#ifndef __ASSEMBLY__
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#define VMALLOC_END 0xff000000
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#define VMALLOC_START 0xf0000000
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#define VMALLOC_VMADDR(x) ((unsigned long)(x))
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#define IOBASE_VADDR 0xff000000
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#define IOBASE_END 0xffffffff
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/*
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* PTEL coherent flags.
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* See Chapter 17 ST50 CPU Core Volume 1, Architecture.
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*/
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/* The bits that are required in the SH-5 TLB are placed in the h/w-defined
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positions, to avoid expensive bit shuffling on every refill. The remaining
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bits are used for s/w purposes and masked out on each refill.
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Note, the PTE slots are used to hold data of type swp_entry_t when a page is
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swapped out. Only the _PAGE_PRESENT flag is significant when the page is
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swapped out, and it must be placed so that it doesn't overlap either the
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type or offset fields of swp_entry_t. For x86, offset is at [31:8] and type
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at [6:1], with _PAGE_PRESENT at bit 0 for both pte_t and swp_entry_t. This
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scheme doesn't map to SH-5 because bit [0] controls cacheability. So bit
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[2] is used for _PAGE_PRESENT and the type field of swp_entry_t is split
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into 2 pieces. That is handled by SWP_ENTRY and SWP_TYPE below. */
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#define _PAGE_WT 0x001 /* CB0: if cacheable, 1->write-thru, 0->write-back */
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#define _PAGE_DEVICE 0x001 /* CB0: if uncacheable, 1->device (i.e. no write-combining or reordering at bus level) */
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#define _PAGE_CACHABLE 0x002 /* CB1: uncachable/cachable */
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#define _PAGE_PRESENT 0x004 /* software: page referenced */
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#define _PAGE_FILE 0x004 /* software: only when !present */
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#define _PAGE_SIZE0 0x008 /* SZ0-bit : size of page */
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#define _PAGE_SIZE1 0x010 /* SZ1-bit : size of page */
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#define _PAGE_SHARED 0x020 /* software: reflects PTEH's SH */
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#define _PAGE_READ 0x040 /* PR0-bit : read access allowed */
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#define _PAGE_EXECUTE 0x080 /* PR1-bit : execute access allowed */
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#define _PAGE_WRITE 0x100 /* PR2-bit : write access allowed */
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#define _PAGE_USER 0x200 /* PR3-bit : user space access allowed */
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#define _PAGE_DIRTY 0x400 /* software: page accessed in write */
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#define _PAGE_ACCESSED 0x800 /* software: page referenced */
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/* Mask which drops software flags */
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#define _PAGE_FLAGS_HARDWARE_MASK 0xfffffffffffff3dbLL
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/*
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* HugeTLB support
|
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|
*/
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|
#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
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#define _PAGE_SZHUGE (_PAGE_SIZE0)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
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#define _PAGE_SZHUGE (_PAGE_SIZE1)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512MB)
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#define _PAGE_SZHUGE (_PAGE_SIZE0 | _PAGE_SIZE1)
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#endif
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/*
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* Default flags for a Kernel page.
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* This is fundametally also SHARED because the main use of this define
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* (other than for PGD/PMD entries) is for the VMALLOC pool which is
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* contextless.
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*
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* _PAGE_EXECUTE is required for modules
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*
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*/
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#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
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_PAGE_EXECUTE | \
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_PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_DIRTY | \
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_PAGE_SHARED)
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/* Default flags for a User page */
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#define _PAGE_TABLE (_KERNPG_TABLE | _PAGE_USER)
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#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define PAGE_NONE __pgprot(_PAGE_CACHABLE | _PAGE_ACCESSED)
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#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
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_PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_USER | \
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_PAGE_SHARED)
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/* We need to include PAGE_EXECUTE in PAGE_COPY because it is the default
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|
* protection mode for the stack. */
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#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_CACHABLE | \
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_PAGE_ACCESSED | _PAGE_USER | _PAGE_EXECUTE)
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#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_CACHABLE | \
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_PAGE_ACCESSED | _PAGE_USER)
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#define PAGE_KERNEL __pgprot(_KERNPG_TABLE)
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/*
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* In ST50 we have full permissions (Read/Write/Execute/Shared).
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* Just match'em all. These are for mmap(), therefore all at least
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|
* User/Cachable/Present/Accessed. No point in making Fault on Write.
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|
|
*/
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|
#define __MMAP_COMMON (_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED)
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|
|
/* sxwr */
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|
#define __P000 __pgprot(__MMAP_COMMON)
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|
#define __P001 __pgprot(__MMAP_COMMON | _PAGE_READ)
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|
#define __P010 __pgprot(__MMAP_COMMON)
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|
|
#define __P011 __pgprot(__MMAP_COMMON | _PAGE_READ)
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|
|
#define __P100 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE)
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|
#define __P101 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE | _PAGE_READ)
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|
|
#define __P110 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE)
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|
|
#define __P111 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE | _PAGE_READ)
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|
|
#define __S000 __pgprot(__MMAP_COMMON | _PAGE_SHARED)
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|
#define __S001 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_READ)
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|
|
#define __S010 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_WRITE)
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|
|
#define __S011 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_READ | _PAGE_WRITE)
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|
|
#define __S100 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE)
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|
|
#define __S101 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE | _PAGE_READ)
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|
|
|
#define __S110 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE | _PAGE_WRITE)
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|
|
#define __S111 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE | _PAGE_READ | _PAGE_WRITE)
|
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|
|
|
|
|
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|
|
/* Make it a device mapping for maximum safety (e.g. for mapping device
|
|
|
|
|
registers into user-space via /dev/map). */
|
|
|
|
|
#define pgprot_noncached(x) __pgprot(((x).pgprot & ~(_PAGE_CACHABLE)) | _PAGE_DEVICE)
|
|
|
|
|
#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
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|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Handling allocation failures during page table setup.
|
|
|
|
|
*/
|
|
|
|
|
extern void __handle_bad_pmd_kernel(pmd_t * pmd);
|
|
|
|
|
#define __handle_bad_pmd(x) __handle_bad_pmd_kernel(x)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* PTE level access routines.
|
|
|
|
|
*
|
|
|
|
|
* Note1:
|
|
|
|
|
* It's the tree walk leaf. This is physical address to be stored.
|
|
|
|
|
*
|
|
|
|
|
* Note 2:
|
|
|
|
|
* Regarding the choice of _PTE_EMPTY:
|
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|
|
|
|
|
|
|
|
We must choose a bit pattern that cannot be valid, whether or not the page
|
|
|
|
|
is present. bit[2]==1 => present, bit[2]==0 => swapped out. If swapped
|
|
|
|
|
out, bits [31:8], [6:3], [1:0] are under swapper control, so only bit[7] is
|
|
|
|
|
left for us to select. If we force bit[7]==0 when swapped out, we could use
|
|
|
|
|
the combination bit[7,2]=2'b10 to indicate an empty PTE. Alternatively, if
|
|
|
|
|
we force bit[7]==1 when swapped out, we can use all zeroes to indicate
|
|
|
|
|
empty. This is convenient, because the page tables get cleared to zero
|
|
|
|
|
when they are allocated.
|
|
|
|
|
|
|
|
|
|
*/
|
|
|
|
|
#define _PTE_EMPTY 0x0
|
|
|
|
|
#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
|
|
|
|
|
#define pte_clear(mm,addr,xp) (set_pte_at(mm, addr, xp, __pte(_PTE_EMPTY)))
|
|
|
|
|
#define pte_none(x) (pte_val(x) == _PTE_EMPTY)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Some definitions to translate between mem_map, PTEs, and page
|
|
|
|
|
* addresses:
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Given a PTE, return the index of the mem_map[] entry corresponding
|
|
|
|
|
* to the page frame the PTE. Get the absolute physical address, make
|
|
|
|
|
* a relative physical address and translate it to an index.
|
|
|
|
|
*/
|
|
|
|
|
#define pte_pagenr(x) (((unsigned long) (pte_val(x)) - \
|
|
|
|
|
__MEMORY_START) >> PAGE_SHIFT)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Given a PTE, return the "struct page *".
|
|
|
|
|
*/
|
|
|
|
|
#define pte_page(x) (mem_map + pte_pagenr(x))
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Return number of (down rounded) MB corresponding to x pages.
|
|
|
|
|
*/
|
|
|
|
|
#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The following have defined behavior only work if pte_present() is true.
|
|
|
|
|
*/
|
|
|
|
|
static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
|
|
|
|
|
static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXECUTE; }
|
|
|
|
|
static inline int pte_dirty(pte_t pte){ return pte_val(pte) & _PAGE_DIRTY; }
|
|
|
|
|
static inline int pte_young(pte_t pte){ return pte_val(pte) & _PAGE_ACCESSED; }
|
|
|
|
|
static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
|
|
|
|
|
static inline int pte_write(pte_t pte){ return pte_val(pte) & _PAGE_WRITE; }
|
|
|
|
|
|
|
|
|
|
extern inline pte_t pte_rdprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_READ)); return pte; }
|
|
|
|
|
extern inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_WRITE)); return pte; }
|
|
|
|
|
extern inline pte_t pte_exprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_EXECUTE)); return pte; }
|
|
|
|
|
extern inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
|
|
|
|
|
extern inline pte_t pte_mkold(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
|
|
|
|
|
|
|
|
|
|
extern inline pte_t pte_mkread(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_READ)); return pte; }
|
|
|
|
|
extern inline pte_t pte_mkwrite(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_WRITE)); return pte; }
|
|
|
|
|
extern inline pte_t pte_mkexec(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_EXECUTE)); return pte; }
|
|
|
|
|
extern inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
|
|
|
|
|
extern inline pte_t pte_mkyoung(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
|
2005-06-22 08:14:44 +08:00
|
|
|
extern inline pte_t pte_mkhuge(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; }
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Conversion functions: convert a page and protection to a page entry.
|
|
|
|
|
*
|
|
|
|
|
* extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
|
|
|
|
|
*/
|
|
|
|
|
#define mk_pte(page,pgprot) \
|
|
|
|
|
({ \
|
|
|
|
|
pte_t __pte; \
|
|
|
|
|
\
|
|
|
|
|
set_pte(&__pte, __pte((((page)-mem_map) << PAGE_SHIFT) | \
|
|
|
|
|
__MEMORY_START | pgprot_val((pgprot)))); \
|
|
|
|
|
__pte; \
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This takes a (absolute) physical page address that is used
|
|
|
|
|
* by the remapping functions
|
|
|
|
|
*/
|
|
|
|
|
#define mk_pte_phys(physpage, pgprot) \
|
|
|
|
|
({ pte_t __pte; set_pte(&__pte, __pte(physpage | pgprot_val(pgprot))); __pte; })
|
|
|
|
|
|
|
|
|
|
extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
|
|
|
|
{ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
|
|
|
|
|
|
|
|
|
|
typedef pte_t *pte_addr_t;
|
|
|
|
|
#define pgtable_cache_init() do { } while (0)
|
|
|
|
|
|
|
|
|
|
extern void update_mmu_cache(struct vm_area_struct * vma,
|
|
|
|
|
unsigned long address, pte_t pte);
|
|
|
|
|
|
|
|
|
|
/* Encode and decode a swap entry */
|
|
|
|
|
#define __swp_type(x) (((x).val & 3) + (((x).val >> 1) & 0x3c))
|
|
|
|
|
#define __swp_offset(x) ((x).val >> 8)
|
|
|
|
|
#define __swp_entry(type, offset) ((swp_entry_t) { ((offset << 8) + ((type & 0x3c) << 1) + (type & 3)) })
|
|
|
|
|
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
|
|
|
|
|
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
|
|
|
|
|
|
|
|
|
|
/* Encode and decode a nonlinear file mapping entry */
|
|
|
|
|
#define PTE_FILE_MAX_BITS 29
|
|
|
|
|
#define pte_to_pgoff(pte) (pte_val(pte))
|
|
|
|
|
#define pgoff_to_pte(off) ((pte_t) { (off) | _PAGE_FILE })
|
|
|
|
|
|
|
|
|
|
/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
|
|
|
|
|
#define PageSkip(page) (0)
|
|
|
|
|
#define kern_addr_valid(addr) (1)
|
|
|
|
|
|
|
|
|
|
#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
|
|
|
|
|
remap_pfn_range(vma, vaddr, pfn, size, prot)
|
|
|
|
|
|
|
|
|
|
#define MK_IOSPACE_PFN(space, pfn) (pfn)
|
|
|
|
|
#define GET_IOSPACE(pfn) 0
|
|
|
|
|
#define GET_PFN(pfn) (pfn)
|
|
|
|
|
|
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* No page table caches to initialise
|
|
|
|
|
*/
|
|
|
|
|
#define pgtable_cache_init() do { } while (0)
|
|
|
|
|
|
|
|
|
|
#define pte_pfn(x) (((unsigned long)((x).pte)) >> PAGE_SHIFT)
|
|
|
|
|
#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
|
|
|
|
|
#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
|
|
|
|
|
|
|
|
|
|
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
|
|
|
|
|
|
|
|
|
|
#include <asm-generic/pgtable.h>
|
|
|
|
|
|
|
|
|
|
#endif /* __ASM_SH64_PGTABLE_H */
|
