2012-10-31 06:02:04 +08:00
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[config]
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command = stat
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args = -dd kill >/dev/null 2>&1
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ret = 1
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# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_TASK_CLOCK
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[event1:base-stat]
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fd=1
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type=1
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config=1
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# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CONTEXT_SWITCHES
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[event2:base-stat]
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fd=2
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type=1
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config=3
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# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CPU_MIGRATIONS
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[event3:base-stat]
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fd=3
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type=1
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config=4
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# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_PAGE_FAULTS
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[event4:base-stat]
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fd=4
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type=1
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config=2
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# PERF_TYPE_HARDWARE / PERF_COUNT_HW_CPU_CYCLES
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[event5:base-stat]
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fd=5
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type=0
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config=0
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2017-10-09 21:07:12 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
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[event6:base-stat]
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fd=6
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type=0
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config=7
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2017-07-03 22:50:29 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_BACKEND
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[event7:base-stat]
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fd=7
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type=0
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config=8
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2017-07-03 22:50:29 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HARDWARE / PERF_COUNT_HW_INSTRUCTIONS
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[event8:base-stat]
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fd=8
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type=0
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config=1
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2017-10-09 21:07:12 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_INSTRUCTIONS
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[event9:base-stat]
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fd=9
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type=0
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config=4
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2017-10-09 21:07:12 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_MISSES
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[event10:base-stat]
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fd=10
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type=0
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config=5
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2017-10-09 21:07:12 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HW_CACHE /
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# PERF_COUNT_HW_CACHE_L1D << 0 |
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# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
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# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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[event11:base-stat]
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fd=11
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type=3
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config=0
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2017-10-09 21:07:12 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HW_CACHE /
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# PERF_COUNT_HW_CACHE_L1D << 0 |
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# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
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# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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[event12:base-stat]
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fd=12
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type=3
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config=65536
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2017-10-09 21:07:12 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HW_CACHE /
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# PERF_COUNT_HW_CACHE_LL << 0 |
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# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
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# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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[event13:base-stat]
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fd=13
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type=3
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config=2
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2017-10-09 21:07:12 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HW_CACHE,
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# PERF_COUNT_HW_CACHE_LL << 0 |
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# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
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# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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[event14:base-stat]
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fd=14
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type=3
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config=65538
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2017-10-09 21:07:12 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HW_CACHE,
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# PERF_COUNT_HW_CACHE_L1I << 0 |
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# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
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# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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[event15:base-stat]
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fd=15
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type=3
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config=1
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2017-07-03 22:50:29 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HW_CACHE,
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# PERF_COUNT_HW_CACHE_L1I << 0 |
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# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
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# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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[event16:base-stat]
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fd=16
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type=3
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config=65537
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2017-10-09 21:07:12 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HW_CACHE,
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# PERF_COUNT_HW_CACHE_DTLB << 0 |
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# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
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# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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[event17:base-stat]
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fd=17
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type=3
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config=3
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2017-10-09 21:07:12 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HW_CACHE,
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# PERF_COUNT_HW_CACHE_DTLB << 0 |
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# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
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# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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[event18:base-stat]
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fd=18
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type=3
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config=65539
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2017-10-09 21:07:12 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HW_CACHE,
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# PERF_COUNT_HW_CACHE_ITLB << 0 |
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# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
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# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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[event19:base-stat]
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fd=19
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type=3
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config=4
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2017-10-09 21:07:12 +08:00
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optional=1
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2012-10-31 06:02:04 +08:00
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# PERF_TYPE_HW_CACHE,
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# PERF_COUNT_HW_CACHE_ITLB << 0 |
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# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
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# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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[event20:base-stat]
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fd=20
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type=3
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config=65540
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2017-10-09 21:07:12 +08:00
|
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optional=1
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