2005-04-17 06:20:36 +08:00
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#
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# PCI configuration
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#
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2016-02-04 05:24:22 +08:00
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source "drivers/pci/pcie/Kconfig"
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PCI: Add pci_bus_addr_t
David Ahern reported that d63e2e1f3df9 ("sparc/PCI: Clip bridge windows
to fit in upstream windows") fails to boot on sparc/T5-8:
pci 0000:06:00.0: reg 0x184: can't handle BAR above 4GB (bus address 0x110204000)
The problem is that sparc64 assumed that dma_addr_t only needed to hold DMA
addresses, i.e., bus addresses returned via the DMA API (dma_map_single(),
etc.), while the PCI core assumed dma_addr_t could hold *any* bus address,
including raw BAR values. On sparc64, all DMA addresses fit in 32 bits, so
dma_addr_t is a 32-bit type. However, BAR values can be 64 bits wide, so
they don't fit in a dma_addr_t. d63e2e1f3df9 added new checking that
tripped over this mismatch.
Add pci_bus_addr_t, which is wide enough to hold any PCI bus address,
including both raw BAR values and DMA addresses. This will be 64 bits
on 64-bit platforms and on platforms with a 64-bit dma_addr_t. Then
dma_addr_t only needs to be wide enough to hold addresses from the DMA API.
[bhelgaas: changelog, bugzilla, Kconfig to ensure pci_bus_addr_t is at
least as wide as dma_addr_t, documentation]
Fixes: d63e2e1f3df9 ("sparc/PCI: Clip bridge windows to fit in upstream windows")
Fixes: 23b13bc76f35 ("PCI: Fail safely if we can't handle BARs larger than 4GB")
Link: http://lkml.kernel.org/r/CAE9FiQU1gJY1LYrxs+ma5LCTEEe4xmtjRG0aXJ9K_Tsu+m9Wuw@mail.gmail.com
Link: http://lkml.kernel.org/r/1427857069-6789-1-git-send-email-yinghai@kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=96231
Reported-by: David Ahern <david.ahern@oracle.com>
Tested-by: David Ahern <david.ahern@oracle.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: David S. Miller <davem@davemloft.net>
CC: stable@vger.kernel.org # v3.19+
2015-05-28 08:23:51 +08:00
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config PCI_BUS_ADDR_T_64BIT
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2015-09-03 00:17:29 +08:00
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def_bool y if (ARCH_DMA_ADDR_T_64BIT || 64BIT)
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PCI: Add pci_bus_addr_t
David Ahern reported that d63e2e1f3df9 ("sparc/PCI: Clip bridge windows
to fit in upstream windows") fails to boot on sparc/T5-8:
pci 0000:06:00.0: reg 0x184: can't handle BAR above 4GB (bus address 0x110204000)
The problem is that sparc64 assumed that dma_addr_t only needed to hold DMA
addresses, i.e., bus addresses returned via the DMA API (dma_map_single(),
etc.), while the PCI core assumed dma_addr_t could hold *any* bus address,
including raw BAR values. On sparc64, all DMA addresses fit in 32 bits, so
dma_addr_t is a 32-bit type. However, BAR values can be 64 bits wide, so
they don't fit in a dma_addr_t. d63e2e1f3df9 added new checking that
tripped over this mismatch.
Add pci_bus_addr_t, which is wide enough to hold any PCI bus address,
including both raw BAR values and DMA addresses. This will be 64 bits
on 64-bit platforms and on platforms with a 64-bit dma_addr_t. Then
dma_addr_t only needs to be wide enough to hold addresses from the DMA API.
[bhelgaas: changelog, bugzilla, Kconfig to ensure pci_bus_addr_t is at
least as wide as dma_addr_t, documentation]
Fixes: d63e2e1f3df9 ("sparc/PCI: Clip bridge windows to fit in upstream windows")
Fixes: 23b13bc76f35 ("PCI: Fail safely if we can't handle BARs larger than 4GB")
Link: http://lkml.kernel.org/r/CAE9FiQU1gJY1LYrxs+ma5LCTEEe4xmtjRG0aXJ9K_Tsu+m9Wuw@mail.gmail.com
Link: http://lkml.kernel.org/r/1427857069-6789-1-git-send-email-yinghai@kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=96231
Reported-by: David Ahern <david.ahern@oracle.com>
Tested-by: David Ahern <david.ahern@oracle.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: David S. Miller <davem@davemloft.net>
CC: stable@vger.kernel.org # v3.19+
2015-05-28 08:23:51 +08:00
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depends on PCI
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2005-04-17 06:20:36 +08:00
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config PCI_MSI
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bool "Message Signaled Interrupts (MSI and MSI-X)"
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depends on PCI
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2014-11-12 19:11:25 +08:00
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select GENERIC_MSI_IRQ
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2005-04-17 06:20:36 +08:00
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help
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This allows device drivers to enable MSI (Message Signaled
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Interrupts). Message Signaled Interrupts enable a device to
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generate an interrupt using an inbound Memory Write on its
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PCI bus instead of asserting a device IRQ pin.
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2006-03-06 13:33:34 +08:00
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Use of PCI MSI interrupts can be disabled at kernel boot time
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by using the 'pci=nomsi' option. This disables MSI for the
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entire system.
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2010-04-09 00:38:47 +08:00
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If you don't know what to do here, say Y.
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2005-04-17 06:20:36 +08:00
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2014-11-11 21:02:18 +08:00
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config PCI_MSI_IRQ_DOMAIN
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bool
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depends on PCI_MSI
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select GENERIC_MSI_IRQ_DOMAIN
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2005-04-17 06:20:36 +08:00
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config PCI_DEBUG
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bool "PCI Debugging"
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depends on PCI && DEBUG_KERNEL
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help
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Say Y here if you want the PCI core to produce a bunch of debug
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messages to the system log. Select this if you are having a
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problem with PCI support and want to see more of what is going on.
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When in doubt, say N.
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2012-02-24 11:23:32 +08:00
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config PCI_REALLOC_ENABLE_AUTO
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bool "Enable PCI resource re-allocation detection"
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depends on PCI
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help
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Say Y here if you want the PCI core to detect if PCI resource
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re-allocation needs to be enabled. You can always use pci=realloc=on
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or pci=realloc=off to override it. Note this feature is a no-op
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unless PCI_IOV support is also enabled; in that case it will
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automatically re-allocate PCI resources if SR-IOV BARs have not
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been allocated by the BIOS.
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When in doubt, say N.
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2008-11-26 13:17:13 +08:00
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config PCI_STUB
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tristate "PCI Stub driver"
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depends on PCI
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help
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Say Y or M here if you want be able to reserve a PCI device
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when it is going to be assigned to a guest operating system.
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When in doubt, say N.
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2010-08-03 09:31:05 +08:00
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config XEN_PCIDEV_FRONTEND
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tristate "Xen PCI Frontend"
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depends on PCI && X86 && XEN
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select PCI_XEN
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2010-12-11 11:33:15 +08:00
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select XEN_XENBUS_FRONTEND
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2010-08-03 09:31:05 +08:00
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default y
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help
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The PCI device frontend driver allows the kernel to import arbitrary
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PCI devices from a PCI backend to support PCI driver domains.
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2006-10-04 17:16:55 +08:00
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config HT_IRQ
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bool "Interrupts on hypertransport devices"
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default y
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2014-10-27 16:12:06 +08:00
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depends on PCI && X86_LOCAL_APIC
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2006-10-04 17:16:55 +08:00
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help
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This allows native hypertransport devices to use interrupts.
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If unsure say Y.
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2009-03-20 11:25:11 +08:00
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2011-09-27 21:57:13 +08:00
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config PCI_ATS
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bool
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2009-03-20 11:25:11 +08:00
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config PCI_IOV
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bool "PCI IOV support"
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depends on PCI
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2011-09-27 21:57:13 +08:00
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select PCI_ATS
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2009-03-20 11:25:11 +08:00
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help
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I/O Virtualization is a PCI feature supported by some devices
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which allows them to create virtual devices which share their
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physical resources.
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If unsure, say N.
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PCI hotplug: move IOAPIC support from acpiphp to ioapic driver
This patch moves PCI I/O APIC support from acpiphp to a separate driver.
Like pciehp and shpchp, acpiphp handles PCI hotplug, i.e., addition and
removal of PCI adapters. But in addition, acpiphp handles some ACPI
hotplug, such as the addition of new host bridges, and the I/O APIC
support was tangled up with that.
I don't think the I/O APIC support needs to be in acpiphp; PCI I/O APICs
usually appear as a function on a PCI host bridge, and we'll enumerate the
APIC before any of the devices behind the bridge that use it.
As far as I know, nobody actually uses I/O APIC hotplug. It depends on
acpi_register_ioapic(), which is only implemented for ia64, and I don't
think any vendors have supported I/O chassis hotplug yet.
Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
CC: Satoru Takeuchi <takeuchi_satoru@jp.fujitsu.com>
CC: MUNEDA Takahiro <muneda.takahiro@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-10-27 01:20:47 +08:00
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2011-09-27 21:57:15 +08:00
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config PCI_PRI
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bool "PCI PRI support"
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2011-10-30 23:35:07 +08:00
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depends on PCI
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2011-09-27 21:57:15 +08:00
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select PCI_ATS
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help
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PRI is the PCI Page Request Interface. It allows PCI devices that are
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behind an IOMMU to recover from page faults.
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If unsure, say N.
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2011-09-27 21:57:16 +08:00
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config PCI_PASID
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bool "PCI PASID support"
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depends on PCI
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select PCI_ATS
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help
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Process Address Space Identifiers (PASIDs) can be used by PCI devices
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to access more than one IO address space at the same time. To make
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use of this feature an IOMMU is required which also supports PASIDs.
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Select this option if you have such an IOMMU and want to compile the
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driver for it into your kernel.
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If unsure, say N.
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2011-03-30 00:45:57 +08:00
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config PCI_LABEL
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def_bool y if (DMI || ACPI)
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select NLS
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
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2016-02-17 05:56:23 +08:00
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config PCI_HYPERV
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tristate "Hyper-V PCI Frontend"
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depends on PCI && X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
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help
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The PCI device frontend driver allows the kernel to import arbitrary
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PCI devices from a PCI backend to support PCI driver domains.
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
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source "drivers/pci/host/Kconfig"
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