forked from luck/tmp_suning_uos_patched
364 lines
14 KiB
C
364 lines
14 KiB
C
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/*********************************************************************
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*
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* Filename: toshoboe.h
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* Version: 2.16
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* Description: Driver for the Toshiba OBOE (or type-O or 701)
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* FIR Chipset, also supports the DONAUOBOE (type-DO
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* or d01) FIR chipset which as far as I know is
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* register compatible.
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* Status: Experimental.
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* Author: James McKenzie <james@fishsoup.dhs.org>
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* Created at: Sat May 8 12:35:27 1999
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* Modified: 2.16 Martin Lucina <mato@kotelna.sk>
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* Modified: 2.16 Sat Jun 22 18:54:29 2002 (sync headers)
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* Modified: 2.17 Christian Gennerat <christian.gennerat@polytechnique.org>
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* Modified: 2.17 jeu sep 12 08:50:20 2002 (add lock to be used by spinlocks)
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*
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* Copyright (c) 1999 James McKenzie, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* Neither James McKenzie nor Cambridge University admit liability nor
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* provide warranty for any of this software. This material is
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* provided "AS-IS" and at no charge.
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*
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* Applicable Models : Libretto 100/110CT and many more.
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* Toshiba refers to this chip as the type-O IR port,
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* or the type-DO IR port.
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*
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* IrDA chip set list from Toshiba Computer Engineering Corp.
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* model method maker controler Version
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* Portege 320CT FIR,SIR Toshiba Oboe(Triangle)
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* Portege 3010CT FIR,SIR Toshiba Oboe(Sydney)
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* Portege 3015CT FIR,SIR Toshiba Oboe(Sydney)
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* Portege 3020CT FIR,SIR Toshiba Oboe(Sydney)
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* Portege 7020CT FIR,SIR ? ?
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*
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* Satell. 4090XCDT FIR,SIR ? ?
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*
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* Libretto 100CT FIR,SIR Toshiba Oboe
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* Libretto 1000CT FIR,SIR Toshiba Oboe
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*
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* TECRA750DVD FIR,SIR Toshiba Oboe(Triangle) REV ID=14h
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* TECRA780 FIR,SIR Toshiba Oboe(Sandlot) REV ID=32h,33h
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* TECRA750CDT FIR,SIR Toshiba Oboe(Triangle) REV ID=13h,14h
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* TECRA8000 FIR,SIR Toshiba Oboe(ISKUR) REV ID=23h
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*
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********************************************************************/
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/* The documentation for this chip is allegedly released */
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/* However I have not seen it, not have I managed to contact */
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/* anyone who has. HOWEVER the chip bears a striking resemblence */
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/* to the IrDA controller in the Toshiba RISC TMPR3922 chip */
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/* the documentation for this is freely available at */
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/* http://www.toshiba.com/taec/components/Generic/TMPR3922.shtml */
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/* The mapping between the registers in that document and the */
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/* Registers in the 701 oboe chip are as follows */
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/* 3922 reg 701 regs, by bit numbers */
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/* 7- 0 15- 8 24-16 31-25 */
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/* $28 0x0 0x1 */
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/* $2c SEE NOTE 1 */
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/* $30 0x6 0x7 */
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/* $34 0x8 0x9 SEE NOTE 2 */
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/* $38 0x10 0x11 */
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/* $3C 0xe SEE NOTE 3 */
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/* $40 0x12 0x13 */
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/* $44 0x14 0x15 */
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/* $48 0x16 0x17 */
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/* $4c 0x18 0x19 */
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/* $50 0x1a 0x1b */
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/* FIXME: could be 0x1b 0x1a here */
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/* $54 0x1d 0x1c */
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/* $5C 0xf SEE NOTE 4 */
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/* $130 SEE NOTE 5 */
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/* $134 SEE NOTE 6 */
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/* */
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/* NOTES: */
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/* 1. The pointer to ring is packed in most unceremoniusly */
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/* 701 Register Address bits (A9-A0 must be zero) */
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/* 0x4: A17 A16 A15 A14 A13 A12 A11 A10 */
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/* 0x5: A25 A24 A23 A22 A21 A20 A19 A18 */
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/* 0x2: 0 0 A31 A30 A29 A28 A27 A26 */
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/* */
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/* 2. The M$ drivers do a write 0x1 to 0x9, however the 3922 */
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/* documentation would suggest that a write of 0x1 to 0x8 */
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/* would be more appropriate. */
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/* */
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/* 3. This assignment is tenuous at best, register 0xe seems to */
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/* have bits arranged 0 0 0 R/W R/W R/W R/W R/W */
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/* if either of the lower two bits are set the chip seems to */
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/* switch off */
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/* */
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/* 4. Bits 7-4 seem to be different 4 seems just to be generic */
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/* receiver busy flag */
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/* */
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/* 5. and 6. The IER and ISR have a different bit assignment */
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/* The lower three bits of both read back as ones */
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/* ISR is register 0xc, IER is register 0xd */
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/* 7 6 5 4 3 2 1 0 */
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/* 0xc: TxDone RxDone TxUndr RxOver SipRcv 1 1 1 */
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/* 0xd: TxDone RxDone TxUndr RxOver SipRcv 1 1 1 */
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/* TxDone xmitt done (generated only if generate interrupt bit */
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/* is set in the ring) */
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/* RxDone recv completed (or other recv condition if you set it */
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/* up */
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/* TxUnder underflow in Transmit FIFO */
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/* RxOver overflow in Recv FIFO */
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/* SipRcv received serial gap (or other condition you set) */
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/* Interrupts are enabled by writing a one to the IER register */
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/* Interrupts are cleared by writting a one to the ISR register */
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/* */
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/* 6. The remaining registers: 0x6 and 0x3 appear to be */
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/* reserved parts of 16 or 32 bit registersthe remainder */
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/* 0xa 0xb 0x1e 0x1f could possibly be (by their behaviour) */
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/* the Unicast Filter register at $58. */
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/* */
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/* 7. While the core obviously expects 32 bit accesses all the */
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/* M$ drivers do 8 bit accesses, infact the Miniport ones */
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/* write and read back the byte serveral times (why?) */
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#ifndef TOSHOBOE_H
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#define TOSHOBOE_H
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/* Registers */
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#define OBOE_IO_EXTENT 0x1f
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/*Receive and transmit slot pointers */
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#define OBOE_REG(i) (i+(self->base))
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#define OBOE_RXSLOT OBOE_REG(0x0)
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#define OBOE_TXSLOT OBOE_REG(0x1)
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#define OBOE_SLOT_MASK 0x3f
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#define OBOE_TXRING_OFFSET 0x200
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#define OBOE_TXRING_OFFSET_IN_SLOTS 0x40
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/*pointer to the ring */
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#define OBOE_RING_BASE0 OBOE_REG(0x4)
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#define OBOE_RING_BASE1 OBOE_REG(0x5)
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#define OBOE_RING_BASE2 OBOE_REG(0x2)
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#define OBOE_RING_BASE3 OBOE_REG(0x3)
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/*Number of slots in the ring */
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#define OBOE_RING_SIZE OBOE_REG(0x7)
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#define OBOE_RING_SIZE_RX4 0x00
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#define OBOE_RING_SIZE_RX8 0x01
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#define OBOE_RING_SIZE_RX16 0x03
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#define OBOE_RING_SIZE_RX32 0x07
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#define OBOE_RING_SIZE_RX64 0x0f
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#define OBOE_RING_SIZE_TX4 0x00
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#define OBOE_RING_SIZE_TX8 0x10
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#define OBOE_RING_SIZE_TX16 0x30
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#define OBOE_RING_SIZE_TX32 0x70
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#define OBOE_RING_SIZE_TX64 0xf0
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#define OBOE_RING_MAX_SIZE 64
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/*Causes the gubbins to re-examine the ring */
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#define OBOE_PROMPT OBOE_REG(0x9)
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#define OBOE_PROMPT_BIT 0x1
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/* Interrupt Status Register */
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#define OBOE_ISR OBOE_REG(0xc)
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/* Interrupt Enable Register */
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#define OBOE_IER OBOE_REG(0xd)
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/* Interrupt bits for IER and ISR */
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#define OBOE_INT_TXDONE 0x80
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#define OBOE_INT_RXDONE 0x40
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#define OBOE_INT_TXUNDER 0x20
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#define OBOE_INT_RXOVER 0x10
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#define OBOE_INT_SIP 0x08
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#define OBOE_INT_MASK 0xf8
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/*Reset Register */
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#define OBOE_CONFIG1 OBOE_REG(0xe)
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#define OBOE_CONFIG1_RST 0x01
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#define OBOE_CONFIG1_DISABLE 0x02
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#define OBOE_CONFIG1_4 0x08
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#define OBOE_CONFIG1_8 0x08
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#define OBOE_CONFIG1_ON 0x8
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#define OBOE_CONFIG1_RESET 0xf
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#define OBOE_CONFIG1_OFF 0xe
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#define OBOE_STATUS OBOE_REG(0xf)
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#define OBOE_STATUS_RXBUSY 0x10
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#define OBOE_STATUS_FIRRX 0x04
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#define OBOE_STATUS_MIRRX 0x02
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#define OBOE_STATUS_SIRRX 0x01
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/*Speed control registers */
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#define OBOE_CONFIG0L OBOE_REG(0x10)
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#define OBOE_CONFIG0H OBOE_REG(0x11)
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#define OBOE_CONFIG0H_TXONLOOP 0x80 /*Transmit when looping (dangerous) */
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#define OBOE_CONFIG0H_LOOP 0x40 /*Loopback Tx->Rx */
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#define OBOE_CONFIG0H_ENTX 0x10 /*Enable Tx */
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#define OBOE_CONFIG0H_ENRX 0x08 /*Enable Rx */
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#define OBOE_CONFIG0H_ENDMAC 0x04 /*Enable/reset* the DMA controller */
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#define OBOE_CONFIG0H_RCVANY 0x02 /*DMA mode 1=bytes, 0=dwords */
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#define OBOE_CONFIG0L_CRC16 0x80 /*CRC 1=16 bit 0=32 bit */
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#define OBOE_CONFIG0L_ENFIR 0x40 /*Enable FIR */
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#define OBOE_CONFIG0L_ENMIR 0x20 /*Enable MIR */
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#define OBOE_CONFIG0L_ENSIR 0x10 /*Enable SIR */
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#define OBOE_CONFIG0L_ENSIRF 0x08 /*Enable SIR framer */
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#define OBOE_CONFIG0L_SIRTEST 0x04 /*Enable SIR framer in MIR and FIR */
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#define OBOE_CONFIG0L_INVERTTX 0x02 /*Invert Tx Line */
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#define OBOE_CONFIG0L_INVERTRX 0x01 /*Invert Rx Line */
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#define OBOE_BOF OBOE_REG(0x12)
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#define OBOE_EOF OBOE_REG(0x13)
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#define OBOE_ENABLEL OBOE_REG(0x14)
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#define OBOE_ENABLEH OBOE_REG(0x15)
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#define OBOE_ENABLEH_PHYANDCLOCK 0x80 /*Toggle low to copy config in */
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#define OBOE_ENABLEH_CONFIGERR 0x40
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#define OBOE_ENABLEH_FIRON 0x20
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#define OBOE_ENABLEH_MIRON 0x10
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#define OBOE_ENABLEH_SIRON 0x08
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#define OBOE_ENABLEH_ENTX 0x04
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#define OBOE_ENABLEH_ENRX 0x02
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#define OBOE_ENABLEH_CRC16 0x01
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#define OBOE_ENABLEL_BROADCAST 0x01
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#define OBOE_CURR_PCONFIGL OBOE_REG(0x16) /*Current config */
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#define OBOE_CURR_PCONFIGH OBOE_REG(0x17)
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#define OBOE_NEW_PCONFIGL OBOE_REG(0x18)
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#define OBOE_NEW_PCONFIGH OBOE_REG(0x19)
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#define OBOE_PCONFIGH_BAUDMASK 0xfc
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#define OBOE_PCONFIGH_WIDTHMASK 0x04
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#define OBOE_PCONFIGL_WIDTHMASK 0xe0
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#define OBOE_PCONFIGL_PREAMBLEMASK 0x1f
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#define OBOE_PCONFIG_BAUDMASK 0xfc00
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#define OBOE_PCONFIG_BAUDSHIFT 10
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#define OBOE_PCONFIG_WIDTHMASK 0x04e0
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#define OBOE_PCONFIG_WIDTHSHIFT 5
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#define OBOE_PCONFIG_PREAMBLEMASK 0x001f
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#define OBOE_PCONFIG_PREAMBLESHIFT 0
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#define OBOE_MAXLENL OBOE_REG(0x1a)
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#define OBOE_MAXLENH OBOE_REG(0x1b)
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#define OBOE_RXCOUNTH OBOE_REG(0x1c) /*Reset on recipt */
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#define OBOE_RXCOUNTL OBOE_REG(0x1d) /*of whole packet */
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/* The PCI ID of the OBOE chip */
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#ifndef PCI_DEVICE_ID_FIR701
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#define PCI_DEVICE_ID_FIR701 0x0701
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#endif
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#ifndef PCI_DEVICE_ID_FIRD01
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#define PCI_DEVICE_ID_FIRD01 0x0d01
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#endif
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struct OboeSlot
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{
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__u16 len; /*Tweleve bits of packet length */
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__u8 unused;
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__u8 control; /*Slot control/status see below */
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__u32 address; /*Slot buffer address */
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}
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__attribute__ ((packed));
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#define OBOE_NTASKS OBOE_TXRING_OFFSET_IN_SLOTS
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struct OboeRing
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{
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struct OboeSlot rx[OBOE_NTASKS];
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struct OboeSlot tx[OBOE_NTASKS];
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};
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#define OBOE_RING_LEN (sizeof(struct OboeRing))
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#define OBOE_CTL_TX_HW_OWNS 0x80 /*W/R This slot owned by the hardware */
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#define OBOE_CTL_TX_DISTX_CRC 0x40 /*W Disable CRC generation for [FM]IR */
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#define OBOE_CTL_TX_BAD_CRC 0x20 /*W Generate bad CRC */
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#define OBOE_CTL_TX_SIP 0x10 /*W Generate an SIP after xmittion */
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#define OBOE_CTL_TX_MKUNDER 0x08 /*W Generate an underrun error */
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#define OBOE_CTL_TX_RTCENTX 0x04 /*W Enable receiver and generate TXdone */
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/* After this slot is processed */
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#define OBOE_CTL_TX_UNDER 0x01 /*R Set by hardware to indicate underrun */
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#define OBOE_CTL_RX_HW_OWNS 0x80 /*W/R This slot owned by hardware */
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#define OBOE_CTL_RX_PHYERR 0x40 /*R Decoder error on receiption */
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#define OBOE_CTL_RX_CRCERR 0x20 /*R CRC error only set for [FM]IR */
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#define OBOE_CTL_RX_LENGTH 0x10 /*R Packet > max Rx length */
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#define OBOE_CTL_RX_OVER 0x08 /*R set to indicate an overflow */
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#define OBOE_CTL_RX_SIRBAD 0x04 /*R SIR had BOF in packet or ABORT sequence */
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#define OBOE_CTL_RX_RXEOF 0x02 /*R Finished receiving on this slot */
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struct toshoboe_cb
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{
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struct net_device *netdev; /* Yes! we are some kind of netdevice */
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struct net_device_stats stats;
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struct tty_driver ttydev;
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|
||
|
|
struct irlap_cb *irlap; /* The link layer we are binded to */
|
||
|
|
|
||
|
|
chipio_t io; /* IrDA controller information */
|
||
|
|
struct qos_info qos; /* QoS capabilities for this device */
|
||
|
|
|
||
|
|
__u32 flags; /* Interface flags */
|
||
|
|
|
||
|
|
struct pci_dev *pdev; /*PCI device */
|
||
|
|
int base; /*IO base */
|
||
|
|
|
||
|
|
|
||
|
|
int txpending; /*how many tx's are pending */
|
||
|
|
int txs, rxs; /*Which slots are we at */
|
||
|
|
|
||
|
|
int irdad; /*Driver under control of netdev end */
|
||
|
|
int async; /*Driver under control of async end */
|
||
|
|
|
||
|
|
|
||
|
|
int stopped; /*Stopped by some or other APM stuff */
|
||
|
|
|
||
|
|
int filter; /*In SIR mode do we want to receive
|
||
|
|
frames or byte ranges */
|
||
|
|
|
||
|
|
void *ringbuf; /*The ring buffer */
|
||
|
|
struct OboeRing *ring; /*The ring */
|
||
|
|
|
||
|
|
void *tx_bufs[OBOE_RING_MAX_SIZE]; /*The buffers */
|
||
|
|
void *rx_bufs[OBOE_RING_MAX_SIZE];
|
||
|
|
|
||
|
|
|
||
|
|
int speed; /*Current setting of the speed */
|
||
|
|
int new_speed; /*Set to request a speed change */
|
||
|
|
|
||
|
|
/* The spinlock protect critical parts of the driver.
|
||
|
|
* Locking is done like this :
|
||
|
|
* spin_lock_irqsave(&self->spinlock, flags);
|
||
|
|
* Releasing the lock :
|
||
|
|
* spin_unlock_irqrestore(&self->spinlock, flags);
|
||
|
|
*/
|
||
|
|
spinlock_t spinlock;
|
||
|
|
/* Used for the probe and diagnostics code */
|
||
|
|
int int_rx;
|
||
|
|
int int_tx;
|
||
|
|
int int_txunder;
|
||
|
|
int int_rxover;
|
||
|
|
int int_sip;
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
#endif
|