2019-08-13 19:13:32 +08:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0 */
|
dt-bindings: ti-sysc: Update binding for timers and capabilities
The ti-sysc binding does not yet describe the capabilities of the
interconnect target module. So to make the ti-sysc binding usable
for configuring the interconnect target module, we need to add few
more properties:
1. To detect between omap2 and omap4 timers, let's add compatibles
for them for "ti,sysc-omap2-timer" and,sysc-omap4-timer". This
makes it easier to pick up the already initialized system timers
later on
2. Let's add "ti,sysc-mask" for a mask of features supported by the
interconnect target module. This describes what we have available
in the various SYSCONFIG registers
3. Let's add "ti,sysc-midle" and "ti,sysc-sidle" lists for the master
and slave idle modes supported by the interconnect target module.
These describe the values available for MIDLE and SIDLE bits in
the SYSCONFIG registers
4. Some interconnect target modules need a short delay after reset
before they can be accessed, let's use "ti,sysc-delay-us" for
that
5. Let's add "ti,syss-mask" bit to describe the optional SYSSTATUS
register bits for reset done bits
6. Let's support the two existing custom quirk properties already
listed in Documentation/devicetree/bindings/arm/omap/omap.txt for
"ti,no-reset-on-init" and "ti,no-idle-on-init"
7. And finally, let's add a header for the binding for the dts
files and the driver to use
Cc: Benoît Cousson <bcousson@baylibre.com>
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Sakari Ailus <sakari.ailus@iki.fi>
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-12-14 08:36:47 +08:00
|
|
|
/* TI sysc interconnect target module defines */
|
|
|
|
|
|
|
|
|
|
/* Generic sysc found on omap2 and later, also known as type1 */
|
|
|
|
|
#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8)
|
|
|
|
|
#define SYSC_OMAP2_EMUFREE (1 << 5)
|
|
|
|
|
#define SYSC_OMAP2_ENAWAKEUP (1 << 2)
|
|
|
|
|
#define SYSC_OMAP2_SOFTRESET (1 << 1)
|
|
|
|
|
#define SYSC_OMAP2_AUTOIDLE (1 << 0)
|
|
|
|
|
|
|
|
|
|
/* Generic sysc found on omap4 and later, also known as type2 */
|
|
|
|
|
#define SYSC_OMAP4_DMADISABLE (1 << 16)
|
|
|
|
|
#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */
|
|
|
|
|
#define SYSC_OMAP4_SOFTRESET (1 << 0)
|
|
|
|
|
|
|
|
|
|
/* SmartReflex sysc found on 36xx and later */
|
|
|
|
|
#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26)
|
|
|
|
|
|
2018-07-10 00:48:38 +08:00
|
|
|
#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4)
|
|
|
|
|
|
2020-02-28 06:28:33 +08:00
|
|
|
/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */
|
|
|
|
|
#define SYSC_PRUSS_SUB_MWAIT (1 << 5)
|
|
|
|
|
#define SYSC_PRUSS_STANDBY_INIT (1 << 4)
|
|
|
|
|
|
dt-bindings: ti-sysc: Update binding for timers and capabilities
The ti-sysc binding does not yet describe the capabilities of the
interconnect target module. So to make the ti-sysc binding usable
for configuring the interconnect target module, we need to add few
more properties:
1. To detect between omap2 and omap4 timers, let's add compatibles
for them for "ti,sysc-omap2-timer" and,sysc-omap4-timer". This
makes it easier to pick up the already initialized system timers
later on
2. Let's add "ti,sysc-mask" for a mask of features supported by the
interconnect target module. This describes what we have available
in the various SYSCONFIG registers
3. Let's add "ti,sysc-midle" and "ti,sysc-sidle" lists for the master
and slave idle modes supported by the interconnect target module.
These describe the values available for MIDLE and SIDLE bits in
the SYSCONFIG registers
4. Some interconnect target modules need a short delay after reset
before they can be accessed, let's use "ti,sysc-delay-us" for
that
5. Let's add "ti,syss-mask" bit to describe the optional SYSSTATUS
register bits for reset done bits
6. Let's support the two existing custom quirk properties already
listed in Documentation/devicetree/bindings/arm/omap/omap.txt for
"ti,no-reset-on-init" and "ti,no-idle-on-init"
7. And finally, let's add a header for the binding for the dts
files and the driver to use
Cc: Benoît Cousson <bcousson@baylibre.com>
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Sakari Ailus <sakari.ailus@iki.fi>
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-12-14 08:36:47 +08:00
|
|
|
/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
|
|
|
|
|
#define SYSC_IDLE_FORCE 0
|
|
|
|
|
#define SYSC_IDLE_NO 1
|
|
|
|
|
#define SYSC_IDLE_SMART 2
|
|
|
|
|
#define SYSC_IDLE_SMART_WKUP 3
|