kernel_optimize_test/include/dt-bindings/clock/meson8-ddr-clkc.h

/* SPDX-License-Identifier: GPL-2.0 */

#define DDR_CLKID_DDR_PLL_DCO			0
#define DDR_CLKID_DDR_PLL			1
dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in the MMCBUS registers. There is no public documentation on this, but the GPL u-boot sources from the Amlogic BSP show that: - it uses the same XTAL input as the main clock controller - it contains a PLL which seems to be implemented just like the other PLLs in this SoC - there is a power-of-two PLL post-divider Add the documentation and header file for this DDR clock controller. Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> 2019-11-17 22:07:30 +08:00			`/* SPDX-License-Identifier: GPL-2.0 */`

			`#define DDR_CLKID_DDR_PLL_DCO 0`
			`#define DDR_CLKID_DDR_PLL 1`