forked from luck/tmp_suning_uos_patched
437 lines
12 KiB
C
437 lines
12 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Wendell Lin <wendell.lin@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT6779_H
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#define _DT_BINDINGS_CLK_MT6779_H
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/* TOPCKGEN */
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#define CLK_TOP_AXI 1
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#define CLK_TOP_MM 2
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#define CLK_TOP_CAM 3
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#define CLK_TOP_MFG 4
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#define CLK_TOP_CAMTG 5
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#define CLK_TOP_UART 6
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#define CLK_TOP_SPI 7
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#define CLK_TOP_MSDC50_0_HCLK 8
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#define CLK_TOP_MSDC50_0 9
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#define CLK_TOP_MSDC30_1 10
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#define CLK_TOP_MSDC30_2 11
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#define CLK_TOP_AUD 12
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#define CLK_TOP_AUD_INTBUS 13
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#define CLK_TOP_FPWRAP_ULPOSC 14
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#define CLK_TOP_SCP 15
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#define CLK_TOP_ATB 16
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#define CLK_TOP_SSPM 17
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#define CLK_TOP_DPI0 18
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#define CLK_TOP_SCAM 19
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#define CLK_TOP_AUD_1 20
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#define CLK_TOP_AUD_2 21
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#define CLK_TOP_DISP_PWM 22
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#define CLK_TOP_SSUSB_TOP_XHCI 23
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#define CLK_TOP_USB_TOP 24
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#define CLK_TOP_SPM 25
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#define CLK_TOP_I2C 26
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#define CLK_TOP_F52M_MFG 27
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#define CLK_TOP_SENINF 28
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#define CLK_TOP_DXCC 29
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#define CLK_TOP_CAMTG2 30
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#define CLK_TOP_AUD_ENG1 31
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#define CLK_TOP_AUD_ENG2 32
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#define CLK_TOP_FAES_UFSFDE 33
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#define CLK_TOP_FUFS 34
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#define CLK_TOP_IMG 35
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#define CLK_TOP_DSP 36
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#define CLK_TOP_DSP1 37
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#define CLK_TOP_DSP2 38
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#define CLK_TOP_IPU_IF 39
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#define CLK_TOP_CAMTG3 40
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#define CLK_TOP_CAMTG4 41
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#define CLK_TOP_PMICSPI 42
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#define CLK_TOP_MAINPLL_CK 43
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#define CLK_TOP_MAINPLL_D2 44
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#define CLK_TOP_MAINPLL_D3 45
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#define CLK_TOP_MAINPLL_D5 46
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#define CLK_TOP_MAINPLL_D7 47
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#define CLK_TOP_MAINPLL_D2_D2 48
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#define CLK_TOP_MAINPLL_D2_D4 49
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#define CLK_TOP_MAINPLL_D2_D8 50
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#define CLK_TOP_MAINPLL_D2_D16 51
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#define CLK_TOP_MAINPLL_D3_D2 52
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#define CLK_TOP_MAINPLL_D3_D4 53
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#define CLK_TOP_MAINPLL_D3_D8 54
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#define CLK_TOP_MAINPLL_D5_D2 55
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#define CLK_TOP_MAINPLL_D5_D4 56
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#define CLK_TOP_MAINPLL_D7_D2 57
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#define CLK_TOP_MAINPLL_D7_D4 58
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#define CLK_TOP_UNIVPLL_CK 59
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#define CLK_TOP_UNIVPLL_D2 60
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#define CLK_TOP_UNIVPLL_D3 61
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#define CLK_TOP_UNIVPLL_D5 62
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#define CLK_TOP_UNIVPLL_D7 63
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#define CLK_TOP_UNIVPLL_D2_D2 64
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#define CLK_TOP_UNIVPLL_D2_D4 65
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#define CLK_TOP_UNIVPLL_D2_D8 66
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#define CLK_TOP_UNIVPLL_D3_D2 67
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#define CLK_TOP_UNIVPLL_D3_D4 68
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#define CLK_TOP_UNIVPLL_D3_D8 69
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#define CLK_TOP_UNIVPLL_D5_D2 70
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#define CLK_TOP_UNIVPLL_D5_D4 71
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#define CLK_TOP_UNIVPLL_D5_D8 72
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#define CLK_TOP_APLL1_CK 73
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#define CLK_TOP_APLL1_D2 74
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#define CLK_TOP_APLL1_D4 75
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#define CLK_TOP_APLL1_D8 76
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#define CLK_TOP_APLL2_CK 77
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#define CLK_TOP_APLL2_D2 78
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#define CLK_TOP_APLL2_D4 79
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#define CLK_TOP_APLL2_D8 80
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#define CLK_TOP_TVDPLL_CK 81
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#define CLK_TOP_TVDPLL_D2 82
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#define CLK_TOP_TVDPLL_D4 83
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#define CLK_TOP_TVDPLL_D8 84
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#define CLK_TOP_TVDPLL_D16 85
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#define CLK_TOP_MSDCPLL_CK 86
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#define CLK_TOP_MSDCPLL_D2 87
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#define CLK_TOP_MSDCPLL_D4 88
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#define CLK_TOP_MSDCPLL_D8 89
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#define CLK_TOP_MSDCPLL_D16 90
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#define CLK_TOP_AD_OSC_CK 91
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#define CLK_TOP_OSC_D2 92
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#define CLK_TOP_OSC_D4 93
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#define CLK_TOP_OSC_D8 94
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#define CLK_TOP_OSC_D16 95
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#define CLK_TOP_F26M_CK_D2 96
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#define CLK_TOP_MFGPLL_CK 97
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#define CLK_TOP_UNIVP_192M_CK 98
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#define CLK_TOP_UNIVP_192M_D2 99
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#define CLK_TOP_UNIVP_192M_D4 100
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#define CLK_TOP_UNIVP_192M_D8 101
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#define CLK_TOP_UNIVP_192M_D16 102
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#define CLK_TOP_UNIVP_192M_D32 103
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#define CLK_TOP_MMPLL_CK 104
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#define CLK_TOP_MMPLL_D4 105
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#define CLK_TOP_MMPLL_D4_D2 106
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#define CLK_TOP_MMPLL_D4_D4 107
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#define CLK_TOP_MMPLL_D5 108
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#define CLK_TOP_MMPLL_D5_D2 109
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#define CLK_TOP_MMPLL_D5_D4 110
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#define CLK_TOP_MMPLL_D6 111
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#define CLK_TOP_MMPLL_D7 112
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#define CLK_TOP_CLK26M 113
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#define CLK_TOP_CLK13M 114
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#define CLK_TOP_ADSP 115
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#define CLK_TOP_DPMAIF 116
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#define CLK_TOP_VENC 117
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#define CLK_TOP_VDEC 118
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#define CLK_TOP_CAMTM 119
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#define CLK_TOP_PWM 120
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#define CLK_TOP_ADSPPLL_CK 121
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#define CLK_TOP_I2S0_M_SEL 122
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#define CLK_TOP_I2S1_M_SEL 123
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#define CLK_TOP_I2S2_M_SEL 124
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#define CLK_TOP_I2S3_M_SEL 125
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#define CLK_TOP_I2S4_M_SEL 126
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#define CLK_TOP_I2S5_M_SEL 127
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#define CLK_TOP_APLL12_DIV0 128
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#define CLK_TOP_APLL12_DIV1 129
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#define CLK_TOP_APLL12_DIV2 130
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#define CLK_TOP_APLL12_DIV3 131
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#define CLK_TOP_APLL12_DIV4 132
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#define CLK_TOP_APLL12_DIVB 133
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#define CLK_TOP_APLL12_DIV5 134
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#define CLK_TOP_IPE 135
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#define CLK_TOP_DPE 136
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#define CLK_TOP_CCU 137
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#define CLK_TOP_DSP3 138
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#define CLK_TOP_SENINF1 139
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#define CLK_TOP_SENINF2 140
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#define CLK_TOP_AUD_H 141
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#define CLK_TOP_CAMTG5 142
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#define CLK_TOP_TVDPLL_MAINPLL_D2_CK 143
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#define CLK_TOP_AD_OSC2_CK 144
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#define CLK_TOP_OSC2_D2 145
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#define CLK_TOP_OSC2_D3 146
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#define CLK_TOP_FMEM_466M_CK 147
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#define CLK_TOP_ADSPPLL_D4 148
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#define CLK_TOP_ADSPPLL_D5 149
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#define CLK_TOP_ADSPPLL_D6 150
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#define CLK_TOP_OSC_D10 151
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#define CLK_TOP_UNIVPLL_D3_D16 152
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#define CLK_TOP_NR_CLK 153
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/* APMIXED */
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#define CLK_APMIXED_ARMPLL_LL 1
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#define CLK_APMIXED_ARMPLL_BL 2
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#define CLK_APMIXED_ARMPLL_BB 3
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#define CLK_APMIXED_CCIPLL 4
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#define CLK_APMIXED_MAINPLL 5
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#define CLK_APMIXED_UNIV2PLL 6
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#define CLK_APMIXED_MSDCPLL 7
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#define CLK_APMIXED_ADSPPLL 8
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#define CLK_APMIXED_MMPLL 9
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#define CLK_APMIXED_MFGPLL 10
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#define CLK_APMIXED_TVDPLL 11
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#define CLK_APMIXED_APLL1 12
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#define CLK_APMIXED_APLL2 13
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#define CLK_APMIXED_SSUSB26M 14
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#define CLK_APMIXED_APPLL26M 15
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#define CLK_APMIXED_MIPIC0_26M 16
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#define CLK_APMIXED_MDPLLGP26M 17
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#define CLK_APMIXED_MM_F26M 18
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#define CLK_APMIXED_UFS26M 19
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#define CLK_APMIXED_MIPIC1_26M 20
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#define CLK_APMIXED_MEMPLL26M 21
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#define CLK_APMIXED_CLKSQ_LVPLL_26M 22
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#define CLK_APMIXED_MIPID0_26M 23
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#define CLK_APMIXED_MIPID1_26M 24
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#define CLK_APMIXED_NR_CLK 25
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/* CAMSYS */
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#define CLK_CAM_LARB10 1
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#define CLK_CAM_DFP_VAD 2
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#define CLK_CAM_LARB11 3
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#define CLK_CAM_LARB9 4
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#define CLK_CAM_CAM 5
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#define CLK_CAM_CAMTG 6
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#define CLK_CAM_SENINF 7
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#define CLK_CAM_CAMSV0 8
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#define CLK_CAM_CAMSV1 9
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#define CLK_CAM_CAMSV2 10
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#define CLK_CAM_CAMSV3 11
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#define CLK_CAM_CCU 12
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#define CLK_CAM_FAKE_ENG 13
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#define CLK_CAM_NR_CLK 14
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/* INFRA */
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#define CLK_INFRA_PMIC_TMR 1
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#define CLK_INFRA_PMIC_AP 2
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#define CLK_INFRA_PMIC_MD 3
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#define CLK_INFRA_PMIC_CONN 4
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#define CLK_INFRA_SCPSYS 5
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#define CLK_INFRA_SEJ 6
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#define CLK_INFRA_APXGPT 7
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#define CLK_INFRA_ICUSB 8
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#define CLK_INFRA_GCE 9
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#define CLK_INFRA_THERM 10
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#define CLK_INFRA_I2C0 11
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#define CLK_INFRA_I2C1 12
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#define CLK_INFRA_I2C2 13
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#define CLK_INFRA_I2C3 14
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#define CLK_INFRA_PWM_HCLK 15
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#define CLK_INFRA_PWM1 16
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#define CLK_INFRA_PWM2 17
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#define CLK_INFRA_PWM3 18
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#define CLK_INFRA_PWM4 19
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#define CLK_INFRA_PWM 20
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#define CLK_INFRA_UART0 21
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#define CLK_INFRA_UART1 22
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#define CLK_INFRA_UART2 23
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#define CLK_INFRA_UART3 24
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#define CLK_INFRA_GCE_26M 25
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#define CLK_INFRA_CQ_DMA_FPC 26
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#define CLK_INFRA_BTIF 27
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#define CLK_INFRA_SPI0 28
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#define CLK_INFRA_MSDC0 29
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#define CLK_INFRA_MSDC1 30
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#define CLK_INFRA_MSDC2 31
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#define CLK_INFRA_MSDC0_SCK 32
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#define CLK_INFRA_DVFSRC 33
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#define CLK_INFRA_GCPU 34
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#define CLK_INFRA_TRNG 35
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#define CLK_INFRA_AUXADC 36
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#define CLK_INFRA_CPUM 37
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#define CLK_INFRA_CCIF1_AP 38
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#define CLK_INFRA_CCIF1_MD 39
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#define CLK_INFRA_AUXADC_MD 40
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#define CLK_INFRA_MSDC1_SCK 41
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#define CLK_INFRA_MSDC2_SCK 42
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#define CLK_INFRA_AP_DMA 43
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#define CLK_INFRA_XIU 44
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#define CLK_INFRA_DEVICE_APC 45
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#define CLK_INFRA_CCIF_AP 46
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#define CLK_INFRA_DEBUGSYS 47
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#define CLK_INFRA_AUD 48
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#define CLK_INFRA_CCIF_MD 49
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#define CLK_INFRA_DXCC_SEC_CORE 50
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#define CLK_INFRA_DXCC_AO 51
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#define CLK_INFRA_DRAMC_F26M 52
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#define CLK_INFRA_IRTX 53
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#define CLK_INFRA_DISP_PWM 54
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#define CLK_INFRA_DPMAIF_CK 55
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#define CLK_INFRA_AUD_26M_BCLK 56
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#define CLK_INFRA_SPI1 57
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#define CLK_INFRA_I2C4 58
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#define CLK_INFRA_MODEM_TEMP_SHARE 59
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#define CLK_INFRA_SPI2 60
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#define CLK_INFRA_SPI3 61
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#define CLK_INFRA_UNIPRO_SCK 62
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#define CLK_INFRA_UNIPRO_TICK 63
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#define CLK_INFRA_UFS_MP_SAP_BCLK 64
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#define CLK_INFRA_MD32_BCLK 65
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#define CLK_INFRA_SSPM 66
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#define CLK_INFRA_UNIPRO_MBIST 67
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#define CLK_INFRA_SSPM_BUS_HCLK 68
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#define CLK_INFRA_I2C5 69
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#define CLK_INFRA_I2C5_ARBITER 70
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#define CLK_INFRA_I2C5_IMM 71
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#define CLK_INFRA_I2C1_ARBITER 72
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#define CLK_INFRA_I2C1_IMM 73
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#define CLK_INFRA_I2C2_ARBITER 74
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#define CLK_INFRA_I2C2_IMM 75
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#define CLK_INFRA_SPI4 76
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#define CLK_INFRA_SPI5 77
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#define CLK_INFRA_CQ_DMA 78
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#define CLK_INFRA_UFS 79
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#define CLK_INFRA_AES_UFSFDE 80
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#define CLK_INFRA_UFS_TICK 81
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#define CLK_INFRA_MSDC0_SELF 82
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#define CLK_INFRA_MSDC1_SELF 83
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#define CLK_INFRA_MSDC2_SELF 84
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#define CLK_INFRA_SSPM_26M_SELF 85
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#define CLK_INFRA_SSPM_32K_SELF 86
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#define CLK_INFRA_UFS_AXI 87
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#define CLK_INFRA_I2C6 88
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#define CLK_INFRA_AP_MSDC0 89
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#define CLK_INFRA_MD_MSDC0 90
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#define CLK_INFRA_USB 91
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#define CLK_INFRA_DEVMPU_BCLK 92
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#define CLK_INFRA_CCIF2_AP 93
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#define CLK_INFRA_CCIF2_MD 94
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#define CLK_INFRA_CCIF3_AP 95
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#define CLK_INFRA_CCIF3_MD 96
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#define CLK_INFRA_SEJ_F13M 97
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||
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#define CLK_INFRA_AES_BCLK 98
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#define CLK_INFRA_I2C7 99
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#define CLK_INFRA_I2C8 100
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||
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#define CLK_INFRA_FBIST2FPC 101
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#define CLK_INFRA_CCIF4_AP 102
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#define CLK_INFRA_CCIF4_MD 103
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#define CLK_INFRA_FADSP 104
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||
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#define CLK_INFRA_SSUSB_XHCI 105
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#define CLK_INFRA_SPI6 106
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#define CLK_INFRA_SPI7 107
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#define CLK_INFRA_NR_CLK 108
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||
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/* MFGCFG */
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#define CLK_MFGCFG_BG3D 1
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#define CLK_MFGCFG_NR_CLK 2
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||
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/* IMG */
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#define CLK_IMG_WPE_A 1
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#define CLK_IMG_MFB 2
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#define CLK_IMG_DIP 3
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#define CLK_IMG_LARB6 4
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#define CLK_IMG_LARB5 5
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#define CLK_IMG_NR_CLK 6
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|
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||
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/* IPE */
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#define CLK_IPE_LARB7 1
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#define CLK_IPE_LARB8 2
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#define CLK_IPE_SMI_SUBCOM 3
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#define CLK_IPE_FD 4
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#define CLK_IPE_FE 5
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#define CLK_IPE_RSC 6
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#define CLK_IPE_DPE 7
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#define CLK_IPE_NR_CLK 8
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||
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||
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/* MM_CONFIG */
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||
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#define CLK_MM_SMI_COMMON 1
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||
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#define CLK_MM_SMI_LARB0 2
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||
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#define CLK_MM_SMI_LARB1 3
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||
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#define CLK_MM_GALS_COMM0 4
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||
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#define CLK_MM_GALS_COMM1 5
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||
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#define CLK_MM_GALS_CCU2MM 6
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||
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#define CLK_MM_GALS_IPU12MM 7
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||
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#define CLK_MM_GALS_IMG2MM 8
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||
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#define CLK_MM_GALS_CAM2MM 9
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||
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#define CLK_MM_GALS_IPU2MM 10
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||
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#define CLK_MM_MDP_DL_TXCK 11
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||
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#define CLK_MM_IPU_DL_TXCK 12
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||
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#define CLK_MM_MDP_RDMA0 13
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||
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#define CLK_MM_MDP_RDMA1 14
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||
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#define CLK_MM_MDP_RSZ0 15
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||
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#define CLK_MM_MDP_RSZ1 16
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||
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#define CLK_MM_MDP_TDSHP 17
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||
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#define CLK_MM_MDP_WROT0 18
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||
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#define CLK_MM_FAKE_ENG 19
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||
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|
#define CLK_MM_DISP_OVL0 20
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||
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|
#define CLK_MM_DISP_OVL0_2L 21
|
||
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#define CLK_MM_DISP_OVL1_2L 22
|
||
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#define CLK_MM_DISP_RDMA0 23
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||
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|
#define CLK_MM_DISP_RDMA1 24
|
||
|
|
#define CLK_MM_DISP_WDMA0 25
|
||
|
|
#define CLK_MM_DISP_COLOR0 26
|
||
|
|
#define CLK_MM_DISP_CCORR0 27
|
||
|
|
#define CLK_MM_DISP_AAL0 28
|
||
|
|
#define CLK_MM_DISP_GAMMA0 29
|
||
|
|
#define CLK_MM_DISP_DITHER0 30
|
||
|
|
#define CLK_MM_DISP_SPLIT 31
|
||
|
|
#define CLK_MM_DSI0_MM_CK 32
|
||
|
|
#define CLK_MM_DSI0_IF_CK 33
|
||
|
|
#define CLK_MM_DPI_MM_CK 34
|
||
|
|
#define CLK_MM_DPI_IF_CK 35
|
||
|
|
#define CLK_MM_FAKE_ENG2 36
|
||
|
|
#define CLK_MM_MDP_DL_RX_CK 37
|
||
|
|
#define CLK_MM_IPU_DL_RX_CK 38
|
||
|
|
#define CLK_MM_26M 39
|
||
|
|
#define CLK_MM_MM_R2Y 40
|
||
|
|
#define CLK_MM_DISP_RSZ 41
|
||
|
|
#define CLK_MM_MDP_WDMA0 42
|
||
|
|
#define CLK_MM_MDP_AAL 43
|
||
|
|
#define CLK_MM_MDP_HDR 44
|
||
|
|
#define CLK_MM_DBI_MM_CK 45
|
||
|
|
#define CLK_MM_DBI_IF_CK 46
|
||
|
|
#define CLK_MM_MDP_WROT1 47
|
||
|
|
#define CLK_MM_DISP_POSTMASK0 48
|
||
|
|
#define CLK_MM_DISP_HRT_BW 49
|
||
|
|
#define CLK_MM_DISP_OVL_FBDC 50
|
||
|
|
#define CLK_MM_NR_CLK 51
|
||
|
|
|
||
|
|
/* VDEC_GCON */
|
||
|
|
#define CLK_VDEC_VDEC 1
|
||
|
|
#define CLK_VDEC_LARB1 2
|
||
|
|
#define CLK_VDEC_GCON_NR_CLK 3
|
||
|
|
|
||
|
|
/* VENC_GCON */
|
||
|
|
#define CLK_VENC_GCON_LARB 1
|
||
|
|
#define CLK_VENC_GCON_VENC 2
|
||
|
|
#define CLK_VENC_GCON_JPGENC 3
|
||
|
|
#define CLK_VENC_GCON_GALS 4
|
||
|
|
#define CLK_VENC_GCON_NR_CLK 5
|
||
|
|
|
||
|
|
/* AUD */
|
||
|
|
#define CLK_AUD_AFE 1
|
||
|
|
#define CLK_AUD_22M 2
|
||
|
|
#define CLK_AUD_24M 3
|
||
|
|
#define CLK_AUD_APLL2_TUNER 4
|
||
|
|
#define CLK_AUD_APLL_TUNER 5
|
||
|
|
#define CLK_AUD_TDM 6
|
||
|
|
#define CLK_AUD_ADC 7
|
||
|
|
#define CLK_AUD_DAC 8
|
||
|
|
#define CLK_AUD_DAC_PREDIS 9
|
||
|
|
#define CLK_AUD_TML 10
|
||
|
|
#define CLK_AUD_NLE 11
|
||
|
|
#define CLK_AUD_I2S1_BCLK_SW 12
|
||
|
|
#define CLK_AUD_I2S2_BCLK_SW 13
|
||
|
|
#define CLK_AUD_I2S3_BCLK_SW 14
|
||
|
|
#define CLK_AUD_I2S4_BCLK_SW 15
|
||
|
|
#define CLK_AUD_I2S5_BCLK_SW 16
|
||
|
|
#define CLK_AUD_CONN_I2S_ASRC 17
|
||
|
|
#define CLK_AUD_GENERAL1_ASRC 18
|
||
|
|
#define CLK_AUD_GENERAL2_ASRC 19
|
||
|
|
#define CLK_AUD_DAC_HIRES 20
|
||
|
|
#define CLK_AUD_PDN_ADDA6_ADC 21
|
||
|
|
#define CLK_AUD_ADC_HIRES 22
|
||
|
|
#define CLK_AUD_ADC_HIRES_TML 23
|
||
|
|
#define CLK_AUD_ADDA6_ADC_HIRES 24
|
||
|
|
#define CLK_AUD_3RD_DAC 25
|
||
|
|
#define CLK_AUD_3RD_DAC_PREDIS 26
|
||
|
|
#define CLK_AUD_3RD_DAC_TML 27
|
||
|
|
#define CLK_AUD_3RD_DAC_HIRES 28
|
||
|
|
#define CLK_AUD_NR_CLK 29
|
||
|
|
|
||
|
|
#endif /* _DT_BINDINGS_CLK_MT6779_H */
|