kernel_optimize_test/include/dt-bindings/phy/phy.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *
 * This header provides constants for the phy framework
 *
 * Copyright (C) 2014 STMicroelectronics
 * Author: Gabriel Fernandez <gabriel.fernandez@st.com>
 */

#ifndef _DT_BINDINGS_PHY
#define _DT_BINDINGS_PHY

#define PHY_NONE		0
#define PHY_TYPE_SATA		1
#define PHY_TYPE_PCIE		2
#define PHY_TYPE_USB2		3
#define PHY_TYPE_USB3		4
#define PHY_TYPE_UFS		5
#define PHY_TYPE_DP		6
#define PHY_TYPE_XPCS		7
#define PHY_TYPE_SGMII		8
#define PHY_TYPE_QSGMII		9

#endif /* _DT_BINDINGS_PHY */
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194 Based on 1 normalized pattern(s): license terms gnu general public license gpl version 2 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170027.447718015@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-29 00:57:21 +08:00			`/* SPDX-License-Identifier: GPL-2.0-only */`
phy: Add PHY header file for DT x Driver defines This provides the shared header file which will be reference from both PHY driver and its associated Device Tree node(s). Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> 2014-11-04 18:51:18 +08:00			`/*`
			`*`
			`* This header provides constants for the phy framework`
			`*`
			`* Copyright (C) 2014 STMicroelectronics`
			`* Author: Gabriel Fernandez <gabriel.fernandez@st.com>`
			`*/`

			`#ifndef _DT_BINDINGS_PHY`
			`#define _DT_BINDINGS_PHY`

phy: add support for USB cluster on the Armada 375 SoC The Armada 375 SoC comes with an USB2 host and device controller and an USB3 controller. The USB cluster control register allows to manage common features of both USB controllers. This commit adds a driver integrated in the generic PHY framework to control this USB cluster feature. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [ kishon@ti.com : Made it to use the updated devm_phy_create API and soem cosmentic changes in Kconfig file.] Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Jason Cooper <jason@lakedaemon.net> 2014-11-13 19:47:46 +08:00			`#define PHY_NONE 0`
phy: Add PHY header file for DT x Driver defines This provides the shared header file which will be reference from both PHY driver and its associated Device Tree node(s). Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> 2014-11-04 18:51:18 +08:00			`#define PHY_TYPE_SATA 1`
			`#define PHY_TYPE_PCIE 2`
			`#define PHY_TYPE_USB2 3`
			`#define PHY_TYPE_USB3 4`
dt-bindings: phy: Add PHY_TYPE_UFS definition Add definition for UFS phy type. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 2017-10-12 14:19:32 +08:00			`#define PHY_TYPE_UFS 5`
dt-bindings: phy: Add PHY_TYPE_DP definition Add definition for DisplayPort phy type. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 2020-01-08 16:30:07 +08:00			`#define PHY_TYPE_DP 6`
dt-bindings: phy: Add PHY_TYPE_XPCS definition Add definition for Ethernet PCS phy type. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Acked-by: Rob Herring <robh@kernel.org> Acked-By: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/6091f0d2a1046f1e3656d9e33b6cc433d5465eaf.1589868358.git.eswara.kota@linux.intel.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 2020-05-19 14:19:19 +08:00			`#define PHY_TYPE_XPCS 7`
dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed Processing System Gigabit Transceiver which provides PHY capabilities to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 2020-06-29 20:00:52 +08:00			`#define PHY_TYPE_SGMII 8`
dt-bindings: phy: Add PHY_TYPE_QSGMII definition Add definition for QSGMII phy type. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1600327846-9733-5-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 2020-09-17 15:30:37 +08:00			`#define PHY_TYPE_QSGMII 9`
phy: Add PHY header file for DT x Driver defines This provides the shared header file which will be reference from both PHY driver and its associated Device Tree node(s). Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> 2014-11-04 18:51:18 +08:00
			`#endif /* _DT_BINDINGS_PHY */`