forked from luck/tmp_suning_uos_patched
142 lines
6.8 KiB
C
142 lines
6.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Defines macros and constants for Renesas RZ/N1 pin controller pin
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* muxing functions.
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*/
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#ifndef __DT_BINDINGS_RZN1_PINCTRL_H
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#define __DT_BINDINGS_RZN1_PINCTRL_H
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#define RZN1_PINMUX(_gpio, _func) \
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(((_func) << 8) | (_gpio))
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/*
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* Given the different levels of muxing on the SoC, it was decided to
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* 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO
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* muxes are all represented by one single value.
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*
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* You can derive the hardware value pretty easily too, as
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* 0...9 are Level 1
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* 10...71 are Level 2. The Level 2 mux will be set to this
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* value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be
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* set accordingly.
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* 72...103 are for the 2 MDIO muxes.
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*/
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#define RZN1_FUNC_HIGHZ 0
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#define RZN1_FUNC_0L 1
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#define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2
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#define RZN1_FUNC_CLK_ETH_NAND 3
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#define RZN1_FUNC_QSPI 4
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#define RZN1_FUNC_SDIO 5
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#define RZN1_FUNC_LCD 6
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#define RZN1_FUNC_LCD_E 7
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#define RZN1_FUNC_MSEBIM 8
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#define RZN1_FUNC_MSEBIS 9
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#define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */
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#define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0)
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#define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1)
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#define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2)
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#define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3)
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#define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4)
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#define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5)
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#define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6)
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#define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7)
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#define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8)
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#define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9)
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#define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10)
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#define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11)
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#define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12)
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#define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13)
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#define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14)
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#define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15)
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#define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16)
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#define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17)
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#define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18)
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#define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19)
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#define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20)
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#define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21)
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#define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22)
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#define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23)
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#define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24)
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#define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25)
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#define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26)
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#define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27)
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#define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28)
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#define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29)
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#define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30)
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#define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31)
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#define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32)
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#define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33)
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#define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34)
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#define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35)
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#define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36)
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#define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37)
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#define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38)
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#define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39)
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#define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40)
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#define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41)
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#define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42)
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#define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43)
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#define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44)
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#define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45)
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#define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46)
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#define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47)
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#define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48)
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#define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49)
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#define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50)
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#define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51)
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#define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52)
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#define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53)
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#define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54)
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#define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55)
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#define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56)
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#define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57)
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#define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58)
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#define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59)
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#define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60)
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#define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61)
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#define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62)
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/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */
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#define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0)
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#define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1)
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#define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2)
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#define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3)
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#define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4)
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#define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5)
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#define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6)
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#define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7)
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/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
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#define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8)
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#define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9)
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#define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10)
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#define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11)
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#define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12)
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#define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13)
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#define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14)
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#define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15)
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/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */
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#define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16)
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#define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17)
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#define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18)
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#define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19)
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#define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20)
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#define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21)
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#define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22)
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#define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23)
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/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
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#define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24)
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#define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25)
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#define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26)
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#define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27)
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#define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28)
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#define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29)
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#define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30)
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#define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31)
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#define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32)
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#endif /* __DT_BINDINGS_RZN1_PINCTRL_H */
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