kernel_optimize_test/include/dt-bindings/reset/altr,rst-mgr-a10sr.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  Copyright Intel Corporation (C) 2017. All Rights Reserved
 *
 * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip
 *
 * Adapted from altr,rst-mgr-a10.h
 */

#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H

/* Peripheral PHY resets */
#define A10SR_RESET_ENET_HPS	0
#define A10SR_RESET_PCIE	1
#define A10SR_RESET_FILE	2
#define A10SR_RESET_BQSPI	3
#define A10SR_RESET_USB		4

#define A10SR_RESET_NUM		5

#endif
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-29 01:10:04 +08:00			`/* SPDX-License-Identifier: GPL-2.0-only */`
dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets The Arria10 System Resource Chip reset controller handles the Arria10 peripheral PHYs. This patch adds the offsets for these PHYs. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 2017-02-23 01:10:16 +08:00			`/*`
			`* Copyright Intel Corporation (C) 2017. All Rights Reserved`
			`*`
			`* Reset binding definitions for Altera Arria10 MAX5 System Resource Chip`
			`*`
			`* Adapted from altr,rst-mgr-a10.h`
			`*/`

			`#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H`
			`#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H`

			`/* Peripheral PHY resets */`
			`#define A10SR_RESET_ENET_HPS 0`
			`#define A10SR_RESET_PCIE 1`
			`#define A10SR_RESET_FILE 2`
			`#define A10SR_RESET_BQSPI 3`
			`#define A10SR_RESET_USB 4`

			`#define A10SR_RESET_NUM 5`

			`#endif`