kernel_optimize_test/include/dt-bindings/reset/mt8173-resets.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Flora Fu, MediaTek
 */

#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173
#define _DT_BINDINGS_RESET_CONTROLLER_MT8173

/* INFRACFG resets */
#define MT8173_INFRA_EMI_REG_RST        0
#define MT8173_INFRA_DRAMC0_A0_RST      1
#define MT8173_INFRA_APCIRQ_EINT_RST    3
#define MT8173_INFRA_APXGPT_RST         4
#define MT8173_INFRA_SCPSYS_RST         5
#define MT8173_INFRA_KP_RST             6
#define MT8173_INFRA_PMIC_WRAP_RST      7
#define MT8173_INFRA_MPIP_RST           8
#define MT8173_INFRA_CEC_RST            9
#define MT8173_INFRA_EMI_RST            32
#define MT8173_INFRA_DRAMC0_RST         34
#define MT8173_INFRA_APMIXEDSYS_RST     35
#define MT8173_INFRA_MIPI_DSI_RST       36
#define MT8173_INFRA_TRNG_RST           37
#define MT8173_INFRA_SYSIRQ_RST         38
#define MT8173_INFRA_MIPI_CSI_RST       39
#define MT8173_INFRA_GCE_FAXI_RST       40
#define MT8173_INFRA_MMIOMMURST         47


/*  PERICFG resets */
#define MT8173_PERI_UART0_SW_RST        0
#define MT8173_PERI_UART1_SW_RST        1
#define MT8173_PERI_UART2_SW_RST        2
#define MT8173_PERI_UART3_SW_RST        3
#define MT8173_PERI_IRRX_SW_RST         4
#define MT8173_PERI_PWM_SW_RST          8
#define MT8173_PERI_AUXADC_SW_RST       10
#define MT8173_PERI_DMA_SW_RST          11
#define MT8173_PERI_I2C6_SW_RST         13
#define MT8173_PERI_NFI_SW_RST          14
#define MT8173_PERI_THERM_SW_RST        16
#define MT8173_PERI_MSDC2_SW_RST        17
#define MT8173_PERI_MSDC3_SW_RST        18
#define MT8173_PERI_MSDC0_SW_RST        19
#define MT8173_PERI_MSDC1_SW_RST        20
#define MT8173_PERI_I2C0_SW_RST         22
#define MT8173_PERI_I2C1_SW_RST         23
#define MT8173_PERI_I2C2_SW_RST         24
#define MT8173_PERI_I2C3_SW_RST         25
#define MT8173_PERI_I2C4_SW_RST         26
#define MT8173_PERI_HDMI_SW_RST         29
#define MT8173_PERI_SPI0_SW_RST         33

#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-27 14:55:21 +08:00			`/* SPDX-License-Identifier: GPL-2.0-only */`
clk: mediatek: Add basic clocks for Mediatek MT8173. This patch adds basic clocks for MT8173, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2015-04-23 16:35:42 +08:00			`/*`
			`* Copyright (c) 2014 MediaTek Inc.`
			`* Author: Flora Fu, MediaTek`
			`*/`

			`#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173`
			`#define _DT_BINDINGS_RESET_CONTROLLER_MT8173`

			`/* INFRACFG resets */`
			`#define MT8173_INFRA_EMI_REG_RST 0`
			`#define MT8173_INFRA_DRAMC0_A0_RST 1`
			`#define MT8173_INFRA_APCIRQ_EINT_RST 3`
			`#define MT8173_INFRA_APXGPT_RST 4`
			`#define MT8173_INFRA_SCPSYS_RST 5`
			`#define MT8173_INFRA_KP_RST 6`
			`#define MT8173_INFRA_PMIC_WRAP_RST 7`
			`#define MT8173_INFRA_MPIP_RST 8`
			`#define MT8173_INFRA_CEC_RST 9`
			`#define MT8173_INFRA_EMI_RST 32`
			`#define MT8173_INFRA_DRAMC0_RST 34`
			`#define MT8173_INFRA_APMIXEDSYS_RST 35`
			`#define MT8173_INFRA_MIPI_DSI_RST 36`
			`#define MT8173_INFRA_TRNG_RST 37`
			`#define MT8173_INFRA_SYSIRQ_RST 38`
			`#define MT8173_INFRA_MIPI_CSI_RST 39`
			`#define MT8173_INFRA_GCE_FAXI_RST 40`
			`#define MT8173_INFRA_MMIOMMURST 47`


			`/* PERICFG resets */`
			`#define MT8173_PERI_UART0_SW_RST 0`
			`#define MT8173_PERI_UART1_SW_RST 1`
			`#define MT8173_PERI_UART2_SW_RST 2`
			`#define MT8173_PERI_UART3_SW_RST 3`
			`#define MT8173_PERI_IRRX_SW_RST 4`
			`#define MT8173_PERI_PWM_SW_RST 8`
			`#define MT8173_PERI_AUXADC_SW_RST 10`
			`#define MT8173_PERI_DMA_SW_RST 11`
			`#define MT8173_PERI_I2C6_SW_RST 13`
			`#define MT8173_PERI_NFI_SW_RST 14`
			`#define MT8173_PERI_THERM_SW_RST 16`
			`#define MT8173_PERI_MSDC2_SW_RST 17`
			`#define MT8173_PERI_MSDC3_SW_RST 18`
			`#define MT8173_PERI_MSDC0_SW_RST 19`
			`#define MT8173_PERI_MSDC1_SW_RST 20`
			`#define MT8173_PERI_I2C0_SW_RST 22`
			`#define MT8173_PERI_I2C1_SW_RST 23`
			`#define MT8173_PERI_I2C2_SW_RST 24`
			`#define MT8173_PERI_I2C3_SW_RST 25`
			`#define MT8173_PERI_I2C4_SW_RST 26`
			`#define MT8173_PERI_HDMI_SW_RST 29`
			`#define MT8173_PERI_SPI0_SW_RST 33`

			`#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */`