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kernel_optimize_test/include/dt-bindings/dma/at91.h

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ARM: at91: dt: add header to define at_hdmac configuration DMA-cell content is a concatenation of several values. In order to keep this stuff human readable, macros are introduced. The values for the FIFO configuration are not the same as the ones used in the configuration register in order to keep backward compatibility. Most devices use the half FIFO configuration but USART ones have to use the ASAP configuration. This parameter was not initially planed to be into the at91 dma dt binding. The third cell will be used to store this parameter, it will become a concatenation of the FIFO configuration and of the peripheral ID. In order to keep backward compatibility i.e. FIFO configuration is equal to 0, we have to perform a translation since the value to put in the register to set half FIFO is 1. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-06-13 16:39:38 +08:00
/*
* This header provides macros for at91 dma bindings.
*
* Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
*
* GPLv2 only
*/
#ifndef __DT_BINDINGS_AT91_DMA_H__
#define __DT_BINDINGS_AT91_DMA_H__
dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver New atmel DMA controller known as XDMAC, introduced with SAMA5D4 devices. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-10-22 23:22:18 +08:00
/* ---------- HDMAC ---------- */
ARM: at91: dt: add header to define at_hdmac configuration DMA-cell content is a concatenation of several values. In order to keep this stuff human readable, macros are introduced. The values for the FIFO configuration are not the same as the ones used in the configuration register in order to keep backward compatibility. Most devices use the half FIFO configuration but USART ones have to use the ASAP configuration. This parameter was not initially planed to be into the at91 dma dt binding. The third cell will be used to store this parameter, it will become a concatenation of the FIFO configuration and of the peripheral ID. In order to keep backward compatibility i.e. FIFO configuration is equal to 0, we have to perform a translation since the value to put in the register to set half FIFO is 1. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-06-13 16:39:38 +08:00
/*
* Source and/or destination peripheral ID
*/
#define AT91_DMA_CFG_PER_ID_MASK (0xff)
#define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK)
/*
* FIFO configuration: it defines when a request is serviced.
*/
#define AT91_DMA_CFG_FIFOCFG_OFFSET (8)
#define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET)
#define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */
#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */
#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */
dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver New atmel DMA controller known as XDMAC, introduced with SAMA5D4 devices. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-10-22 23:22:18 +08:00
/* ---------- XDMAC ---------- */
#define AT91_XDMAC_DT_MEM_IF_MASK (0x1)
#define AT91_XDMAC_DT_MEM_IF_OFFSET (13)
#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \
<< AT91_XDMAC_DT_MEM_IF_OFFSET)
#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
& AT91_XDMAC_DT_MEM_IF_MASK)
#define AT91_XDMAC_DT_PER_IF_MASK (0x1)
#define AT91_XDMAC_DT_PER_IF_OFFSET (14)
#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \
<< AT91_XDMAC_DT_PER_IF_OFFSET)
#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
& AT91_XDMAC_DT_PER_IF_MASK)
#define AT91_XDMAC_DT_PERID_MASK (0x7f)
#define AT91_XDMAC_DT_PERID_OFFSET (24)
#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \
<< AT91_XDMAC_DT_PERID_OFFSET)
#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
& AT91_XDMAC_DT_PERID_MASK)
ARM: at91: dt: add header to define at_hdmac configuration DMA-cell content is a concatenation of several values. In order to keep this stuff human readable, macros are introduced. The values for the FIFO configuration are not the same as the ones used in the configuration register in order to keep backward compatibility. Most devices use the half FIFO configuration but USART ones have to use the ASAP configuration. This parameter was not initially planed to be into the at91 dma dt binding. The third cell will be used to store this parameter, it will become a concatenation of the FIFO configuration and of the peripheral ID. In order to keep backward compatibility i.e. FIFO configuration is equal to 0, we have to perform a translation since the value to put in the register to set half FIFO is 1. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-06-13 16:39:38 +08:00
#endif /* __DT_BINDINGS_AT91_DMA_H__ */
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