kernel_optimize_test/include/dt-bindings/memory/tegra124-mc.h

#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
#define DT_BINDINGS_MEMORY_TEGRA124_MC_H

#define TEGRA_SWGROUP_PTC	0
#define TEGRA_SWGROUP_DC	1
#define TEGRA_SWGROUP_DCB	2
#define TEGRA_SWGROUP_AFI	3
#define TEGRA_SWGROUP_AVPC	4
#define TEGRA_SWGROUP_HDA	5
#define TEGRA_SWGROUP_HC	6
#define TEGRA_SWGROUP_MSENC	7
#define TEGRA_SWGROUP_PPCS	8
#define TEGRA_SWGROUP_SATA	9
#define TEGRA_SWGROUP_VDE	10
#define TEGRA_SWGROUP_MPCORELP	11
#define TEGRA_SWGROUP_MPCORE	12
#define TEGRA_SWGROUP_ISP2	13
#define TEGRA_SWGROUP_XUSB_HOST	14
#define TEGRA_SWGROUP_XUSB_DEV	15
#define TEGRA_SWGROUP_ISP2B	16
#define TEGRA_SWGROUP_TSEC	17
#define TEGRA_SWGROUP_A9AVP	18
#define TEGRA_SWGROUP_GPU	19
#define TEGRA_SWGROUP_SDMMC1A	20
#define TEGRA_SWGROUP_SDMMC2A	21
#define TEGRA_SWGROUP_SDMMC3A	22
#define TEGRA_SWGROUP_SDMMC4A	23
#define TEGRA_SWGROUP_VIC	24
#define TEGRA_SWGROUP_VI	25

#endif
memory: Add NVIDIA Tegra memory controller support The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements. This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead. The Tegra SMMU operates on memory clients and SWGROUPs. A memory client is a unidirectional, special-purpose DMA master. A SWGROUP represents a set of memory clients that form a logical functional unit corresponding to a single device. Typically a device has two clients: one client for read transactions and one client for write transactions, but there are also devices that have only read clients, but many of them (such as the display controllers). Because there is no 1:1 relationship between memory clients and devices the driver keeps a table of memory clients and the SWGROUPs that they belong to per SoC. Note that this is an exception and due to the fact that the SMMU is tightly integrated with the rest of the Tegra SoC. The use of these tables is discouraged in drivers for generic IOMMU devices such as the ARM SMMU because the same IOMMU could be used in any number of SoCs and keeping such tables for each SoC would not scale. Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com> 2014-04-16 15:24:44 +08:00			`#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H`
			`#define DT_BINDINGS_MEMORY_TEGRA124_MC_H`

			`#define TEGRA_SWGROUP_PTC 0`
			`#define TEGRA_SWGROUP_DC 1`
			`#define TEGRA_SWGROUP_DCB 2`
			`#define TEGRA_SWGROUP_AFI 3`
			`#define TEGRA_SWGROUP_AVPC 4`
			`#define TEGRA_SWGROUP_HDA 5`
			`#define TEGRA_SWGROUP_HC 6`
			`#define TEGRA_SWGROUP_MSENC 7`
			`#define TEGRA_SWGROUP_PPCS 8`
			`#define TEGRA_SWGROUP_SATA 9`
			`#define TEGRA_SWGROUP_VDE 10`
			`#define TEGRA_SWGROUP_MPCORELP 11`
			`#define TEGRA_SWGROUP_MPCORE 12`
			`#define TEGRA_SWGROUP_ISP2 13`
			`#define TEGRA_SWGROUP_XUSB_HOST 14`
			`#define TEGRA_SWGROUP_XUSB_DEV 15`
			`#define TEGRA_SWGROUP_ISP2B 16`
			`#define TEGRA_SWGROUP_TSEC 17`
			`#define TEGRA_SWGROUP_A9AVP 18`
			`#define TEGRA_SWGROUP_GPU 19`
			`#define TEGRA_SWGROUP_SDMMC1A 20`
			`#define TEGRA_SWGROUP_SDMMC2A 21`
			`#define TEGRA_SWGROUP_SDMMC3A 22`
			`#define TEGRA_SWGROUP_SDMMC4A 23`
			`#define TEGRA_SWGROUP_VIC 24`
			`#define TEGRA_SWGROUP_VI 25`

			`#endif`