forked from luck/tmp_suning_uos_patched
drm/vc4: Add support for the transposer block
The transposer block is providing support for mem-to-mem composition, which is exposed as a drm_writeback connector in DRM. Add a driver to support this feature. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/20180703075022.15138-9-boris.brezillon@bootlin.com
This commit is contained in:
Boris Brezillon
Boris Brezillon
parent
1ebe99a75e
commit
008095e065
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@ -74,6 +74,12 @@ Required properties for DSI:
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The 3 clocks output from the DSI analog PHY: dsi[01]_byte,
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dsi[01]_ddr2, and dsi[01]_ddr
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Required properties for the TXP (writeback) block:
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- compatible: Should be "brcm,bcm2835-txp"
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- reg: Physical base address and length of the TXP block's registers
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- interrupts: The interrupt number
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See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
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[1] Documentation/devicetree/bindings/media/video-interfaces.txt
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Example:
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@ -19,6 +19,7 @@ vc4-y := \
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vc4_plane.o \
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vc4_render_cl.o \
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vc4_trace_points.o \
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vc4_txp.o \
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vc4_v3d.o \
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vc4_validate.o \
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vc4_validate_shaders.o
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@ -46,6 +46,8 @@ struct vc4_crtc_state {
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struct drm_crtc_state base;
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/* Dlist area for this CRTC configuration. */
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struct drm_mm_node mm;
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bool feed_txp;
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bool txp_armed;
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};
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static inline struct vc4_crtc_state *
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@ -324,10 +326,8 @@ static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
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return NULL;
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}
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static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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static void vc4_crtc_config_pv(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
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struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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@ -338,12 +338,6 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
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vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
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u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
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bool debug_dump_regs = false;
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
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vc4_crtc_dump_regs(vc4_crtc);
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}
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/* Reset the PV fifo. */
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CRTC_WRITE(PV_CONTROL, 0);
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@ -419,6 +413,49 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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PV_CONTROL_CLK_SELECT) |
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PV_CONTROL_FIFO_CLR |
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PV_CONTROL_EN);
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}
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static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
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struct drm_display_mode *mode = &crtc->state->adjusted_mode;
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bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
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bool debug_dump_regs = false;
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
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vc4_crtc_dump_regs(vc4_crtc);
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}
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if (vc4_crtc->channel == 2) {
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u32 dispctrl;
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u32 dsp3_mux;
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/*
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* SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
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* FIFO X'.
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* SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
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*
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* DSP3 is connected to FIFO2 unless the transposer is
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* enabled. In this case, FIFO 2 is directly accessed by the
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* TXP IP, and we need to disable the FIFO2 -> pixelvalve1
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* route.
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*/
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if (vc4_state->feed_txp)
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dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
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else
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dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
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dispctrl = HVS_READ(SCALER_DISPCTRL) &
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~SCALER_DISPCTRL_DSP3_MUX_MASK;
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HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
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}
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if (!vc4_state->feed_txp)
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vc4_crtc_config_pv(crtc);
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HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
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SCALER_DISPBKGND_AUTOHS |
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@ -499,6 +536,13 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
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}
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}
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void vc4_crtc_txp_armed(struct drm_crtc_state *state)
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{
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
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vc4_state->txp_armed = true;
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}
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static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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@ -514,8 +558,11 @@ static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
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WARN_ON(drm_crtc_vblank_get(crtc) != 0);
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spin_lock_irqsave(&dev->event_lock, flags);
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vc4_crtc->event = crtc->state->event;
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crtc->state->event = NULL;
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if (!vc4_state->feed_txp || vc4_state->txp_armed) {
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vc4_crtc->event = crtc->state->event;
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crtc->state->event = NULL;
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}
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HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
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vc4_state->mm.start);
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@ -533,8 +580,8 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct drm_crtc_state *state = crtc->state;
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struct drm_display_mode *mode = &state->adjusted_mode;
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
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struct drm_display_mode *mode = &crtc->state->adjusted_mode;
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require_hvs_enabled(dev);
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@ -546,15 +593,21 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
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/* Turn on the scaler, which will wait for vstart to start
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* compositing.
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* When feeding the transposer, we should operate in oneshot
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* mode.
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*/
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HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
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VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
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VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
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SCALER_DISPCTRLX_ENABLE);
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SCALER_DISPCTRLX_ENABLE |
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(vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
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/* Turn on the pixel valve, which will emit the vstart signal. */
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CRTC_WRITE(PV_V_CONTROL,
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CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
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/* When feeding the transposer block the pixelvalve is unneeded and
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* should not be enabled.
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*/
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if (!vc4_state->feed_txp)
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CRTC_WRITE(PV_V_CONTROL,
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CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
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}
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static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
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@ -579,8 +632,10 @@ static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
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struct drm_plane *plane;
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unsigned long flags;
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const struct drm_plane_state *plane_state;
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struct drm_connector *conn;
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struct drm_connector_state *conn_state;
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u32 dlist_count = 0;
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int ret;
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int ret, i;
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/* The pixelvalve can only feed one encoder (and encoders are
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* 1:1 with connectors.)
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@ -600,6 +655,24 @@ static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
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if (ret)
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return ret;
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for_each_new_connector_in_state(state->state, conn, conn_state, i) {
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if (conn_state->crtc != crtc)
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continue;
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/* The writeback connector is implemented using the transposer
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* block which is directly taking its data from the HVS FIFO.
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*/
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if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) {
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state->no_vblank = true;
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vc4_state->feed_txp = true;
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} else {
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state->no_vblank = false;
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vc4_state->feed_txp = false;
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}
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break;
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}
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return 0;
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}
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@ -713,7 +786,8 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
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spin_lock_irqsave(&dev->event_lock, flags);
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if (vc4_crtc->event &&
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(vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
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(vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
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vc4_state->feed_txp)) {
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drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
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vc4_crtc->event = NULL;
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drm_crtc_vblank_put(crtc);
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@ -721,6 +795,13 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
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{
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crtc->t_vblank = ktime_get();
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drm_crtc_handle_vblank(&crtc->base);
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vc4_crtc_handle_page_flip(crtc);
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}
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static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
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{
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struct vc4_crtc *vc4_crtc = data;
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@ -728,10 +809,8 @@ static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
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irqreturn_t ret = IRQ_NONE;
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if (stat & PV_INT_VFP_START) {
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vc4_crtc->t_vblank = ktime_get();
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CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
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drm_crtc_handle_vblank(&vc4_crtc->base);
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vc4_crtc_handle_page_flip(vc4_crtc);
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vc4_crtc_handle_vblank(vc4_crtc);
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ret = IRQ_HANDLED;
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}
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@ -884,12 +963,15 @@ static int vc4_page_flip(struct drm_crtc *crtc,
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static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
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{
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struct vc4_crtc_state *vc4_state;
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struct vc4_crtc_state *vc4_state, *old_vc4_state;
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vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
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if (!vc4_state)
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return NULL;
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old_vc4_state = to_vc4_crtc_state(crtc->state);
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vc4_state->feed_txp = old_vc4_state->feed_txp;
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__drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
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return &vc4_state->base;
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}
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@ -987,9 +1069,17 @@ static void vc4_set_crtc_possible_masks(struct drm_device *drm,
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struct drm_encoder *encoder;
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drm_for_each_encoder(encoder, drm) {
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struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
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struct vc4_encoder *vc4_encoder;
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int i;
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/* HVS FIFO2 can feed the TXP IP. */
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if (crtc_data->hvs_channel == 2 &&
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encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
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encoder->possible_crtcs |= drm_crtc_mask(crtc);
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continue;
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}
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vc4_encoder = to_vc4_encoder(encoder);
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for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
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if (vc4_encoder->type == encoder_types[i]) {
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vc4_encoder->clock_select = i;
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@ -21,6 +21,7 @@ static const struct drm_info_list vc4_debugfs_list[] = {
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{"dsi1_regs", vc4_dsi_debugfs_regs, 0, (void *)(uintptr_t)1},
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{"hdmi_regs", vc4_hdmi_debugfs_regs, 0},
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{"vec_regs", vc4_vec_debugfs_regs, 0},
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{"txp_regs", vc4_txp_debugfs_regs, 0},
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{"hvs_regs", vc4_hvs_debugfs_regs, 0},
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{"crtc0_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)0},
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{"crtc1_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)1},
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@ -344,6 +344,7 @@ static struct platform_driver *const component_drivers[] = {
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&vc4_vec_driver,
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&vc4_dpi_driver,
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&vc4_dsi_driver,
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&vc4_txp_driver,
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&vc4_hvs_driver,
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&vc4_crtc_driver,
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&vc4_v3d_driver,
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@ -73,6 +73,7 @@ struct vc4_dev {
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struct vc4_dpi *dpi;
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struct vc4_dsi *dsi1;
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struct vc4_vec *vec;
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struct vc4_txp *txp;
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struct vc4_hang_state *hang_state;
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@ -698,6 +699,8 @@ bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
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bool in_vblank_irq, int *vpos, int *hpos,
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ktime_t *stime, ktime_t *etime,
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const struct drm_display_mode *mode);
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void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
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void vc4_crtc_txp_armed(struct drm_crtc_state *state);
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/* vc4_debugfs.c */
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int vc4_debugfs_init(struct drm_minor *minor);
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@ -745,6 +748,10 @@ int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
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extern struct platform_driver vc4_vec_driver;
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int vc4_vec_debugfs_regs(struct seq_file *m, void *unused);
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/* vc4_txp.c */
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extern struct platform_driver vc4_txp_driver;
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int vc4_txp_debugfs_regs(struct seq_file *m, void *unused);
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/* vc4_irq.c */
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irqreturn_t vc4_irq(int irq, void *arg);
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void vc4_irq_preinstall(struct drm_device *dev);
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477
drivers/gpu/drm/vc4/vc4_txp.c
Normal file
477
drivers/gpu/drm/vc4/vc4_txp.c
Normal file
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@ -0,0 +1,477 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright © 2018 Broadcom
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Boris Brezillon <boris.brezillon@bootlin.com>
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*/
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_writeback.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/of_graph.h>
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#include <linux/of_platform.h>
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#include <linux/pm_runtime.h>
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#include "vc4_drv.h"
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#include "vc4_regs.h"
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/* Base address of the output. Raster formats must be 4-byte aligned,
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* T and LT must be 16-byte aligned or maybe utile-aligned (docs are
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* inconsistent, but probably utile).
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*/
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#define TXP_DST_PTR 0x00
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/* Pitch in bytes for raster images, 16-byte aligned. For tiled, it's
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* the width in tiles.
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*/
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#define TXP_DST_PITCH 0x04
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/* For T-tiled imgaes, DST_PITCH should be the number of tiles wide,
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* shifted up.
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*/
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# define TXP_T_TILE_WIDTH_SHIFT 7
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/* For LT-tiled images, DST_PITCH should be the number of utiles wide,
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* shifted up.
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*/
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# define TXP_LT_TILE_WIDTH_SHIFT 4
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/* Pre-rotation width/height of the image. Must match HVS config.
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*
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* If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit
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* and width/height must be tile or utile-aligned as appropriate. If
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* transposing (rotating), width is limited to 1920.
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*
|
||||
* Height is limited to various numbers between 4088 and 4095. I'd
|
||||
* just use 4088 to be safe.
|
||||
*/
|
||||
#define TXP_DIM 0x08
|
||||
# define TXP_HEIGHT_SHIFT 16
|
||||
# define TXP_HEIGHT_MASK GENMASK(31, 16)
|
||||
# define TXP_WIDTH_SHIFT 0
|
||||
# define TXP_WIDTH_MASK GENMASK(15, 0)
|
||||
|
||||
#define TXP_DST_CTRL 0x0c
|
||||
/* These bits are set to 0x54 */
|
||||
#define TXP_PILOT_SHIFT 24
|
||||
#define TXP_PILOT_MASK GENMASK(31, 24)
|
||||
/* Bits 22-23 are set to 0x01 */
|
||||
#define TXP_VERSION_SHIFT 22
|
||||
#define TXP_VERSION_MASK GENMASK(23, 22)
|
||||
|
||||
/* Powers down the internal memory. */
|
||||
# define TXP_POWERDOWN BIT(21)
|
||||
|
||||
/* Enables storing the alpha component in 8888/4444, instead of
|
||||
* filling with ~ALPHA_INVERT.
|
||||
*/
|
||||
# define TXP_ALPHA_ENABLE BIT(20)
|
||||
|
||||
/* 4 bits, each enables stores for a channel in each set of 4 bytes.
|
||||
* Set to 0xf for normal operation.
|
||||
*/
|
||||
# define TXP_BYTE_ENABLE_SHIFT 16
|
||||
# define TXP_BYTE_ENABLE_MASK GENMASK(19, 16)
|
||||
|
||||
/* Debug: Generate VSTART again at EOF. */
|
||||
# define TXP_VSTART_AT_EOF BIT(15)
|
||||
|
||||
/* Debug: Terminate the current frame immediately. Stops AXI
|
||||
* writes.
|
||||
*/
|
||||
# define TXP_ABORT BIT(14)
|
||||
|
||||
# define TXP_DITHER BIT(13)
|
||||
|
||||
/* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for
|
||||
* !TXP_ALPHA_ENABLE.
|
||||
*/
|
||||
# define TXP_ALPHA_INVERT BIT(12)
|
||||
|
||||
/* Note: I've listed the channels here in high bit (in byte 3/2/1) to
|
||||
* low bit (in byte 0) order.
|
||||
*/
|
||||
# define TXP_FORMAT_SHIFT 8
|
||||
# define TXP_FORMAT_MASK GENMASK(11, 8)
|
||||
# define TXP_FORMAT_ABGR4444 0
|
||||
# define TXP_FORMAT_ARGB4444 1
|
||||
# define TXP_FORMAT_BGRA4444 2
|
||||
# define TXP_FORMAT_RGBA4444 3
|
||||
# define TXP_FORMAT_BGR565 6
|
||||
# define TXP_FORMAT_RGB565 7
|
||||
/* 888s are non-rotated, raster-only */
|
||||
# define TXP_FORMAT_BGR888 8
|
||||
# define TXP_FORMAT_RGB888 9
|
||||
# define TXP_FORMAT_ABGR8888 12
|
||||
# define TXP_FORMAT_ARGB8888 13
|
||||
# define TXP_FORMAT_BGRA8888 14
|
||||
# define TXP_FORMAT_RGBA8888 15
|
||||
|
||||
/* If TFORMAT is set, generates LT instead of T format. */
|
||||
# define TXP_LINEAR_UTILE BIT(7)
|
||||
|
||||
/* Rotate output by 90 degrees. */
|
||||
# define TXP_TRANSPOSE BIT(6)
|
||||
|
||||
/* Generate a tiled format for V3D. */
|
||||
# define TXP_TFORMAT BIT(5)
|
||||
|
||||
/* Generates some undefined test mode output. */
|
||||
# define TXP_TEST_MODE BIT(4)
|
||||
|
||||
/* Request odd field from HVS. */
|
||||
# define TXP_FIELD BIT(3)
|
||||
|
||||
/* Raise interrupt when idle. */
|
||||
# define TXP_EI BIT(2)
|
||||
|
||||
/* Set when generating a frame, clears when idle. */
|
||||
# define TXP_BUSY BIT(1)
|
||||
|
||||
/* Starts a frame. Self-clearing. */
|
||||
# define TXP_GO BIT(0)
|
||||
|
||||
/* Number of lines received and committed to memory. */
|
||||
#define TXP_PROGRESS 0x10
|
||||
|
||||
#define TXP_READ(offset) readl(txp->regs + (offset))
|
||||
#define TXP_WRITE(offset, val) writel(val, txp->regs + (offset))
|
||||
|
||||
struct vc4_txp {
|
||||
struct platform_device *pdev;
|
||||
|
||||
struct drm_writeback_connector connector;
|
||||
|
||||
void __iomem *regs;
|
||||
};
|
||||
|
||||
static inline struct vc4_txp *encoder_to_vc4_txp(struct drm_encoder *encoder)
|
||||
{
|
||||
return container_of(encoder, struct vc4_txp, connector.encoder);
|
||||
}
|
||||
|
||||
static inline struct vc4_txp *connector_to_vc4_txp(struct drm_connector *conn)
|
||||
{
|
||||
return container_of(conn, struct vc4_txp, connector.base);
|
||||
}
|
||||
|
||||
#define TXP_REG(reg) { reg, #reg }
|
||||
static const struct {
|
||||
u32 reg;
|
||||
const char *name;
|
||||
} txp_regs[] = {
|
||||
TXP_REG(TXP_DST_PTR),
|
||||
TXP_REG(TXP_DST_PITCH),
|
||||
TXP_REG(TXP_DIM),
|
||||
TXP_REG(TXP_DST_CTRL),
|
||||
TXP_REG(TXP_PROGRESS),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
int vc4_txp_debugfs_regs(struct seq_file *m, void *unused)
|
||||
{
|
||||
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
||||
struct drm_device *dev = node->minor->dev;
|
||||
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
||||
struct vc4_txp *txp = vc4->txp;
|
||||
int i;
|
||||
|
||||
if (!txp)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(txp_regs); i++) {
|
||||
seq_printf(m, "%s (0x%04x): 0x%08x\n",
|
||||
txp_regs[i].name, txp_regs[i].reg,
|
||||
TXP_READ(txp_regs[i].reg));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int vc4_txp_connector_get_modes(struct drm_connector *connector)
|
||||
{
|
||||
struct drm_device *dev = connector->dev;
|
||||
|
||||
return drm_add_modes_noedid(connector, dev->mode_config.max_width,
|
||||
dev->mode_config.max_height);
|
||||
}
|
||||
|
||||
static enum drm_mode_status
|
||||
vc4_txp_connector_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct drm_mode_config *mode_config = &dev->mode_config;
|
||||
int w = mode->hdisplay, h = mode->vdisplay;
|
||||
|
||||
if (w < mode_config->min_width || w > mode_config->max_width)
|
||||
return MODE_BAD_HVALUE;
|
||||
|
||||
if (h < mode_config->min_height || h > mode_config->max_height)
|
||||
return MODE_BAD_VVALUE;
|
||||
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
static const u32 drm_fmts[] = {
|
||||
DRM_FORMAT_RGB888,
|
||||
DRM_FORMAT_BGR888,
|
||||
DRM_FORMAT_XRGB8888,
|
||||
DRM_FORMAT_XBGR8888,
|
||||
DRM_FORMAT_ARGB8888,
|
||||
DRM_FORMAT_ABGR8888,
|
||||
DRM_FORMAT_RGBX8888,
|
||||
DRM_FORMAT_BGRX8888,
|
||||
DRM_FORMAT_RGBA8888,
|
||||
DRM_FORMAT_BGRA8888,
|
||||
};
|
||||
|
||||
static const u32 txp_fmts[] = {
|
||||
TXP_FORMAT_RGB888,
|
||||
TXP_FORMAT_BGR888,
|
||||
TXP_FORMAT_ARGB8888,
|
||||
TXP_FORMAT_ABGR8888,
|
||||
TXP_FORMAT_ARGB8888,
|
||||
TXP_FORMAT_ABGR8888,
|
||||
TXP_FORMAT_RGBA8888,
|
||||
TXP_FORMAT_BGRA8888,
|
||||
TXP_FORMAT_RGBA8888,
|
||||
TXP_FORMAT_BGRA8888,
|
||||
};
|
||||
|
||||
static int vc4_txp_connector_atomic_check(struct drm_connector *conn,
|
||||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
struct drm_crtc_state *crtc_state;
|
||||
struct drm_gem_cma_object *gem;
|
||||
struct drm_framebuffer *fb;
|
||||
int i;
|
||||
|
||||
if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
|
||||
return 0;
|
||||
|
||||
crtc_state = drm_atomic_get_new_crtc_state(conn_state->state,
|
||||
conn_state->crtc);
|
||||
|
||||
fb = conn_state->writeback_job->fb;
|
||||
if (fb->width != crtc_state->mode.hdisplay ||
|
||||
fb->height != crtc_state->mode.vdisplay) {
|
||||
DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",
|
||||
fb->width, fb->height);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
|
||||
if (fb->format->format == drm_fmts[i])
|
||||
break;
|
||||
}
|
||||
|
||||
if (i == ARRAY_SIZE(drm_fmts))
|
||||
return -EINVAL;
|
||||
|
||||
gem = drm_fb_cma_get_gem_obj(fb, 0);
|
||||
|
||||
/* Pitch must be aligned on 16 bytes. */
|
||||
if (fb->pitches[0] & GENMASK(3, 0))
|
||||
return -EINVAL;
|
||||
|
||||
vc4_crtc_txp_armed(crtc_state);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
|
||||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
struct vc4_txp *txp = connector_to_vc4_txp(conn);
|
||||
struct drm_gem_cma_object *gem;
|
||||
struct drm_display_mode *mode;
|
||||
struct drm_framebuffer *fb;
|
||||
u32 ctrl;
|
||||
int i;
|
||||
|
||||
if (WARN_ON(!conn_state->writeback_job ||
|
||||
!conn_state->writeback_job->fb))
|
||||
return;
|
||||
|
||||
mode = &conn_state->crtc->state->adjusted_mode;
|
||||
fb = conn_state->writeback_job->fb;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
|
||||
if (fb->format->format == drm_fmts[i])
|
||||
break;
|
||||
}
|
||||
|
||||
if (WARN_ON(i == ARRAY_SIZE(drm_fmts)))
|
||||
return;
|
||||
|
||||
ctrl = TXP_GO | TXP_VSTART_AT_EOF | TXP_EI |
|
||||
VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) |
|
||||
VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT);
|
||||
|
||||
if (fb->format->has_alpha)
|
||||
ctrl |= TXP_ALPHA_ENABLE;
|
||||
|
||||
gem = drm_fb_cma_get_gem_obj(fb, 0);
|
||||
TXP_WRITE(TXP_DST_PTR, gem->paddr + fb->offsets[0]);
|
||||
TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]);
|
||||
TXP_WRITE(TXP_DIM,
|
||||
VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) |
|
||||
VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT));
|
||||
|
||||
TXP_WRITE(TXP_DST_CTRL, ctrl);
|
||||
|
||||
drm_writeback_queue_job(&txp->connector, conn_state->writeback_job);
|
||||
}
|
||||
|
||||
static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = {
|
||||
.get_modes = vc4_txp_connector_get_modes,
|
||||
.mode_valid = vc4_txp_connector_mode_valid,
|
||||
.atomic_check = vc4_txp_connector_atomic_check,
|
||||
.atomic_commit = vc4_txp_connector_atomic_commit,
|
||||
};
|
||||
|
||||
static enum drm_connector_status
|
||||
vc4_txp_connector_detect(struct drm_connector *connector, bool force)
|
||||
{
|
||||
return connector_status_connected;
|
||||
}
|
||||
|
||||
static void vc4_txp_connector_destroy(struct drm_connector *connector)
|
||||
{
|
||||
drm_connector_unregister(connector);
|
||||
drm_connector_cleanup(connector);
|
||||
}
|
||||
|
||||
static const struct drm_connector_funcs vc4_txp_connector_funcs = {
|
||||
.detect = vc4_txp_connector_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
.destroy = vc4_txp_connector_destroy,
|
||||
.reset = drm_atomic_helper_connector_reset,
|
||||
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
|
||||
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
|
||||
};
|
||||
|
||||
static void vc4_txp_encoder_disable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct vc4_txp *txp = encoder_to_vc4_txp(encoder);
|
||||
|
||||
if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) {
|
||||
unsigned long timeout = jiffies + msecs_to_jiffies(1000);
|
||||
|
||||
TXP_WRITE(TXP_DST_CTRL, TXP_ABORT);
|
||||
|
||||
while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY &&
|
||||
time_before(jiffies, timeout))
|
||||
;
|
||||
|
||||
WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY);
|
||||
}
|
||||
|
||||
TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN);
|
||||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = {
|
||||
.disable = vc4_txp_encoder_disable,
|
||||
};
|
||||
|
||||
static irqreturn_t vc4_txp_interrupt(int irq, void *data)
|
||||
{
|
||||
struct vc4_txp *txp = data;
|
||||
|
||||
TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI);
|
||||
vc4_crtc_handle_vblank(to_vc4_crtc(txp->connector.base.state->crtc));
|
||||
drm_writeback_signal_completion(&txp->connector, 0);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int vc4_txp_bind(struct device *dev, struct device *master, void *data)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct drm_device *drm = dev_get_drvdata(master);
|
||||
struct vc4_dev *vc4 = to_vc4_dev(drm);
|
||||
struct vc4_txp *txp;
|
||||
int ret, irq;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
txp = devm_kzalloc(dev, sizeof(*txp), GFP_KERNEL);
|
||||
if (!txp)
|
||||
return -ENOMEM;
|
||||
|
||||
txp->pdev = pdev;
|
||||
|
||||
txp->regs = vc4_ioremap_regs(pdev, 0);
|
||||
if (IS_ERR(txp->regs))
|
||||
return PTR_ERR(txp->regs);
|
||||
|
||||
drm_connector_helper_add(&txp->connector.base,
|
||||
&vc4_txp_connector_helper_funcs);
|
||||
ret = drm_writeback_connector_init(drm, &txp->connector,
|
||||
&vc4_txp_connector_funcs,
|
||||
&vc4_txp_encoder_helper_funcs,
|
||||
drm_fmts, ARRAY_SIZE(drm_fmts));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0,
|
||||
dev_name(dev), txp);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dev_set_drvdata(dev, txp);
|
||||
vc4->txp = txp;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void vc4_txp_unbind(struct device *dev, struct device *master,
|
||||
void *data)
|
||||
{
|
||||
struct drm_device *drm = dev_get_drvdata(master);
|
||||
struct vc4_dev *vc4 = to_vc4_dev(drm);
|
||||
struct vc4_txp *txp = dev_get_drvdata(dev);
|
||||
|
||||
vc4_txp_connector_destroy(&txp->connector.base);
|
||||
|
||||
vc4->txp = NULL;
|
||||
}
|
||||
|
||||
static const struct component_ops vc4_txp_ops = {
|
||||
.bind = vc4_txp_bind,
|
||||
.unbind = vc4_txp_unbind,
|
||||
};
|
||||
|
||||
static int vc4_txp_probe(struct platform_device *pdev)
|
||||
{
|
||||
return component_add(&pdev->dev, &vc4_txp_ops);
|
||||
}
|
||||
|
||||
static int vc4_txp_remove(struct platform_device *pdev)
|
||||
{
|
||||
component_del(&pdev->dev, &vc4_txp_ops);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id vc4_txp_dt_match[] = {
|
||||
{ .compatible = "brcm,bcm2835-txp" },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
struct platform_driver vc4_txp_driver = {
|
||||
.probe = vc4_txp_probe,
|
||||
.remove = vc4_txp_remove,
|
||||
.driver = {
|
||||
.name = "vc4_txp",
|
||||
.of_match_table = vc4_txp_dt_match,
|
||||
},
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user