forked from luck/tmp_suning_uos_patched
ARM: at91: Add machine header file for AT91SAM9N12 SoC
Signed-off-by: Hong Xu <hong.xu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Hong Xu
Jean-Christophe PLAGNIOL-VILLARD
parent
26690863e2
commit
0205968427
60
arch/arm/mach-at91/include/mach/at91sam9n12.h
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60
arch/arm/mach-at91/include/mach/at91sam9n12.h
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/*
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* SoC specific header file for the AT91SAM9N12
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*
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* Copyright (C) 2012 Atmel Corporation
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*
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* Common definitions, based on AT91SAM9N12 SoC datasheet
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*
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* Licensed under GPLv2 or later
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*/
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#ifndef _AT91SAM9N12_H_
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#define _AT91SAM9N12_H_
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
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#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
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#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */
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#define AT91SAM9N12_ID_USART0 5 /* USART 0 */
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#define AT91SAM9N12_ID_USART1 6 /* USART 1 */
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#define AT91SAM9N12_ID_USART2 7 /* USART 2 */
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#define AT91SAM9N12_ID_USART3 8 /* USART 3 */
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#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */
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#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */
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#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */
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#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */
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#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */
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#define AT91SAM9N12_ID_UART0 15 /* UART 0 */
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#define AT91SAM9N12_ID_UART1 16 /* UART 1 */
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#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
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#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */
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#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */
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#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */
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#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */
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#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */
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#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */
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#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */
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#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */
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#define AT91SAM9N12_ID_TRNG 30 /* TRNG */
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#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */
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/*
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* User Peripheral physical base addresses.
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*/
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#define AT91SAM9N12_BASE_USART0 0xf801c000
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#define AT91SAM9N12_BASE_USART1 0xf8020000
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#define AT91SAM9N12_BASE_USART2 0xf8024000
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#define AT91SAM9N12_BASE_USART3 0xf8028000
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/*
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* Internal Memory.
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*/
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#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
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#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
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#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */
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#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
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#endif
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53
arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
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arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
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/*
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* Matrix-centric header file for the AT91SAM9N12
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*
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* Copyright (C) 2012 Atmel Corporation.
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*
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* Only EBI related registers.
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* Write Protect register definitions may be useful.
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*
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* Licensed under GPLv2 or later.
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*/
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#ifndef _AT91SAM9N12_MATRIX_H_
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#define _AT91SAM9N12_MATRIX_H_
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#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */
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#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
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#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
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#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
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#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
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#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
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#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
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#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
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#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
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#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
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#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
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#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
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#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
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#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
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#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
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#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
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#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
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#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
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#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
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#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
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#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
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#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
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#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
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#define AT91_MATRIX_MP_OFF (0 << 25)
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#define AT91_MATRIX_MP_ON (1 << 25)
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#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
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#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
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#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
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#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
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#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
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#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
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#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
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#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
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#define AT91_MATRIX_WPSR_WPV (1 << 0)
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#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
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#endif
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@ -25,6 +25,7 @@
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#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
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#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
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#define ARCH_ID_AT91SAM9X5 0x819a05a0
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#define ARCH_ID_AT91SAM9N12 0x819a07a0
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#define ARCH_ID_AT91SAM9XE128 0x329973a0
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#define ARCH_ID_AT91SAM9XE256 0x329a93a0
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@ -71,6 +72,9 @@ enum at91_soc_type {
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/* SAM9X5 */
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AT91_SOC_SAM9X5,
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/* SAM9N12 */
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AT91_SOC_SAM9N12,
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/* Unknown type */
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AT91_SOC_NONE
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};
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@ -177,6 +181,12 @@ static inline int at91_soc_is_detected(void)
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#define cpu_is_at91sam9x25() (0)
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#endif
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#ifdef CONFIG_SOC_AT91SAM9N12
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#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12)
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#else
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#define cpu_is_at91sam9n12() (0)
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#endif
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/*
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* Since this is ARM, we will never run on any AVR32 CPU. But these
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* definitions may reduce clutter in common drivers.
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@ -32,6 +32,7 @@
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#include <mach/at91sam9rl.h>
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#include <mach/at91sam9g45.h>
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#include <mach/at91sam9x5.h>
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#include <mach/at91sam9n12.h>
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/*
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* On all at91 except rm9200 and x40 have the System Controller starts
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@ -20,6 +20,7 @@ extern struct at91_init_soc at91sam9263_soc;
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extern struct at91_init_soc at91sam9g45_soc;
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extern struct at91_init_soc at91sam9rl_soc;
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extern struct at91_init_soc at91sam9x5_soc;
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extern struct at91_init_soc at91sam9n12_soc;
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static inline int at91_soc_is_enabled(void)
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{
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@ -53,3 +54,7 @@ static inline int at91_soc_is_enabled(void)
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#if !defined(CONFIG_SOC_AT91SAM9X5)
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#define at91sam9x5_soc at91_boot_soc
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#endif
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#if !defined(CONFIG_SOC_AT91SAM9N12)
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#define at91sam9n12_soc at91_boot_soc
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#endif
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