forked from luck/tmp_suning_uos_patched
Reset controller updates for v5.8
This tag adds support for i.MX8MP and i.MX8MN SoCs to the i.MX7 reset controller driver, extends the Hi6220 reset driver to support the AO reset controller used to bring the Mali450 GPU out of reset, and adds a define for the internal DAC reset line on Amlogic GXL SoCs. -----BEGIN PGP SIGNATURE----- iI4EABYIADYWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXr6nvBgccGhpbGlwcC56 YWJlbEBnbWFpbC5jb20ACgkQ1YWnJRg3YsB63QEA8Rig0c9jN9LBDxVmqxB8dU/k 4fc3vMtuxbbrzmoD9rIA/ApMrQe77k/JW+hCSBrgCQWlvHInRncKwrEIhWk7ADkN =BaS5 -----END PGP SIGNATURE----- Merge tag 'reset-for-v5.8' of git://git.pengutronix.de/pza/linux into arm/drivers Reset controller updates for v5.8 This tag adds support for i.MX8MP and i.MX8MN SoCs to the i.MX7 reset controller driver, extends the Hi6220 reset driver to support the AO reset controller used to bring the Mali450 GPU out of reset, and adds a define for the internal DAC reset line on Amlogic GXL SoCs. * tag 'reset-for-v5.8' of git://git.pengutronix.de/pza/linux: reset: hi6220: Add support for AO reset controller reset: imx7: Add support for i.MX8MP SoC dt-bindings: reset: imx7: Document usage on i.MX8MP SoC dt-bindings: reset: imx7: Add support for i.MX8MN dt-bindings: reset: meson: add gxl internal dac reset Link: https://lore.kernel.org/r/20200515143844.GA17201@pengutronix.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
0417a5c6a4
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@ -9,6 +9,8 @@ Required properties:
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- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"
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- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"
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- For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"
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- For i.MX8MN SoCs should be "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"
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- For i.MX8MP SoCs should be "fsl,imx8mp-src", "syscon"
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- reg: should be register base and length as documented in the
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datasheet
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- interrupts: Should contain SRC interrupt
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@ -49,4 +51,6 @@ Example:
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For list of all valid reset indices see
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<dt-bindings/reset/imx7-reset.h> for i.MX7,
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM and
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN and
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<dt-bindings/reset/imx8mp-reset.h> for i.MX8MP
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@ -33,6 +33,7 @@
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enum hi6220_reset_ctrl_type {
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PERIPHERAL,
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MEDIA,
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AO,
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};
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struct hi6220_reset_data {
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@ -92,6 +93,65 @@ static const struct reset_control_ops hi6220_media_reset_ops = {
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.deassert = hi6220_media_deassert,
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};
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#define AO_SCTRL_SC_PW_CLKEN0 0x800
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#define AO_SCTRL_SC_PW_CLKDIS0 0x804
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#define AO_SCTRL_SC_PW_RSTEN0 0x810
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#define AO_SCTRL_SC_PW_RSTDIS0 0x814
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#define AO_SCTRL_SC_PW_ISOEN0 0x820
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#define AO_SCTRL_SC_PW_ISODIS0 0x824
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#define AO_MAX_INDEX 12
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static int hi6220_ao_assert(struct reset_controller_dev *rc_dev,
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unsigned long idx)
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{
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struct hi6220_reset_data *data = to_reset_data(rc_dev);
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struct regmap *regmap = data->regmap;
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int ret;
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ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTEN0, BIT(idx));
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if (ret)
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return ret;
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ret = regmap_write(regmap, AO_SCTRL_SC_PW_ISOEN0, BIT(idx));
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if (ret)
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return ret;
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ret = regmap_write(regmap, AO_SCTRL_SC_PW_CLKDIS0, BIT(idx));
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return ret;
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}
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static int hi6220_ao_deassert(struct reset_controller_dev *rc_dev,
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unsigned long idx)
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{
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struct hi6220_reset_data *data = to_reset_data(rc_dev);
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struct regmap *regmap = data->regmap;
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int ret;
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/*
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* It was suggested to disable isolation before enabling
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* the clocks and deasserting reset, to avoid glitches.
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* But this order is preserved to keep it matching the
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* vendor code.
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*/
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ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTDIS0, BIT(idx));
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if (ret)
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return ret;
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ret = regmap_write(regmap, AO_SCTRL_SC_PW_ISODIS0, BIT(idx));
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if (ret)
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return ret;
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ret = regmap_write(regmap, AO_SCTRL_SC_PW_CLKEN0, BIT(idx));
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return ret;
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}
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static const struct reset_control_ops hi6220_ao_reset_ops = {
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.assert = hi6220_ao_assert,
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.deassert = hi6220_ao_deassert,
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};
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static int hi6220_reset_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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@ -117,9 +177,12 @@ static int hi6220_reset_probe(struct platform_device *pdev)
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if (type == MEDIA) {
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data->rc_dev.ops = &hi6220_media_reset_ops;
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data->rc_dev.nr_resets = MEDIA_MAX_INDEX;
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} else {
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} else if (type == PERIPHERAL) {
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data->rc_dev.ops = &hi6220_peripheral_reset_ops;
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data->rc_dev.nr_resets = PERIPH_MAX_INDEX;
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} else {
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data->rc_dev.ops = &hi6220_ao_reset_ops;
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data->rc_dev.nr_resets = AO_MAX_INDEX;
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}
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return reset_controller_register(&data->rc_dev);
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@ -134,6 +197,10 @@ static const struct of_device_id hi6220_reset_match[] = {
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.compatible = "hisilicon,hi6220-mediactrl",
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.data = (void *)MEDIA,
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},
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{
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.compatible = "hisilicon,hi6220-aoctrl",
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.data = (void *)AO,
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, hi6220_reset_match);
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@ -15,6 +15,7 @@
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#include <linux/regmap.h>
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#include <dt-bindings/reset/imx7-reset.h>
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#include <dt-bindings/reset/imx8mq-reset.h>
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#include <dt-bindings/reset/imx8mp-reset.h>
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struct imx7_src_signal {
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unsigned int offset, bit;
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@ -145,6 +146,18 @@ enum imx8mq_src_registers {
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SRC_DDRC2_RCR = 0x1004,
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};
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enum imx8mp_src_registers {
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SRC_SUPERMIX_RCR = 0x0018,
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SRC_AUDIOMIX_RCR = 0x001c,
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SRC_MLMIX_RCR = 0x0028,
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SRC_GPU2D_RCR = 0x0038,
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SRC_GPU3D_RCR = 0x003c,
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SRC_VPU_G1_RCR = 0x0048,
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SRC_VPU_G2_RCR = 0x004c,
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SRC_VPUVC8KE_RCR = 0x0050,
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SRC_NOC_RCR = 0x0054,
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};
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static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
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[IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
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[IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
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@ -253,6 +266,93 @@ static const struct imx7_src_variant variant_imx8mq = {
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},
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};
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static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
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[IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
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[IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
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[IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
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[IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
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[IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
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[IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
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[IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
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[IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
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[IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
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[IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
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[IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
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[IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
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[IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
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[IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
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[IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
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[IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
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[IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
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[IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
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[IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
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[IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
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[IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
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[IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) },
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[IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) },
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[IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) },
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[IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) },
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[IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
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[IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
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[IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
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[IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
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[IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) },
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[IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) },
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[IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) },
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[IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
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[IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
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[IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) },
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[IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) },
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[IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) },
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[IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) },
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};
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static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct imx7_src *imx7src = to_imx7_src(rcdev);
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const unsigned int bit = imx7src->signals[id].bit;
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unsigned int value = assert ? bit : 0;
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switch (id) {
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case IMX8MP_RESET_PCIEPHY:
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/*
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* wait for more than 10us to release phy g_rst and
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* btnrst
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*/
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if (!assert)
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udelay(10);
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break;
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case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
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value = assert ? 0 : bit;
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break;
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}
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return imx7_reset_update(imx7src, id, value);
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}
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static int imx8mp_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return imx8mp_reset_set(rcdev, id, true);
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}
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static int imx8mp_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return imx8mp_reset_set(rcdev, id, false);
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}
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static const struct imx7_src_variant variant_imx8mp = {
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.signals = imx8mp_src_signals,
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.signals_num = ARRAY_SIZE(imx8mp_src_signals),
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.ops = {
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.assert = imx8mp_reset_assert,
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.deassert = imx8mp_reset_deassert,
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},
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};
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static int imx7_reset_probe(struct platform_device *pdev)
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{
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struct imx7_src *imx7src;
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@ -283,6 +383,7 @@ static int imx7_reset_probe(struct platform_device *pdev)
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static const struct of_device_id imx7_reset_dt_ids[] = {
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{ .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
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{ .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
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{ .compatible = "fsl,imx8mp-src", .data = &variant_imx8mp },
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{ /* sentinel */ },
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};
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@ -69,7 +69,7 @@
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#define RESET_SYS_CPU_L2 58
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#define RESET_SYS_CPU_P 59
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#define RESET_SYS_CPU_MBIST 60
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/* 61 */
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#define RESET_ACODEC 61
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/* 62 */
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/* 63 */
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/* RESET2 */
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50
include/dt-bindings/reset/imx8mp-reset.h
Normal file
50
include/dt-bindings/reset/imx8mp-reset.h
Normal file
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@ -0,0 +1,50 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2020 NXP
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*/
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#ifndef DT_BINDING_RESET_IMX8MP_H
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#define DT_BINDING_RESET_IMX8MP_H
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#define IMX8MP_RESET_A53_CORE_POR_RESET0 0
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#define IMX8MP_RESET_A53_CORE_POR_RESET1 1
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#define IMX8MP_RESET_A53_CORE_POR_RESET2 2
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#define IMX8MP_RESET_A53_CORE_POR_RESET3 3
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#define IMX8MP_RESET_A53_CORE_RESET0 4
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#define IMX8MP_RESET_A53_CORE_RESET1 5
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#define IMX8MP_RESET_A53_CORE_RESET2 6
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#define IMX8MP_RESET_A53_CORE_RESET3 7
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#define IMX8MP_RESET_A53_DBG_RESET0 8
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#define IMX8MP_RESET_A53_DBG_RESET1 9
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#define IMX8MP_RESET_A53_DBG_RESET2 10
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#define IMX8MP_RESET_A53_DBG_RESET3 11
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#define IMX8MP_RESET_A53_ETM_RESET0 12
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#define IMX8MP_RESET_A53_ETM_RESET1 13
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#define IMX8MP_RESET_A53_ETM_RESET2 14
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#define IMX8MP_RESET_A53_ETM_RESET3 15
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#define IMX8MP_RESET_A53_SOC_DBG_RESET 16
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#define IMX8MP_RESET_A53_L2RESET 17
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#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18
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#define IMX8MP_RESET_OTG1_PHY_RESET 19
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#define IMX8MP_RESET_OTG2_PHY_RESET 20
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#define IMX8MP_RESET_SUPERMIX_RESET 21
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#define IMX8MP_RESET_AUDIOMIX_RESET 22
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#define IMX8MP_RESET_MLMIX_RESET 23
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#define IMX8MP_RESET_PCIEPHY 24
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#define IMX8MP_RESET_PCIEPHY_PERST 25
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#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26
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#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27
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#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28
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#define IMX8MP_RESET_MEDIA_RESET 29
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#define IMX8MP_RESET_GPU2D_RESET 30
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#define IMX8MP_RESET_GPU3D_RESET 31
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#define IMX8MP_RESET_GPU_RESET 32
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#define IMX8MP_RESET_VPU_RESET 33
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#define IMX8MP_RESET_VPU_G1_RESET 34
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#define IMX8MP_RESET_VPU_G2_RESET 35
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#define IMX8MP_RESET_VPUVC8KE_RESET 36
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#define IMX8MP_RESET_NOC_RESET 37
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#define IMX8MP_RESET_NUM 38
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#endif
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@ -28,36 +28,36 @@
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#define IMX8MQ_RESET_A53_L2RESET 17
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#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
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#define IMX8MQ_RESET_OTG1_PHY_RESET 19
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#define IMX8MQ_RESET_OTG2_PHY_RESET 20
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#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
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#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
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#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23
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#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24
|
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#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25
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#define IMX8MQ_RESET_PCIEPHY 26
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#define IMX8MQ_RESET_PCIEPHY_PERST 27
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#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
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#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
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#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */
|
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#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */
|
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#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DISP_RESET 31
|
||||
#define IMX8MQ_RESET_GPU_RESET 32
|
||||
#define IMX8MQ_RESET_VPU_RESET 33
|
||||
#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC1_PRST 44
|
||||
#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
|
||||
#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
|
||||
#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
|
||||
#define IMX8MQ_RESET_NUM 50
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user