AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

ixgbe: Update get_physical_layer() calls, plus a version bump

Browse Source 
Not all physical connection types are being correctly identified.  This
fixes that issue, and cleans up the logic to make it more maintainable.

Also clean up the code for device capabilities from the EEPROM to support
multiple SKUs of the same hardware.

Bump the version to reflect all the updates since the 82599 merge.

Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Peter P Waskiewicz Jr 2009-04-09 22:28:50 +00:00 committed by David S. Miller
parent 1eb99d5ac4
commit 04193058c1
5 changed files with 172 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

85
drivers/net/ixgbe/ixgbe_82598.c
View File

@ -1089,35 +1089,56 @@ static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
{ {
u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
u16 ext_ability = 0;
switch (hw->device_id) { hw->phy.ops.identify(hw);
case IXGBE_DEV_ID_82598:
/* Default device ID is mezzanine card KX/KX4 */ /* Copper PHY must be checked before AUTOC LMS to determine correct
physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
IXGBE_PHYSICAL_LAYER_1000BASE_KX); if (hw->phy.type == ixgbe_phy_tn ||
hw->phy.type == ixgbe_phy_cu_unknown) {
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
goto out;
}
switch (autoc & IXGBE_AUTOC_LMS_MASK) {
case IXGBE_AUTOC_LMS_1G_AN:
case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
else
physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
break; break;
case IXGBE_DEV_ID_82598_BX: case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
case IXGBE_DEV_ID_82598EB_CX4: physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
else /* XAUI */
physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
break; break;
case IXGBE_DEV_ID_82598_DA_DUAL_PORT: case IXGBE_AUTOC_LMS_KX4_AN:
physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
if (autoc & IXGBE_AUTOC_KX_SUPP)
physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
if (autoc & IXGBE_AUTOC_KX4_SUPP)
physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
break; break;
case IXGBE_DEV_ID_82598AF_DUAL_PORT: default:
case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
break; break;
case IXGBE_DEV_ID_82598EB_XF_LR: }
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
break; if (hw->phy.type == ixgbe_phy_nl) {
case IXGBE_DEV_ID_82598AT:
physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
IXGBE_PHYSICAL_LAYER_1000BASE_T);
break;
case IXGBE_DEV_ID_82598EB_SFP_LOM:
hw->phy.ops.identify_sfp(hw); hw->phy.ops.identify_sfp(hw);
switch (hw->phy.sfp_type) { switch (hw->phy.sfp_type) {
@ -1134,13 +1155,25 @@ static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
break; break;
} }
break; }
switch (hw->device_id) {
case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
break;
case IXGBE_DEV_ID_82598AF_DUAL_PORT:
case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
break;
case IXGBE_DEV_ID_82598EB_XF_LR:
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
break;
default: default:
physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
break; break;
} }
out:
return physical_layer; return physical_layer;
} }

140
drivers/net/ixgbe/ixgbe_82599.c
View File

@ -1177,53 +1177,98 @@ s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
{ {
u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
u16 ext_ability = 0;
u8 comp_codes_10g = 0; u8 comp_codes_10g = 0;
switch (hw->device_id) { hw->phy.ops.identify(hw);
case IXGBE_DEV_ID_82599:
case IXGBE_DEV_ID_82599_KX4:
/* Default device ID is mezzanine card KX/KX4 */
physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
IXGBE_PHYSICAL_LAYER_1000BASE_KX);
break;
case IXGBE_DEV_ID_82599_SFP:
hw->phy.ops.identify_sfp(hw);
switch (hw->phy.sfp_type) { if (hw->phy.type == ixgbe_phy_tn ||
case ixgbe_sfp_type_da_cu: hw->phy.type == ixgbe_phy_cu_unknown) {
case ixgbe_sfp_type_da_cu_core0: hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
case ixgbe_sfp_type_da_cu_core1: IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
break; physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
case ixgbe_sfp_type_sr: if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
break; if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
case ixgbe_sfp_type_lr: physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; goto out;
break; }
case ixgbe_sfp_type_srlr_core0:
case ixgbe_sfp_type_srlr_core1: switch (autoc & IXGBE_AUTOC_LMS_MASK) {
hw->phy.ops.read_i2c_eeprom(hw, case IXGBE_AUTOC_LMS_1G_AN:
IXGBE_SFF_10GBE_COMP_CODES, case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
&comp_codes_10g); if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
IXGBE_PHYSICAL_LAYER_10GBASE_SR; goto out;
else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) } else
physical_layer = /* SFI mode so read SFP module */
IXGBE_PHYSICAL_LAYER_10GBASE_LR; goto sfp_check;
else break;
physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
default: if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
break; else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
} physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
goto out;
break;
case IXGBE_AUTOC_LMS_10G_SERIAL:
if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
goto out;
} else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
goto sfp_check;
break;
case IXGBE_AUTOC_LMS_KX4_KX_KR:
case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
if (autoc & IXGBE_AUTOC_KX_SUPP)
physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
if (autoc & IXGBE_AUTOC_KX4_SUPP)
physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
if (autoc & IXGBE_AUTOC_KR_SUPP)
physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
goto out;
break; break;
default: default:
physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; goto out;
break; break;
} }
sfp_check:
/* SFP check must be done last since DA modules are sometimes used to
* test KR mode - we need to id KR mode correctly before SFP module.
* Call identify_sfp because the pluggable module may have changed */
hw->phy.ops.identify_sfp(hw);
if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
goto out;
switch (hw->phy.type) {
case ixgbe_phy_tw_tyco:
case ixgbe_phy_tw_unknown:
physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
break;
case ixgbe_phy_sfp_avago:
case ixgbe_phy_sfp_ftl:
case ixgbe_phy_sfp_intel:
case ixgbe_phy_sfp_unknown:
hw->phy.ops.read_i2c_eeprom(hw,
IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
break;
default:
break;
}
out:
return physical_layer; return physical_layer;
} }
@ -1271,6 +1316,22 @@ s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
return 0; return 0;
} }
/**
* ixgbe_get_device_caps_82599 - Get additional device capabilities
* @hw: pointer to hardware structure
* @device_caps: the EEPROM word with the extra device capabilities
*
* This function will read the EEPROM location for the device capabilities,
* and return the word through device_caps.
**/
s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
{
hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
return 0;
}
static struct ixgbe_mac_operations mac_ops_82599 = { static struct ixgbe_mac_operations mac_ops_82599 = {
.init_hw = &ixgbe_init_hw_generic, .init_hw = &ixgbe_init_hw_generic,
.reset_hw = &ixgbe_reset_hw_82599, .reset_hw = &ixgbe_reset_hw_82599,
@ -1280,6 +1341,7 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
.get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599, .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
.enable_rx_dma = &ixgbe_enable_rx_dma_82599, .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
.get_mac_addr = &ixgbe_get_mac_addr_generic, .get_mac_addr = &ixgbe_get_mac_addr_generic,
.get_device_caps = &ixgbe_get_device_caps_82599,
.stop_adapter = &ixgbe_stop_adapter_generic, .stop_adapter = &ixgbe_stop_adapter_generic,
.get_bus_info = &ixgbe_get_bus_info_generic, .get_bus_info = &ixgbe_get_bus_info_generic,
.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,

2
drivers/net/ixgbe/ixgbe_main.c
View File

@ -47,7 +47,7 @@ char ixgbe_driver_name[] = "ixgbe";
static const char ixgbe_driver_string[] = static const char ixgbe_driver_string[] =
"Intel(R) 10 Gigabit PCI Express Network Driver"; "Intel(R) 10 Gigabit PCI Express Network Driver";
#define DRV_VERSION "2.0.8-k2" #define DRV_VERSION "2.0.16-k2"
const char ixgbe_driver_version[] = DRV_VERSION; const char ixgbe_driver_version[] = DRV_VERSION;
static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";

8
drivers/net/ixgbe/ixgbe_phy.c
View File

@ -632,7 +632,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
hw->phy.multispeed_fiber = true; hw->phy.multispeed_fiber = true;
/* Determine PHY vendor */ /* Determine PHY vendor */
if (hw->phy.type == ixgbe_phy_unknown) { if (hw->phy.type != ixgbe_phy_nl) {
hw->phy.id = identifier; hw->phy.id = identifier;
hw->phy.ops.read_i2c_eeprom(hw, hw->phy.ops.read_i2c_eeprom(hw,
IXGBE_SFF_VENDOR_OUI_BYTE0, IXGBE_SFF_VENDOR_OUI_BYTE0,
@ -682,9 +682,9 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
goto out; goto out;
} }
hw->eeprom.ops.read(hw, IXGBE_PHY_ENFORCE_INTEL_SFP_OFFSET, /* This is guaranteed to be 82599, no need to check for NULL */
&enforce_sfp); hw->mac.ops.get_device_caps(hw, &enforce_sfp);
if (!(enforce_sfp & IXGBE_PHY_ALLOW_ANY_SFP)) { if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
/* Make sure we're a supported PHY type */ /* Make sure we're a supported PHY type */
if (hw->phy.type == ixgbe_phy_sfp_intel) { if (hw->phy.type == ixgbe_phy_sfp_intel) {
status = 0; status = 0;

10
drivers/net/ixgbe/ixgbe_type.h
View File

@ -862,6 +862,7 @@
#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */ #define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */
#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */ #define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */
#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */ #define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */
#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
@ -898,8 +899,6 @@
#define IXGBE_CONTROL_NL 0x000F #define IXGBE_CONTROL_NL 0x000F
#define IXGBE_CONTROL_EOL_NL 0x0FFF #define IXGBE_CONTROL_EOL_NL 0x0FFF
#define IXGBE_CONTROL_SOL_NL 0x0000 #define IXGBE_CONTROL_SOL_NL 0x0000
#define IXGBE_PHY_ENFORCE_INTEL_SFP_OFFSET 0x002C
#define IXGBE_PHY_ALLOW_ANY_SFP 0x1
/* General purpose Interrupt Enable */ /* General purpose Interrupt Enable */
#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
@ -1385,6 +1384,7 @@
#define IXGBE_FW_PTR 0x0F #define IXGBE_FW_PTR 0x0F
#define IXGBE_PBANUM0_PTR 0x15 #define IXGBE_PBANUM0_PTR 0x15
#define IXGBE_PBANUM1_PTR 0x16 #define IXGBE_PBANUM1_PTR 0x16
#define IXGBE_DEVICE_CAPS 0x2C
#define IXGBE_PCIE_MSIX_82599_CAPS 0x72 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72
#define IXGBE_PCIE_MSIX_82598_CAPS 0x62 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62
@ -1428,6 +1428,8 @@
#define IXGBE_EERD_ATTEMPTS 100000 #define IXGBE_EERD_ATTEMPTS 100000
#endif #endif
#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
/* PCI Bus Info */ /* PCI Bus Info */
#define IXGBE_PCI_LINK_STATUS 0xB2 #define IXGBE_PCI_LINK_STATUS 0xB2
#define IXGBE_PCI_LINK_WIDTH 0x3F0 #define IXGBE_PCI_LINK_WIDTH 0x3F0
@ -1865,7 +1867,7 @@ typedef u32 ixgbe_physical_layer;
#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001 #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002 #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
#define IXGBE_PHYSICAL_LAYER_100BASE_T 0x0004 #define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
@ -1874,6 +1876,7 @@ typedef u32 ixgbe_physical_layer;
#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
enum ixgbe_eeprom_type { enum ixgbe_eeprom_type {
ixgbe_eeprom_uninitialized = 0, ixgbe_eeprom_uninitialized = 0,
@ -2105,6 +2108,7 @@ struct ixgbe_mac_operations {
enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
u32 (*get_supported_physical_layer)(struct ixgbe_hw *); u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
s32 (*stop_adapter)(struct ixgbe_hw *); s32 (*stop_adapter)(struct ixgbe_hw *);
s32 (*get_bus_info)(struct ixgbe_hw *); s32 (*get_bus_info)(struct ixgbe_hw *);
void (*set_lan_id)(struct ixgbe_hw *); void (*set_lan_id)(struct ixgbe_hw *);