forked from luck/tmp_suning_uos_patched
ARM: SoC fixes
Another batch of fixes for ARM SoC platforms. Most are smaller fixes, Two areas that are worth pointing out are: * OMAP had a handful of changes to voltage specs that caused a bit of churn, most of volume of change in this branch is due to this. * There are a couple of _rcuidle fixes from Paul that touch common code and came in through the OMAP tree since they were the ones who saw the problems. The rest is smaller changes across a handful of platforms. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXZjf6AAoJEIwa5zzehBx3ExoP/2eGTZyGUt9DFutZs2OhZRgh tI3zBgfPaAEmt+rnvVE3NhDbfjPsV2cANDxE/MaZsFaKkgkHNBbmZpJ3Y7OlgB+k 3kl4y87Ez1NEJrzQKzqVICzCD3IKA3cxUwUELIp3C7LhnKO1UXmRXp8UXee1Yc1E gL23Z2FncrDLOdvVfp/dTj1scB1XQrt3kePSu7sIuyDuGiPLRvO8fNjvIfOQaGDt Y27Yk1GrNpvqiOAkziOzUmSGZ6ZZ+wUdUKc/+QcxSnqxrSldtaQDsmmL4z6DQ1xj j0jagfVGXNLrCUj0zyWwwPG7pZ37BDJ1mj7AMiX9N7LDQFHR9owEVNf2zd1ar37k 64Vlz+38m8lXNHM2/gL6gqFZIm0Kjt9C/wrvyealsuflGmx4xMSTRr2yvde5URBO diFzee3y2NPhvaRaEd1/yFJ/c0D5bVS8M1lced6GXn/l8SrWjg1SrYZley2PGjQH esEr7odTR7Um1UIXalpL1yBxoOVfGJl3bPYe8/veniFSi4DV+yeCOCc6pN0Km4WQ huUlzJkIXgtgAUt5gvWAw7sC+qzYPL+qOMAJsfb/vANoGg2QMrt+u9RAWnMKidpo GcjKNvAhAmAfwUgVHeLxO714MjIHWhKEVGkGsiDwoLCisn7HTLmaYk8qmOTlExcC g/nj7vtaXFfMDcD3uco0 =C0Az -----END PGP SIGNATURE----- Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "Another batch of fixes for ARM SoC platforms. Most are smaller fixes. Two areas that are worth pointing out are: - OMAP had a handful of changes to voltage specs that caused a bit of churn, most of volume of change in this branch is due to this. - There are a couple of _rcuidle fixes from Paul that touch common code and came in through the OMAP tree since they were the ones who saw the problems. The rest is smaller changes across a handful of platforms" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (36 commits) ARM: dts: STi: stih407-family: Disable reserved-memory co-processor nodes ARM: dts: am437x-sk-evm: Reduce i2c0 bus speed for tps65218 ARM: OMAP2+: timer: add probe for clocksources ARM: OMAP1: fix ams-delta FIQ handler to work with sparse IRQ memory: omap-gpmc: Fix omap gpmc EXTRADELAY timing arm: Use _rcuidle for smp_cross_call() tracepoints MAINTAINERS: Add myself as reviewer of ARM FSL/NXP ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON ARM: imx6ul: Fix Micrel PHY mask ARM: OMAP2+: Select OMAP_INTERCONNECT for SOC_AM43XX ARM: dts: DRA74x: fix DSS PLL2 addresses ARM: OMAP2: Enable Errata 430973 for OMAP3 ARM: dts: socfpga: Add missing PHY phandle ARM: dts: exynos: Fix port nodes names for Exynos5420 Peach Pit board ARM: dts: exynos: Fix port nodes names for Exynos5250 Snow board ARM: dts: sun6i: yones-toptech-bs1078-v2: Drop constraints on dc1sw regulator ARM: dts: sun6i: primo81: Drop constraints on dc1sw regulator ARM: dts: sunxi: Add OLinuXino Lime2 eMMC to the Makefile ...
This commit is contained in:
commit
049a40c0a2
|
@ -1159,6 +1159,7 @@ F: arch/arm/mach-footbridge/
|
|||
ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
|
||||
M: Shawn Guo <shawnguo@kernel.org>
|
||||
M: Sascha Hauer <kernel@pengutronix.de>
|
||||
R: Fabio Estevam <fabio.estevam@nxp.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
|
||||
|
|
|
@ -741,6 +741,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
|
|||
sun7i-a20-olimex-som-evb.dtb \
|
||||
sun7i-a20-olinuxino-lime.dtb \
|
||||
sun7i-a20-olinuxino-lime2.dtb \
|
||||
sun7i-a20-olinuxino-lime2-emmc.dtb \
|
||||
sun7i-a20-olinuxino-micro.dtb \
|
||||
sun7i-a20-orangepi.dtb \
|
||||
sun7i-a20-orangepi-mini.dtb \
|
||||
|
|
|
@ -418,7 +418,7 @@ &i2c0 {
|
|||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
clock-frequency = <400000>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
tps@24 {
|
||||
compatible = "ti,tps65218";
|
||||
|
|
|
@ -60,10 +60,26 @@ tps659038: tps659038@58 {
|
|||
|
||||
tps659038_pmic {
|
||||
compatible = "ti,tps659038-pmic";
|
||||
|
||||
smps12-in-supply = <&vmain>;
|
||||
smps3-in-supply = <&vmain>;
|
||||
smps45-in-supply = <&vmain>;
|
||||
smps6-in-supply = <&vmain>;
|
||||
smps7-in-supply = <&vmain>;
|
||||
smps8-in-supply = <&vmain>;
|
||||
smps9-in-supply = <&vmain>;
|
||||
ldo1-in-supply = <&vmain>;
|
||||
ldo2-in-supply = <&vmain>;
|
||||
ldo3-in-supply = <&vmain>;
|
||||
ldo4-in-supply = <&vmain>;
|
||||
ldo9-in-supply = <&vmain>;
|
||||
ldoln-in-supply = <&vmain>;
|
||||
ldousb-in-supply = <&vmain>;
|
||||
ldortc-in-supply = <&vmain>;
|
||||
|
||||
regulators {
|
||||
smps12_reg: smps12 {
|
||||
/* VDD_MPU */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps12";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
|
@ -73,7 +89,6 @@ smps12_reg: smps12 {
|
|||
|
||||
smps3_reg: smps3 {
|
||||
/* VDD_DDR EMIF1 EMIF2 */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps3";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -84,7 +99,6 @@ smps3_reg: smps3 {
|
|||
smps45_reg: smps45 {
|
||||
/* VDD_DSPEVE on AM572 */
|
||||
/* VDD_IVA + VDD_DSP on AM571 */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps45";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
|
@ -94,7 +108,6 @@ smps45_reg: smps45 {
|
|||
|
||||
smps6_reg: smps6 {
|
||||
/* VDD_GPU */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps6";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
|
@ -104,7 +117,6 @@ smps6_reg: smps6 {
|
|||
|
||||
smps7_reg: smps7 {
|
||||
/* VDD_CORE */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps7";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
|
@ -115,13 +127,11 @@ smps7_reg: smps7 {
|
|||
smps8_reg: smps8 {
|
||||
/* 5728 - VDD_IVAHD */
|
||||
/* 5718 - N.C. test point */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps8";
|
||||
};
|
||||
|
||||
smps9_reg: smps9 {
|
||||
/* VDD_3_3D */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps9";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
@ -132,7 +142,6 @@ smps9_reg: smps9 {
|
|||
ldo1_reg: ldo1 {
|
||||
/* VDDSHV8 - VSDMMC */
|
||||
/* NOTE: on rev 1.3a, data supply */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
@ -142,7 +151,6 @@ ldo1_reg: ldo1 {
|
|||
|
||||
ldo2_reg: ldo2 {
|
||||
/* VDDSH18V */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
@ -152,7 +160,6 @@ ldo2_reg: ldo2 {
|
|||
|
||||
ldo3_reg: ldo3 {
|
||||
/* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
@ -162,7 +169,6 @@ ldo3_reg: ldo3 {
|
|||
|
||||
ldo4_reg: ldo4 {
|
||||
/* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
@ -174,7 +180,6 @@ ldo4_reg: ldo4 {
|
|||
|
||||
ldo9_reg: ldo9 {
|
||||
/* VDD_RTC */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldo9";
|
||||
regulator-min-microvolt = <840000>;
|
||||
regulator-max-microvolt = <1160000>;
|
||||
|
@ -184,7 +189,6 @@ ldo9_reg: ldo9 {
|
|||
|
||||
ldoln_reg: ldoln {
|
||||
/* VDDA_1V8_PLL */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldoln";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
@ -194,7 +198,6 @@ ldoln_reg: ldoln {
|
|||
|
||||
ldousb_reg: ldousb {
|
||||
/* VDDA_3V_USB: VDDA_USBHS33 */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldousb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
@ -204,7 +207,6 @@ ldousb_reg: ldousb {
|
|||
|
||||
ldortc_reg: ldortc {
|
||||
/* VDDA_RTC */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldortc";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
|
|
@ -93,6 +93,10 @@ partition@0x780000 {
|
|||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd1_pins>;
|
||||
|
@ -101,6 +105,10 @@ &mmc2 {
|
|||
cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pincntl {
|
||||
sd1_pins: pinmux_sd1_pins {
|
||||
pinctrl-single,pins = <
|
||||
|
|
|
@ -45,6 +45,14 @@ &cpsw_emac1 {
|
|||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd2_pins>;
|
||||
|
@ -53,6 +61,7 @@ &mmc3 {
|
|||
dmas = <&edma_xbar 8 0 1 /* use SDTXEVT1 instead of MCASP0TX */
|
||||
&edma_xbar 9 0 2>; /* use SDRXEVT1 instead of MCASP0RX */
|
||||
dma-names = "tx", "rx";
|
||||
non-removable;
|
||||
};
|
||||
|
||||
&pincntl {
|
||||
|
|
|
@ -1451,6 +1451,8 @@ gpmc: gpmc@50000000 {
|
|||
ti,hwmods = "gpmc";
|
||||
reg = <0x50000000 0x37c>; /* device IO registers */
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&edma_xbar 4 0>;
|
||||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <8>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
|
|
|
@ -107,8 +107,8 @@ &dss {
|
|||
reg = <0x58000000 0x80>,
|
||||
<0x58004054 0x4>,
|
||||
<0x58004300 0x20>,
|
||||
<0x58005054 0x4>,
|
||||
<0x58005300 0x20>;
|
||||
<0x58009054 0x4>,
|
||||
<0x58009300 0x20>;
|
||||
reg-names = "dss", "pll1_clkctrl", "pll1",
|
||||
"pll2_clkctrl", "pll2";
|
||||
|
||||
|
|
|
@ -242,7 +242,7 @@ &dp {
|
|||
hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
port0 {
|
||||
port {
|
||||
dp_out: endpoint {
|
||||
remote-endpoint = <&bridge_in>;
|
||||
};
|
||||
|
@ -485,13 +485,20 @@ ptn3460: lvds-bridge@20 {
|
|||
edid-emulation = <5>;
|
||||
|
||||
ports {
|
||||
port0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
bridge_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port1 {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
bridge_in: endpoint {
|
||||
remote-endpoint = <&dp_out>;
|
||||
};
|
||||
|
|
|
@ -163,7 +163,7 @@ &dp {
|
|||
hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
port0 {
|
||||
port {
|
||||
dp_out: endpoint {
|
||||
remote-endpoint = <&bridge_in>;
|
||||
};
|
||||
|
@ -631,13 +631,20 @@ ps8625: lvds-bridge@48 {
|
|||
use-external-pwm;
|
||||
|
||||
ports {
|
||||
port0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
bridge_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port1 {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
bridge_in: endpoint {
|
||||
remote-endpoint = <&dp_out>;
|
||||
};
|
||||
|
|
|
@ -85,7 +85,7 @@ mmc2_pins: pinmux_mmc2_pins {
|
|||
OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
|
||||
OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
|
||||
OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
|
||||
OMAP3_CORE1_IOPAD(0x215e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
|
||||
OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
|
||||
OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
|
||||
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
|
||||
>;
|
||||
|
|
|
@ -188,6 +188,7 @@ &mmc1 {
|
|||
vmmc-supply = <&vmmc1>;
|
||||
vmmc_aux-supply = <&vsim>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
|
|
|
@ -194,6 +194,12 @@ OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
|
|||
OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_wp_pins: pinmux_mmc1_cd_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
|
@ -250,3 +256,8 @@ dpi_out: endpoint {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>;
|
||||
wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */
|
||||
};
|
||||
|
|
|
@ -288,7 +288,7 @@ ssi_pins: pinmux_ssi {
|
|||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
|
||||
OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */
|
||||
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
|
||||
OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
|
||||
OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
|
||||
|
@ -300,7 +300,7 @@ OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
|
|||
modem_pins: pinmux_modem {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
|
||||
OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */
|
||||
OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */
|
||||
OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
|
||||
OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
|
||||
OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
|
||||
|
|
|
@ -97,7 +97,7 @@ ssi_pins: pinmux_ssi_pins {
|
|||
OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
|
||||
OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */
|
||||
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
|
||||
OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
|
||||
OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
|
||||
OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
|
||||
|
@ -110,7 +110,7 @@ ssi_pins_idle: pinmux_ssi_pins_idle {
|
|||
OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */
|
||||
OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */
|
||||
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
|
||||
OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */
|
||||
OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */
|
||||
OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */
|
||||
|
@ -120,7 +120,7 @@ OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7) /* ssi1_wake */
|
|||
|
||||
modem_pins1: pinmux_modem_core1_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio_34 (ape_rst_rq) */
|
||||
OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */
|
||||
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */
|
||||
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */
|
||||
>;
|
||||
|
|
|
@ -98,7 +98,7 @@ uart2_pins: pinmux_uart2_pins {
|
|||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
|
||||
OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */
|
||||
OMAP3_CORE1_IOPAD(0x217a, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
|
||||
OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
|
||||
OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
|
||||
>;
|
||||
};
|
||||
|
@ -107,7 +107,7 @@ uart3_pins: pinmux_uart3_pins {
|
|||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
|
||||
OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
|
||||
OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
|
||||
OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
|
||||
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
|
||||
>;
|
||||
};
|
||||
|
@ -125,7 +125,7 @@ mmc3_2_pins: pinmux_mmc3_2_pins {
|
|||
pinctrl-single,pins = <
|
||||
OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */
|
||||
OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e6, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */
|
||||
>;
|
||||
|
|
|
@ -14,6 +14,29 @@ aliases {
|
|||
display0 = &hdmi0;
|
||||
};
|
||||
|
||||
vmain: fixedregulator-vmain {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmain";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vsys_cobra: fixedregulator-vsys_cobra {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_cobra";
|
||||
vin-supply = <&vmain>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vdds_1v8_main: fixedregulator-vdds_1v8_main {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdds_1v8_main";
|
||||
vin-supply = <&smps7_reg>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vmmcsd_fixed: fixedregulator-mmcsd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
|
@ -309,7 +332,7 @@ OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
|
|||
|
||||
wlcore_irq_pin: pinmux_wlcore_irq_pin {
|
||||
pinctrl-single,pins = <
|
||||
OMAP5_IOPAD(0x40, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
|
||||
OMAP5_IOPAD(0x40, PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
@ -409,6 +432,26 @@ palmas_pmic {
|
|||
|
||||
ti,ldo6-vibrator;
|
||||
|
||||
smps123-in-supply = <&vsys_cobra>;
|
||||
smps45-in-supply = <&vsys_cobra>;
|
||||
smps6-in-supply = <&vsys_cobra>;
|
||||
smps7-in-supply = <&vsys_cobra>;
|
||||
smps8-in-supply = <&vsys_cobra>;
|
||||
smps9-in-supply = <&vsys_cobra>;
|
||||
smps10_out2-in-supply = <&vsys_cobra>;
|
||||
smps10_out1-in-supply = <&vsys_cobra>;
|
||||
ldo1-in-supply = <&vsys_cobra>;
|
||||
ldo2-in-supply = <&vsys_cobra>;
|
||||
ldo3-in-supply = <&vdds_1v8_main>;
|
||||
ldo4-in-supply = <&vdds_1v8_main>;
|
||||
ldo5-in-supply = <&vsys_cobra>;
|
||||
ldo6-in-supply = <&vdds_1v8_main>;
|
||||
ldo7-in-supply = <&vsys_cobra>;
|
||||
ldo8-in-supply = <&vsys_cobra>;
|
||||
ldo9-in-supply = <&vmmcsd_fixed>;
|
||||
ldoln-in-supply = <&vsys_cobra>;
|
||||
ldousb-in-supply = <&vsys_cobra>;
|
||||
|
||||
regulators {
|
||||
smps123_reg: smps123 {
|
||||
/* VDD_OPP_MPU */
|
||||
|
@ -600,7 +643,8 @@ twl6040: twl@4b {
|
|||
pinctrl-0 = <&twl6040_pins>;
|
||||
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
|
||||
ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */
|
||||
|
||||
/* audpwron gpio defined in the board specific dts */
|
||||
|
||||
vio-supply = <&smps7_reg>;
|
||||
v2v1-supply = <&smps9_reg>;
|
||||
|
|
|
@ -35,6 +35,22 @@ tca6416: tca6416@21 {
|
|||
};
|
||||
};
|
||||
|
||||
/* LDO4 is VPP1 - ball AD9 */
|
||||
&ldo4_reg {
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
};
|
||||
|
||||
/*
|
||||
* LDO7 is used for HDMI: VDDA_DSIPORTA - ball AA33, VDDA_DSIPORTC - ball AE33,
|
||||
* VDDA_HDMI - ball AN25
|
||||
*/
|
||||
&ldo7_reg {
|
||||
status = "okay";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
&omap5_pmx_core {
|
||||
i2c4_pins: pinmux_i2c4_pins {
|
||||
pinctrl-single,pins = <
|
||||
|
@ -52,3 +68,13 @@ &tpd12s015 {
|
|||
<&gpio7 3 0>; /* 195, SDA */
|
||||
};
|
||||
|
||||
&twl6040 {
|
||||
ti,audpwron-gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio line 144 */
|
||||
};
|
||||
|
||||
&twl6040_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP5_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_144 */
|
||||
OMAP5_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */
|
||||
>;
|
||||
};
|
||||
|
|
|
@ -51,3 +51,13 @@ &tpd12s015 {
|
|||
<&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */
|
||||
<&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */
|
||||
};
|
||||
|
||||
&twl6040 {
|
||||
ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */
|
||||
};
|
||||
|
||||
&twl6040_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
|
||||
>;
|
||||
};
|
||||
|
|
|
@ -136,6 +136,7 @@ regulator-usb-nrst {
|
|||
&gmac1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
|
||||
snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
|
|
|
@ -24,18 +24,21 @@ gp0_reserved: rproc@40000000 {
|
|||
compatible = "shared-dma-pool";
|
||||
reg = <0x40000000 0x01000000>;
|
||||
no-map;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gp1_reserved: rproc@41000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x41000000 0x01000000>;
|
||||
no-map;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
audio_reserved: rproc@42000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x42000000 0x01000000>;
|
||||
no-map;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmu_reserved: rproc@43000000 {
|
||||
|
|
|
@ -176,8 +176,6 @@ ®_aldo3 {
|
|||
};
|
||||
|
||||
®_dc1sw {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc-lcd";
|
||||
};
|
||||
|
||||
|
|
|
@ -135,8 +135,6 @@ ®_aldo3 {
|
|||
|
||||
®_dc1sw {
|
||||
regulator-name = "vcc-lcd-usb2";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
®_dc5ldo {
|
||||
|
|
|
@ -82,6 +82,7 @@ CONFIG_TOUCHSCREEN_MMS114=y
|
|||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_MAX77693_HAPTIC=y
|
||||
CONFIG_INPUT_MAX8997_HAPTIC=y
|
||||
CONFIG_KEYBOARD_SAMSUNG=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_SAMSUNG=y
|
||||
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
|
||||
|
|
|
@ -264,6 +264,7 @@ CONFIG_KEYBOARD_TEGRA=y
|
|||
CONFIG_KEYBOARD_SPEAR=y
|
||||
CONFIG_KEYBOARD_ST_KEYSCAN=y
|
||||
CONFIG_KEYBOARD_CROS_EC=m
|
||||
CONFIG_KEYBOARD_SAMSUNG=m
|
||||
CONFIG_MOUSE_PS2_ELANTECH=y
|
||||
CONFIG_MOUSE_CYAPA=m
|
||||
CONFIG_MOUSE_ELAN_I2C=y
|
||||
|
|
|
@ -486,7 +486,7 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = {
|
|||
|
||||
static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
|
||||
{
|
||||
trace_ipi_raise(target, ipi_types[ipinr]);
|
||||
trace_ipi_raise_rcuidle(target, ipi_types[ipinr]);
|
||||
__smp_cross_call(target, ipinr);
|
||||
}
|
||||
|
||||
|
|
|
@ -61,7 +61,6 @@ config ARCH_EXYNOS4
|
|||
select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
|
||||
select CPU_EXYNOS4210
|
||||
select GIC_NON_BANKED
|
||||
select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
help
|
||||
Samsung EXYNOS4 (Cortex-A9) SoC based systems
|
||||
|
|
|
@ -46,7 +46,7 @@ static int ksz8081_phy_fixup(struct phy_device *dev)
|
|||
static void __init imx6ul_enet_phy_init(void)
|
||||
{
|
||||
if (IS_BUILTIN(CONFIG_PHYLIB))
|
||||
phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff,
|
||||
phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK,
|
||||
ksz8081_phy_fixup);
|
||||
}
|
||||
|
||||
|
|
|
@ -43,8 +43,8 @@
|
|||
#define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK)
|
||||
|
||||
/* IRQ handler register bitmasks */
|
||||
#define DEFERRED_FIQ_MASK (0x1 << (INT_DEFERRED_FIQ % IH2_BASE))
|
||||
#define GPIO_BANK1_MASK (0x1 << INT_GPIO_BANK1)
|
||||
#define DEFERRED_FIQ_MASK OMAP_IRQ_BIT(INT_DEFERRED_FIQ)
|
||||
#define GPIO_BANK1_MASK OMAP_IRQ_BIT(INT_GPIO_BANK1)
|
||||
|
||||
/* Driver buffer byte offsets */
|
||||
#define BUF_MASK (FIQ_MASK * 4)
|
||||
|
@ -110,7 +110,7 @@ ENTRY(qwerty_fiqin_start)
|
|||
mov r8, #2 @ reset FIQ agreement
|
||||
str r8, [r12, #IRQ_CONTROL_REG_OFFSET]
|
||||
|
||||
cmp r10, #INT_GPIO_BANK1 @ is it GPIO bank interrupt?
|
||||
cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY) @ is it GPIO interrupt?
|
||||
beq gpio @ yes - process it
|
||||
|
||||
mov r8, #1
|
||||
|
|
|
@ -109,7 +109,8 @@ void __init ams_delta_init_fiq(void)
|
|||
* Since no set_type() method is provided by OMAP irq chip,
|
||||
* switch to edge triggered interrupt type manually.
|
||||
*/
|
||||
offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4;
|
||||
offset = IRQ_ILR0_REG_OFFSET +
|
||||
((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4;
|
||||
val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
|
||||
omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
|
||||
|
||||
|
@ -149,7 +150,7 @@ void __init ams_delta_init_fiq(void)
|
|||
/*
|
||||
* Redirect GPIO interrupts to FIQ
|
||||
*/
|
||||
offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4;
|
||||
offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4;
|
||||
val = omap_readl(OMAP_IH1_BASE + offset) | 1;
|
||||
omap_writel(val, OMAP_IH1_BASE + offset);
|
||||
}
|
||||
|
|
|
@ -14,6 +14,8 @@
|
|||
#ifndef __AMS_DELTA_FIQ_H
|
||||
#define __AMS_DELTA_FIQ_H
|
||||
|
||||
#include <mach/irqs.h>
|
||||
|
||||
/*
|
||||
* Interrupt number used for passing control from FIQ to IRQ.
|
||||
* IRQ12, described as reserved, has been selected.
|
||||
|
|
|
@ -17,6 +17,7 @@ config ARCH_OMAP3
|
|||
select PM_OPP if PM
|
||||
select PM if CPU_IDLE
|
||||
select SOC_HAS_OMAP2_SDRC
|
||||
select ARM_ERRATA_430973
|
||||
|
||||
config ARCH_OMAP4
|
||||
bool "TI OMAP4"
|
||||
|
@ -36,6 +37,7 @@ config ARCH_OMAP4
|
|||
select PM if CPU_IDLE
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_775420
|
||||
select OMAP_INTERCONNECT
|
||||
|
||||
config SOC_OMAP5
|
||||
bool "TI OMAP5"
|
||||
|
@ -67,6 +69,8 @@ config SOC_AM43XX
|
|||
select HAVE_ARM_SCU
|
||||
select GENERIC_CLOCKEVENTS_BROADCAST
|
||||
select HAVE_ARM_TWD
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_775420
|
||||
|
||||
config SOC_DRA7XX
|
||||
bool "TI DRA7XX"
|
||||
|
@ -240,4 +244,12 @@ endmenu
|
|||
|
||||
endif
|
||||
|
||||
config OMAP5_ERRATA_801819
|
||||
bool "Errata 801819: An eviction from L1 data cache might stall indefinitely"
|
||||
depends on SOC_OMAP5 || SOC_DRA7XX
|
||||
help
|
||||
A livelock can occur in the L2 cache arbitration that might prevent
|
||||
a snoop from completing. Under certain conditions this can cause the
|
||||
system to deadlock.
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -46,6 +46,7 @@
|
|||
|
||||
#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
|
||||
#define OMAP5_MON_AMBA_IF_INDEX 0x108
|
||||
#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
|
||||
|
||||
/* Secure PPA(Primary Protected Application) APIs */
|
||||
#define OMAP4_PPA_L2_POR_INDEX 0x23
|
||||
|
|
|
@ -50,6 +50,39 @@ void __iomem *omap4_get_scu_base(void)
|
|||
return scu_base;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP5_ERRATA_801819
|
||||
void omap5_erratum_workaround_801819(void)
|
||||
{
|
||||
u32 acr, revidr;
|
||||
u32 acr_mask;
|
||||
|
||||
/* REVIDR[3] indicates erratum fix available on silicon */
|
||||
asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr));
|
||||
if (revidr & (0x1 << 3))
|
||||
return;
|
||||
|
||||
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
|
||||
/*
|
||||
* BIT(27) - Disables streaming. All write-allocate lines allocate in
|
||||
* the L1 or L2 cache.
|
||||
* BIT(25) - Disables streaming. All write-allocate lines allocate in
|
||||
* the L1 cache.
|
||||
*/
|
||||
acr_mask = (0x3 << 25) | (0x3 << 27);
|
||||
/* do we already have it done.. if yes, skip expensive smc */
|
||||
if ((acr & acr_mask) == acr_mask)
|
||||
return;
|
||||
|
||||
acr |= acr_mask;
|
||||
omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
|
||||
|
||||
pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n",
|
||||
__func__, smp_processor_id());
|
||||
}
|
||||
#else
|
||||
static inline void omap5_erratum_workaround_801819(void) { }
|
||||
#endif
|
||||
|
||||
static void omap4_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
|
@ -64,12 +97,15 @@ static void omap4_secondary_init(unsigned int cpu)
|
|||
omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
|
||||
4, 0, 0, 0, 0, 0);
|
||||
|
||||
/*
|
||||
* Configure the CNTFRQ register for the secondary cpu's which
|
||||
* indicates the frequency of the cpu local timers.
|
||||
*/
|
||||
if (soc_is_omap54xx() || soc_is_dra7xx())
|
||||
if (soc_is_omap54xx() || soc_is_dra7xx()) {
|
||||
/*
|
||||
* Configure the CNTFRQ register for the secondary cpu's which
|
||||
* indicates the frequency of the cpu local timers.
|
||||
*/
|
||||
set_cntfreq();
|
||||
/* Configure ACR to disable streaming WA for 801819 */
|
||||
omap5_erratum_workaround_801819();
|
||||
}
|
||||
|
||||
/*
|
||||
* Synchronise with the boot thread.
|
||||
|
@ -218,6 +254,8 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
|
|||
|
||||
if (cpu_is_omap446x())
|
||||
startup_addr = omap4460_secondary_startup;
|
||||
if (soc_is_dra74x() || soc_is_omap54xx())
|
||||
omap5_erratum_workaround_801819();
|
||||
|
||||
/*
|
||||
* Write the address of secondary startup routine into the
|
||||
|
|
|
@ -186,8 +186,9 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
|
|||
trace_state = (PWRDM_TRACE_STATES_FLAG |
|
||||
((next & OMAP_POWERSTATE_MASK) << 8) |
|
||||
((prev & OMAP_POWERSTATE_MASK) << 0));
|
||||
trace_power_domain_target(pwrdm->name, trace_state,
|
||||
smp_processor_id());
|
||||
trace_power_domain_target_rcuidle(pwrdm->name,
|
||||
trace_state,
|
||||
smp_processor_id());
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
@ -523,8 +524,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
|
|||
|
||||
if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
|
||||
/* Trace the pwrdm desired target state */
|
||||
trace_power_domain_target(pwrdm->name, pwrst,
|
||||
smp_processor_id());
|
||||
trace_power_domain_target_rcuidle(pwrdm->name, pwrst,
|
||||
smp_processor_id());
|
||||
/* Program the pwrdm desired target state */
|
||||
ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
|
||||
}
|
||||
|
|
|
@ -36,14 +36,7 @@ static struct powerdomain iva_7xx_pwrdm = {
|
|||
.prcm_offs = DRA7XX_PRM_IVA_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF,
|
||||
.banks = 4,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* hwa_mem */
|
||||
[1] = PWRSTS_OFF_RET, /* sl2_mem */
|
||||
[2] = PWRSTS_OFF_RET, /* tcm1_mem */
|
||||
[3] = PWRSTS_OFF_RET, /* tcm2_mem */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* hwa_mem */
|
||||
[1] = PWRSTS_ON, /* sl2_mem */
|
||||
|
@ -76,12 +69,7 @@ static struct powerdomain ipu_7xx_pwrdm = {
|
|||
.prcm_offs = DRA7XX_PRM_IPU_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF,
|
||||
.banks = 2,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* aessmem */
|
||||
[1] = PWRSTS_OFF_RET, /* periphmem */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* aessmem */
|
||||
[1] = PWRSTS_ON, /* periphmem */
|
||||
|
@ -95,11 +83,7 @@ static struct powerdomain dss_7xx_pwrdm = {
|
|||
.prcm_offs = DRA7XX_PRM_DSS_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* dss_mem */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* dss_mem */
|
||||
},
|
||||
|
@ -111,13 +95,8 @@ static struct powerdomain l4per_7xx_pwrdm = {
|
|||
.name = "l4per_pwrdm",
|
||||
.prcm_offs = DRA7XX_PRM_L4PER_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.banks = 2,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* nonretained_bank */
|
||||
[1] = PWRSTS_OFF_RET, /* retained_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* nonretained_bank */
|
||||
[1] = PWRSTS_ON, /* retained_bank */
|
||||
|
@ -132,9 +111,6 @@ static struct powerdomain gpu_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* gpu_mem */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* gpu_mem */
|
||||
},
|
||||
|
@ -148,8 +124,6 @@ static struct powerdomain wkupaon_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* wkup_bank */
|
||||
},
|
||||
|
@ -161,15 +135,7 @@ static struct powerdomain core_7xx_pwrdm = {
|
|||
.prcm_offs = DRA7XX_PRM_CORE_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
.banks = 5,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
|
||||
[1] = PWRSTS_OFF_RET, /* core_ocmram */
|
||||
[2] = PWRSTS_OFF_RET, /* core_other_bank */
|
||||
[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
|
||||
[4] = PWRSTS_OFF_RET, /* ipu_unicache */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* core_nret_bank */
|
||||
[1] = PWRSTS_ON, /* core_ocmram */
|
||||
|
@ -226,11 +192,7 @@ static struct powerdomain vpe_7xx_pwrdm = {
|
|||
.prcm_offs = DRA7XX_PRM_VPE_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* vpe_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* vpe_bank */
|
||||
},
|
||||
|
@ -260,14 +222,8 @@ static struct powerdomain l3init_7xx_pwrdm = {
|
|||
.name = "l3init_pwrdm",
|
||||
.prcm_offs = DRA7XX_PRM_L3INIT_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.banks = 3,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* gmac_bank */
|
||||
[1] = PWRSTS_OFF_RET, /* l3init_bank1 */
|
||||
[2] = PWRSTS_OFF_RET, /* l3init_bank2 */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* gmac_bank */
|
||||
[1] = PWRSTS_ON, /* l3init_bank1 */
|
||||
|
@ -283,9 +239,6 @@ static struct powerdomain eve3_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* eve3_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* eve3_bank */
|
||||
},
|
||||
|
@ -299,9 +252,6 @@ static struct powerdomain emu_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* emu_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* emu_bank */
|
||||
},
|
||||
|
@ -314,11 +264,6 @@ static struct powerdomain dsp2_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 3,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* dsp2_edma */
|
||||
[1] = PWRSTS_OFF_RET, /* dsp2_l1 */
|
||||
[2] = PWRSTS_OFF_RET, /* dsp2_l2 */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* dsp2_edma */
|
||||
[1] = PWRSTS_ON, /* dsp2_l1 */
|
||||
|
@ -334,11 +279,6 @@ static struct powerdomain dsp1_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 3,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* dsp1_edma */
|
||||
[1] = PWRSTS_OFF_RET, /* dsp1_l1 */
|
||||
[2] = PWRSTS_OFF_RET, /* dsp1_l2 */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* dsp1_edma */
|
||||
[1] = PWRSTS_ON, /* dsp1_l1 */
|
||||
|
@ -354,9 +294,6 @@ static struct powerdomain cam_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* vip_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* vip_bank */
|
||||
},
|
||||
|
@ -370,9 +307,6 @@ static struct powerdomain eve4_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* eve4_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* eve4_bank */
|
||||
},
|
||||
|
@ -386,9 +320,6 @@ static struct powerdomain eve2_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* eve2_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* eve2_bank */
|
||||
},
|
||||
|
@ -402,9 +333,6 @@ static struct powerdomain eve1_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* eve1_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* eve1_bank */
|
||||
},
|
||||
|
|
|
@ -496,8 +496,7 @@ void __init omap_init_time(void)
|
|||
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
|
||||
2, "timer_sys_ck", NULL, false);
|
||||
|
||||
if (of_have_populated_dt())
|
||||
clocksource_probe();
|
||||
clocksource_probe();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
|
||||
|
@ -505,6 +504,8 @@ void __init omap3_secure_sync32k_timer_init(void)
|
|||
{
|
||||
__omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
|
||||
2, "timer_sys_ck", NULL, false);
|
||||
|
||||
clocksource_probe();
|
||||
}
|
||||
#endif /* CONFIG_ARCH_OMAP3 */
|
||||
|
||||
|
@ -513,6 +514,8 @@ void __init omap3_gptimer_timer_init(void)
|
|||
{
|
||||
__omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
|
||||
1, "timer_sys_ck", "ti,timer-alwon", true);
|
||||
|
||||
clocksource_probe();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
@ -68,7 +68,7 @@
|
|||
#include <linux/platform_data/asoc-s3c.h>
|
||||
#include <linux/platform_data/spi-s3c64xx.h>
|
||||
|
||||
static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
|
||||
#define samsung_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
|
||||
|
||||
/* AC97 */
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
|
|
|
@ -125,7 +125,7 @@ amba {
|
|||
#size-cells = <1>;
|
||||
#interrupts-cells = <3>;
|
||||
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
|
|
|
@ -163,7 +163,7 @@ xin24m: xin24m {
|
|||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
|
@ -398,7 +398,7 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
|
|||
gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
|
||||
GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
|
||||
gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
|
||||
GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
|
||||
GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
|
||||
gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
|
||||
GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
|
||||
p->cycle2cyclesamecsen);
|
||||
|
|
Loading…
Reference in New Issue
Block a user