forked from luck/tmp_suning_uos_patched
[MFD] Add code UCB1200/UCB1300 device support
Add the core device support code for the Philips UCB1200 and UCB1300 devices. Also includes the following from Pavel: This fixes u32 vs. pm_message_t confusion and uses cleaner try_to_freeze() [fixing compilation as a side-effect on newer kernels.] Signed-off-by: Pavel Machek <pavel@suse.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
Russell King
parent
2f79f458d2
commit
05c45ca9aa
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@ -13,4 +13,9 @@ config MCP_SA11X0
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depends on ARCH_SA1100
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select MCP
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# Chip drivers
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config MCP_UCB1200
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tristate "Support for UCB1200 / UCB1300"
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depends on MCP
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endmenu
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@ -4,3 +4,4 @@
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obj-$(CONFIG_MCP) += mcp-core.o
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obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o
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obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o
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665
drivers/mfd/ucb1x00-core.c
Normal file
665
drivers/mfd/ucb1x00-core.c
Normal file
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@ -0,0 +1,665 @@
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/*
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* linux/drivers/mfd/ucb1x00-core.c
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*
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* Copyright (C) 2001 Russell King, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*
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* The UCB1x00 core driver provides basic services for handling IO,
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* the ADC, interrupts, and accessing registers. It is designed
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* such that everything goes through this layer, thereby providing
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* a consistent locking methodology, as well as allowing the drivers
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* to be used on other non-MCP-enabled hardware platforms.
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*
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* Note that all locks are private to this file. Nothing else may
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* touch them.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <asm/dma.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include "ucb1x00.h"
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static DECLARE_MUTEX(ucb1x00_sem);
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static LIST_HEAD(ucb1x00_drivers);
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static LIST_HEAD(ucb1x00_devices);
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/**
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* ucb1x00_io_set_dir - set IO direction
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* @ucb: UCB1x00 structure describing chip
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* @in: bitfield of IO pins to be set as inputs
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* @out: bitfield of IO pins to be set as outputs
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*
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* Set the IO direction of the ten general purpose IO pins on
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* the UCB1x00 chip. The @in bitfield has priority over the
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* @out bitfield, in that if you specify a pin as both input
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* and output, it will end up as an input.
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*
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* ucb1x00_enable must have been called to enable the comms
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* before using this function.
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*
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* This function takes a spinlock, disabling interrupts.
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*/
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void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out)
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{
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unsigned long flags;
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spin_lock_irqsave(&ucb->io_lock, flags);
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ucb->io_dir |= out;
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ucb->io_dir &= ~in;
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ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
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spin_unlock_irqrestore(&ucb->io_lock, flags);
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}
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/**
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* ucb1x00_io_write - set or clear IO outputs
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* @ucb: UCB1x00 structure describing chip
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* @set: bitfield of IO pins to set to logic '1'
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* @clear: bitfield of IO pins to set to logic '0'
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*
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* Set the IO output state of the specified IO pins. The value
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* is retained if the pins are subsequently configured as inputs.
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* The @clear bitfield has priority over the @set bitfield -
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* outputs will be cleared.
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*
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* ucb1x00_enable must have been called to enable the comms
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* before using this function.
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*
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* This function takes a spinlock, disabling interrupts.
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*/
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void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear)
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{
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unsigned long flags;
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spin_lock_irqsave(&ucb->io_lock, flags);
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ucb->io_out |= set;
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ucb->io_out &= ~clear;
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ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
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spin_unlock_irqrestore(&ucb->io_lock, flags);
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}
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/**
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* ucb1x00_io_read - read the current state of the IO pins
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* @ucb: UCB1x00 structure describing chip
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*
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* Return a bitfield describing the logic state of the ten
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* general purpose IO pins.
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*
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* ucb1x00_enable must have been called to enable the comms
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* before using this function.
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*
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* This function does not take any semaphores or spinlocks.
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*/
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unsigned int ucb1x00_io_read(struct ucb1x00 *ucb)
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{
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return ucb1x00_reg_read(ucb, UCB_IO_DATA);
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}
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/*
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* UCB1300 data sheet says we must:
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* 1. enable ADC => 5us (including reference startup time)
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* 2. select input => 51*tsibclk => 4.3us
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* 3. start conversion => 102*tsibclk => 8.5us
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* (tsibclk = 1/11981000)
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* Period between SIB 128-bit frames = 10.7us
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*/
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/**
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* ucb1x00_adc_enable - enable the ADC converter
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* @ucb: UCB1x00 structure describing chip
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*
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* Enable the ucb1x00 and ADC converter on the UCB1x00 for use.
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* Any code wishing to use the ADC converter must call this
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* function prior to using it.
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*
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* This function takes the ADC semaphore to prevent two or more
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* concurrent uses, and therefore may sleep. As a result, it
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* can only be called from process context, not interrupt
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* context.
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*
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* You should release the ADC as soon as possible using
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* ucb1x00_adc_disable.
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*/
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void ucb1x00_adc_enable(struct ucb1x00 *ucb)
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{
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down(&ucb->adc_sem);
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ucb->adc_cr |= UCB_ADC_ENA;
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ucb1x00_enable(ucb);
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ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
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}
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/**
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* ucb1x00_adc_read - read the specified ADC channel
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* @ucb: UCB1x00 structure describing chip
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* @adc_channel: ADC channel mask
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* @sync: wait for syncronisation pulse.
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*
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* Start an ADC conversion and wait for the result. Note that
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* synchronised ADC conversions (via the ADCSYNC pin) must wait
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* until the trigger is asserted and the conversion is finished.
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*
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* This function currently spins waiting for the conversion to
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* complete (2 frames max without sync).
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*
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* If called for a synchronised ADC conversion, it may sleep
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* with the ADC semaphore held.
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*/
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unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync)
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{
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unsigned int val;
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if (sync)
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adc_channel |= UCB_ADC_SYNC_ENA;
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ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel);
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ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START);
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for (;;) {
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val = ucb1x00_reg_read(ucb, UCB_ADC_DATA);
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if (val & UCB_ADC_DAT_VAL)
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break;
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/* yield to other processes */
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set_current_state(TASK_INTERRUPTIBLE);
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schedule_timeout(1);
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}
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return UCB_ADC_DAT(val);
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}
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/**
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* ucb1x00_adc_disable - disable the ADC converter
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* @ucb: UCB1x00 structure describing chip
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*
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* Disable the ADC converter and release the ADC semaphore.
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*/
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void ucb1x00_adc_disable(struct ucb1x00 *ucb)
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{
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ucb->adc_cr &= ~UCB_ADC_ENA;
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ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
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ucb1x00_disable(ucb);
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up(&ucb->adc_sem);
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}
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/*
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* UCB1x00 Interrupt handling.
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*
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* The UCB1x00 can generate interrupts when the SIBCLK is stopped.
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* Since we need to read an internal register, we must re-enable
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* SIBCLK to talk to the chip. We leave the clock running until
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* we have finished processing all interrupts from the chip.
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*/
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static irqreturn_t ucb1x00_irq(int irqnr, void *devid, struct pt_regs *regs)
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{
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struct ucb1x00 *ucb = devid;
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struct ucb1x00_irq *irq;
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unsigned int isr, i;
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ucb1x00_enable(ucb);
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isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS);
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ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
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ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
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for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++)
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if (isr & 1 && irq->fn)
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irq->fn(i, irq->devid);
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ucb1x00_disable(ucb);
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return IRQ_HANDLED;
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}
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/**
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* ucb1x00_hook_irq - hook a UCB1x00 interrupt
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* @ucb: UCB1x00 structure describing chip
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* @idx: interrupt index
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* @fn: function to call when interrupt is triggered
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* @devid: device id to pass to interrupt handler
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*
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* Hook the specified interrupt. You can only register one handler
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* for each interrupt source. The interrupt source is not enabled
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* by this function; use ucb1x00_enable_irq instead.
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*
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* Interrupt handlers will be called with other interrupts enabled.
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*
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* Returns zero on success, or one of the following errors:
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* -EINVAL if the interrupt index is invalid
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* -EBUSY if the interrupt has already been hooked
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*/
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int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid)
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{
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struct ucb1x00_irq *irq;
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int ret = -EINVAL;
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if (idx < 16) {
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irq = ucb->irq_handler + idx;
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ret = -EBUSY;
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spin_lock_irq(&ucb->lock);
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if (irq->fn == NULL) {
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irq->devid = devid;
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irq->fn = fn;
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ret = 0;
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}
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spin_unlock_irq(&ucb->lock);
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}
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return ret;
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}
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/**
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* ucb1x00_enable_irq - enable an UCB1x00 interrupt source
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* @ucb: UCB1x00 structure describing chip
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* @idx: interrupt index
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* @edges: interrupt edges to enable
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*
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* Enable the specified interrupt to trigger on %UCB_RISING,
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* %UCB_FALLING or both edges. The interrupt should have been
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* hooked by ucb1x00_hook_irq.
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*/
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void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
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{
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unsigned long flags;
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if (idx < 16) {
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spin_lock_irqsave(&ucb->lock, flags);
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ucb1x00_enable(ucb);
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if (edges & UCB_RISING) {
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ucb->irq_ris_enbl |= 1 << idx;
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ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
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}
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if (edges & UCB_FALLING) {
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ucb->irq_fal_enbl |= 1 << idx;
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ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
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}
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ucb1x00_disable(ucb);
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spin_unlock_irqrestore(&ucb->lock, flags);
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}
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}
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/**
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* ucb1x00_disable_irq - disable an UCB1x00 interrupt source
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* @ucb: UCB1x00 structure describing chip
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* @edges: interrupt edges to disable
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*
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* Disable the specified interrupt triggering on the specified
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* (%UCB_RISING, %UCB_FALLING or both) edges.
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*/
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void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
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{
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unsigned long flags;
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if (idx < 16) {
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spin_lock_irqsave(&ucb->lock, flags);
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ucb1x00_enable(ucb);
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if (edges & UCB_RISING) {
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ucb->irq_ris_enbl &= ~(1 << idx);
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ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
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}
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if (edges & UCB_FALLING) {
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ucb->irq_fal_enbl &= ~(1 << idx);
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ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
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}
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ucb1x00_disable(ucb);
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spin_unlock_irqrestore(&ucb->lock, flags);
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}
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}
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/**
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* ucb1x00_free_irq - disable and free the specified UCB1x00 interrupt
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* @ucb: UCB1x00 structure describing chip
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* @idx: interrupt index
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* @devid: device id.
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*
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* Disable the interrupt source and remove the handler. devid must
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* match the devid passed when hooking the interrupt.
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*
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* Returns zero on success, or one of the following errors:
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* -EINVAL if the interrupt index is invalid
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* -ENOENT if devid does not match
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*/
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int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid)
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{
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struct ucb1x00_irq *irq;
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int ret;
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if (idx >= 16)
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goto bad;
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irq = ucb->irq_handler + idx;
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ret = -ENOENT;
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spin_lock_irq(&ucb->lock);
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if (irq->devid == devid) {
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ucb->irq_ris_enbl &= ~(1 << idx);
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ucb->irq_fal_enbl &= ~(1 << idx);
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ucb1x00_enable(ucb);
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ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
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ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
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ucb1x00_disable(ucb);
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irq->fn = NULL;
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irq->devid = NULL;
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ret = 0;
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}
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spin_unlock_irq(&ucb->lock);
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return ret;
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bad:
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printk(KERN_ERR "Freeing bad UCB1x00 irq %d\n", idx);
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return -EINVAL;
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}
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static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv)
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{
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struct ucb1x00_dev *dev;
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int ret = -ENOMEM;
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dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL);
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if (dev) {
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dev->ucb = ucb;
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dev->drv = drv;
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ret = drv->add(dev);
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if (ret == 0) {
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list_add(&dev->dev_node, &ucb->devs);
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list_add(&dev->drv_node, &drv->devs);
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} else {
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kfree(dev);
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}
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}
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return ret;
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}
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static void ucb1x00_remove_dev(struct ucb1x00_dev *dev)
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{
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dev->drv->remove(dev);
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list_del(&dev->dev_node);
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list_del(&dev->drv_node);
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kfree(dev);
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}
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/*
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* Try to probe our interrupt, rather than relying on lots of
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* hard-coded machine dependencies. For reference, the expected
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* IRQ mappings are:
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*
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* Machine Default IRQ
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* adsbitsy IRQ_GPCIN4
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* cerf IRQ_GPIO_UCB1200_IRQ
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* flexanet IRQ_GPIO_GUI
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* freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ
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* graphicsclient ADS_EXT_IRQ(8)
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* graphicsmaster ADS_EXT_IRQ(8)
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* lart LART_IRQ_UCB1200
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* omnimeter IRQ_GPIO23
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* pfs168 IRQ_GPIO_UCB1300_IRQ
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* simpad IRQ_GPIO_UCB1300_IRQ
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* shannon SHANNON_IRQ_GPIO_IRQ_CODEC
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* yopy IRQ_GPIO_UCB1200_IRQ
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*/
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static int ucb1x00_detect_irq(struct ucb1x00 *ucb)
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{
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unsigned long mask;
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mask = probe_irq_on();
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if (!mask)
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return NO_IRQ;
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/*
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* Enable the ADC interrupt.
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*/
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ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
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ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
|
||||
ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
|
||||
ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
|
||||
|
||||
/*
|
||||
* Cause an ADC interrupt.
|
||||
*/
|
||||
ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
|
||||
ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
|
||||
|
||||
/*
|
||||
* Wait for the conversion to complete.
|
||||
*/
|
||||
while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0);
|
||||
ucb1x00_reg_write(ucb, UCB_ADC_CR, 0);
|
||||
|
||||
/*
|
||||
* Disable and clear interrupt.
|
||||
*/
|
||||
ucb1x00_reg_write(ucb, UCB_IE_RIS, 0);
|
||||
ucb1x00_reg_write(ucb, UCB_IE_FAL, 0);
|
||||
ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
|
||||
ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
|
||||
|
||||
/*
|
||||
* Read triggered interrupt.
|
||||
*/
|
||||
return probe_irq_off(mask);
|
||||
}
|
||||
|
||||
static int ucb1x00_probe(struct mcp *mcp)
|
||||
{
|
||||
struct ucb1x00 *ucb;
|
||||
struct ucb1x00_driver *drv;
|
||||
unsigned int id;
|
||||
int ret = -ENODEV;
|
||||
|
||||
mcp_enable(mcp);
|
||||
id = mcp_reg_read(mcp, UCB_ID);
|
||||
|
||||
if (id != UCB_ID_1200 && id != UCB_ID_1300) {
|
||||
printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id);
|
||||
goto err_disable;
|
||||
}
|
||||
|
||||
ucb = kmalloc(sizeof(struct ucb1x00), GFP_KERNEL);
|
||||
ret = -ENOMEM;
|
||||
if (!ucb)
|
||||
goto err_disable;
|
||||
|
||||
memset(ucb, 0, sizeof(struct ucb1x00));
|
||||
|
||||
ucb->cdev.class = &ucb1x00_class;
|
||||
ucb->cdev.dev = &mcp->attached_device;
|
||||
strlcpy(ucb->cdev.class_id, "ucb1x00", sizeof(ucb->cdev.class_id));
|
||||
|
||||
spin_lock_init(&ucb->lock);
|
||||
spin_lock_init(&ucb->io_lock);
|
||||
sema_init(&ucb->adc_sem, 1);
|
||||
|
||||
ucb->id = id;
|
||||
ucb->mcp = mcp;
|
||||
ucb->irq = ucb1x00_detect_irq(ucb);
|
||||
if (ucb->irq == NO_IRQ) {
|
||||
printk(KERN_ERR "UCB1x00: IRQ probe failed\n");
|
||||
ret = -ENODEV;
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
ret = request_irq(ucb->irq, ucb1x00_irq, 0, "UCB1x00", ucb);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "ucb1x00: unable to grab irq%d: %d\n",
|
||||
ucb->irq, ret);
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
set_irq_type(ucb->irq, IRQT_RISING);
|
||||
mcp_set_drvdata(mcp, ucb);
|
||||
|
||||
ret = class_device_register(&ucb->cdev);
|
||||
if (ret)
|
||||
goto err_irq;
|
||||
|
||||
INIT_LIST_HEAD(&ucb->devs);
|
||||
down(&ucb1x00_sem);
|
||||
list_add(&ucb->node, &ucb1x00_devices);
|
||||
list_for_each_entry(drv, &ucb1x00_drivers, node) {
|
||||
ucb1x00_add_dev(ucb, drv);
|
||||
}
|
||||
up(&ucb1x00_sem);
|
||||
goto out;
|
||||
|
||||
err_irq:
|
||||
free_irq(ucb->irq, ucb);
|
||||
err_free:
|
||||
kfree(ucb);
|
||||
err_disable:
|
||||
mcp_disable(mcp);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ucb1x00_remove(struct mcp *mcp)
|
||||
{
|
||||
struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
|
||||
struct list_head *l, *n;
|
||||
|
||||
down(&ucb1x00_sem);
|
||||
list_del(&ucb->node);
|
||||
list_for_each_safe(l, n, &ucb->devs) {
|
||||
struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node);
|
||||
ucb1x00_remove_dev(dev);
|
||||
}
|
||||
up(&ucb1x00_sem);
|
||||
|
||||
free_irq(ucb->irq, ucb);
|
||||
class_device_unregister(&ucb->cdev);
|
||||
}
|
||||
|
||||
static void ucb1x00_release(struct class_device *dev)
|
||||
{
|
||||
struct ucb1x00 *ucb = classdev_to_ucb1x00(dev);
|
||||
kfree(ucb);
|
||||
}
|
||||
|
||||
static struct class ucb1x00_class = {
|
||||
.name = "ucb1x00",
|
||||
.release = ucb1x00_release,
|
||||
};
|
||||
|
||||
int ucb1x00_register_driver(struct ucb1x00_driver *drv)
|
||||
{
|
||||
struct ucb1x00 *ucb;
|
||||
|
||||
INIT_LIST_HEAD(&drv->devs);
|
||||
down(&ucb1x00_sem);
|
||||
list_add(&drv->node, &ucb1x00_drivers);
|
||||
list_for_each_entry(ucb, &ucb1x00_devices, node) {
|
||||
ucb1x00_add_dev(ucb, drv);
|
||||
}
|
||||
up(&ucb1x00_sem);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ucb1x00_unregister_driver(struct ucb1x00_driver *drv)
|
||||
{
|
||||
struct list_head *n, *l;
|
||||
|
||||
down(&ucb1x00_sem);
|
||||
list_del(&drv->node);
|
||||
list_for_each_safe(l, n, &drv->devs) {
|
||||
struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node);
|
||||
ucb1x00_remove_dev(dev);
|
||||
}
|
||||
up(&ucb1x00_sem);
|
||||
}
|
||||
|
||||
static int ucb1x00_suspend(struct mcp *mcp, pm_message_t state)
|
||||
{
|
||||
struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
|
||||
struct ucb1x00_dev *dev;
|
||||
|
||||
down(&ucb1x00_sem);
|
||||
list_for_each_entry(dev, &ucb->devs, dev_node) {
|
||||
if (dev->drv->suspend)
|
||||
dev->drv->suspend(dev, state);
|
||||
}
|
||||
up(&ucb1x00_sem);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ucb1x00_resume(struct mcp *mcp)
|
||||
{
|
||||
struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
|
||||
struct ucb1x00_dev *dev;
|
||||
|
||||
down(&ucb1x00_sem);
|
||||
list_for_each_entry(dev, &ucb->devs, dev_node) {
|
||||
if (dev->drv->resume)
|
||||
dev->drv->resume(dev);
|
||||
}
|
||||
up(&ucb1x00_sem);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct mcp_driver ucb1x00_driver = {
|
||||
.drv = {
|
||||
.name = "ucb1x00",
|
||||
},
|
||||
.probe = ucb1x00_probe,
|
||||
.remove = ucb1x00_remove,
|
||||
.suspend = ucb1x00_suspend,
|
||||
.resume = ucb1x00_resume,
|
||||
};
|
||||
|
||||
static int __init ucb1x00_init(void)
|
||||
{
|
||||
int ret = class_register(&ucb1x00_class);
|
||||
if (ret == 0) {
|
||||
ret = mcp_driver_register(&ucb1x00_driver);
|
||||
if (ret)
|
||||
class_unregister(&ucb1x00_class);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit ucb1x00_exit(void)
|
||||
{
|
||||
mcp_driver_unregister(&ucb1x00_driver);
|
||||
class_unregister(&ucb1x00_class);
|
||||
}
|
||||
|
||||
module_init(ucb1x00_init);
|
||||
module_exit(ucb1x00_exit);
|
||||
|
||||
EXPORT_SYMBOL(ucb1x00_class);
|
||||
|
||||
EXPORT_SYMBOL(ucb1x00_io_set_dir);
|
||||
EXPORT_SYMBOL(ucb1x00_io_write);
|
||||
EXPORT_SYMBOL(ucb1x00_io_read);
|
||||
|
||||
EXPORT_SYMBOL(ucb1x00_adc_enable);
|
||||
EXPORT_SYMBOL(ucb1x00_adc_read);
|
||||
EXPORT_SYMBOL(ucb1x00_adc_disable);
|
||||
|
||||
EXPORT_SYMBOL(ucb1x00_hook_irq);
|
||||
EXPORT_SYMBOL(ucb1x00_free_irq);
|
||||
EXPORT_SYMBOL(ucb1x00_enable_irq);
|
||||
EXPORT_SYMBOL(ucb1x00_disable_irq);
|
||||
|
||||
EXPORT_SYMBOL(ucb1x00_register_driver);
|
||||
EXPORT_SYMBOL(ucb1x00_unregister_driver);
|
||||
|
||||
MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
|
||||
MODULE_DESCRIPTION("UCB1x00 core driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
256
drivers/mfd/ucb1x00.h
Normal file
256
drivers/mfd/ucb1x00.h
Normal file
|
|
@ -0,0 +1,256 @@
|
|||
/*
|
||||
* linux/drivers/mfd/ucb1x00.h
|
||||
*
|
||||
* Copyright (C) 2001 Russell King, All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License.
|
||||
*/
|
||||
#ifndef UCB1200_H
|
||||
#define UCB1200_H
|
||||
|
||||
#define UCB_IO_DATA 0x00
|
||||
#define UCB_IO_DIR 0x01
|
||||
|
||||
#define UCB_IO_0 (1 << 0)
|
||||
#define UCB_IO_1 (1 << 1)
|
||||
#define UCB_IO_2 (1 << 2)
|
||||
#define UCB_IO_3 (1 << 3)
|
||||
#define UCB_IO_4 (1 << 4)
|
||||
#define UCB_IO_5 (1 << 5)
|
||||
#define UCB_IO_6 (1 << 6)
|
||||
#define UCB_IO_7 (1 << 7)
|
||||
#define UCB_IO_8 (1 << 8)
|
||||
#define UCB_IO_9 (1 << 9)
|
||||
|
||||
#define UCB_IE_RIS 0x02
|
||||
#define UCB_IE_FAL 0x03
|
||||
#define UCB_IE_STATUS 0x04
|
||||
#define UCB_IE_CLEAR 0x04
|
||||
#define UCB_IE_ADC (1 << 11)
|
||||
#define UCB_IE_TSPX (1 << 12)
|
||||
#define UCB_IE_TSMX (1 << 13)
|
||||
#define UCB_IE_TCLIP (1 << 14)
|
||||
#define UCB_IE_ACLIP (1 << 15)
|
||||
|
||||
#define UCB_IRQ_TSPX 12
|
||||
|
||||
#define UCB_TC_A 0x05
|
||||
#define UCB_TC_A_LOOP (1 << 7) /* UCB1200 */
|
||||
#define UCB_TC_A_AMPL (1 << 7) /* UCB1300 */
|
||||
|
||||
#define UCB_TC_B 0x06
|
||||
#define UCB_TC_B_VOICE_ENA (1 << 3)
|
||||
#define UCB_TC_B_CLIP (1 << 4)
|
||||
#define UCB_TC_B_ATT (1 << 6)
|
||||
#define UCB_TC_B_SIDE_ENA (1 << 11)
|
||||
#define UCB_TC_B_MUTE (1 << 13)
|
||||
#define UCB_TC_B_IN_ENA (1 << 14)
|
||||
#define UCB_TC_B_OUT_ENA (1 << 15)
|
||||
|
||||
#define UCB_AC_A 0x07
|
||||
#define UCB_AC_B 0x08
|
||||
#define UCB_AC_B_LOOP (1 << 8)
|
||||
#define UCB_AC_B_MUTE (1 << 13)
|
||||
#define UCB_AC_B_IN_ENA (1 << 14)
|
||||
#define UCB_AC_B_OUT_ENA (1 << 15)
|
||||
|
||||
#define UCB_TS_CR 0x09
|
||||
#define UCB_TS_CR_TSMX_POW (1 << 0)
|
||||
#define UCB_TS_CR_TSPX_POW (1 << 1)
|
||||
#define UCB_TS_CR_TSMY_POW (1 << 2)
|
||||
#define UCB_TS_CR_TSPY_POW (1 << 3)
|
||||
#define UCB_TS_CR_TSMX_GND (1 << 4)
|
||||
#define UCB_TS_CR_TSPX_GND (1 << 5)
|
||||
#define UCB_TS_CR_TSMY_GND (1 << 6)
|
||||
#define UCB_TS_CR_TSPY_GND (1 << 7)
|
||||
#define UCB_TS_CR_MODE_INT (0 << 8)
|
||||
#define UCB_TS_CR_MODE_PRES (1 << 8)
|
||||
#define UCB_TS_CR_MODE_POS (2 << 8)
|
||||
#define UCB_TS_CR_BIAS_ENA (1 << 11)
|
||||
#define UCB_TS_CR_TSPX_LOW (1 << 12)
|
||||
#define UCB_TS_CR_TSMX_LOW (1 << 13)
|
||||
|
||||
#define UCB_ADC_CR 0x0a
|
||||
#define UCB_ADC_SYNC_ENA (1 << 0)
|
||||
#define UCB_ADC_VREFBYP_CON (1 << 1)
|
||||
#define UCB_ADC_INP_TSPX (0 << 2)
|
||||
#define UCB_ADC_INP_TSMX (1 << 2)
|
||||
#define UCB_ADC_INP_TSPY (2 << 2)
|
||||
#define UCB_ADC_INP_TSMY (3 << 2)
|
||||
#define UCB_ADC_INP_AD0 (4 << 2)
|
||||
#define UCB_ADC_INP_AD1 (5 << 2)
|
||||
#define UCB_ADC_INP_AD2 (6 << 2)
|
||||
#define UCB_ADC_INP_AD3 (7 << 2)
|
||||
#define UCB_ADC_EXT_REF (1 << 5)
|
||||
#define UCB_ADC_START (1 << 7)
|
||||
#define UCB_ADC_ENA (1 << 15)
|
||||
|
||||
#define UCB_ADC_DATA 0x0b
|
||||
#define UCB_ADC_DAT_VAL (1 << 15)
|
||||
#define UCB_ADC_DAT(x) (((x) & 0x7fe0) >> 5)
|
||||
|
||||
#define UCB_ID 0x0c
|
||||
#define UCB_ID_1200 0x1004
|
||||
#define UCB_ID_1300 0x1005
|
||||
|
||||
#define UCB_MODE 0x0d
|
||||
#define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
|
||||
#define UCB_MODE_AUD_OFF_CAN (1 << 13)
|
||||
|
||||
#include "mcp.h"
|
||||
|
||||
struct ucb1x00_irq {
|
||||
void *devid;
|
||||
void (*fn)(int, void *);
|
||||
};
|
||||
|
||||
extern struct class ucb1x00_class;
|
||||
|
||||
struct ucb1x00 {
|
||||
spinlock_t lock;
|
||||
struct mcp *mcp;
|
||||
unsigned int irq;
|
||||
struct semaphore adc_sem;
|
||||
spinlock_t io_lock;
|
||||
u16 id;
|
||||
u16 io_dir;
|
||||
u16 io_out;
|
||||
u16 adc_cr;
|
||||
u16 irq_fal_enbl;
|
||||
u16 irq_ris_enbl;
|
||||
struct ucb1x00_irq irq_handler[16];
|
||||
struct class_device cdev;
|
||||
struct list_head node;
|
||||
struct list_head devs;
|
||||
};
|
||||
|
||||
struct ucb1x00_driver;
|
||||
|
||||
struct ucb1x00_dev {
|
||||
struct list_head dev_node;
|
||||
struct list_head drv_node;
|
||||
struct ucb1x00 *ucb;
|
||||
struct ucb1x00_driver *drv;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
struct ucb1x00_driver {
|
||||
struct list_head node;
|
||||
struct list_head devs;
|
||||
int (*add)(struct ucb1x00_dev *dev);
|
||||
void (*remove)(struct ucb1x00_dev *dev);
|
||||
int (*suspend)(struct ucb1x00_dev *dev, pm_message_t state);
|
||||
int (*resume)(struct ucb1x00_dev *dev);
|
||||
};
|
||||
|
||||
#define classdev_to_ucb1x00(cd) container_of(cd, struct ucb1x00, cdev)
|
||||
|
||||
int ucb1x00_register_driver(struct ucb1x00_driver *);
|
||||
void ucb1x00_unregister_driver(struct ucb1x00_driver *);
|
||||
|
||||
/**
|
||||
* ucb1x00_clkrate - return the UCB1x00 SIB clock rate
|
||||
* @ucb: UCB1x00 structure describing chip
|
||||
*
|
||||
* Return the SIB clock rate in Hz.
|
||||
*/
|
||||
static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
|
||||
{
|
||||
return mcp_get_sclk_rate(ucb->mcp);
|
||||
}
|
||||
|
||||
/**
|
||||
* ucb1x00_enable - enable the UCB1x00 SIB clock
|
||||
* @ucb: UCB1x00 structure describing chip
|
||||
*
|
||||
* Enable the SIB clock. This can be called multiple times.
|
||||
*/
|
||||
static inline void ucb1x00_enable(struct ucb1x00 *ucb)
|
||||
{
|
||||
mcp_enable(ucb->mcp);
|
||||
}
|
||||
|
||||
/**
|
||||
* ucb1x00_disable - disable the UCB1x00 SIB clock
|
||||
* @ucb: UCB1x00 structure describing chip
|
||||
*
|
||||
* Disable the SIB clock. The SIB clock will only be disabled
|
||||
* when the number of ucb1x00_enable calls match the number of
|
||||
* ucb1x00_disable calls.
|
||||
*/
|
||||
static inline void ucb1x00_disable(struct ucb1x00 *ucb)
|
||||
{
|
||||
mcp_disable(ucb->mcp);
|
||||
}
|
||||
|
||||
/**
|
||||
* ucb1x00_reg_write - write a UCB1x00 register
|
||||
* @ucb: UCB1x00 structure describing chip
|
||||
* @reg: UCB1x00 4-bit register index to write
|
||||
* @val: UCB1x00 16-bit value to write
|
||||
*
|
||||
* Write the UCB1x00 register @reg with value @val. The SIB
|
||||
* clock must be running for this function to return.
|
||||
*/
|
||||
static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
|
||||
{
|
||||
mcp_reg_write(ucb->mcp, reg, val);
|
||||
}
|
||||
|
||||
/**
|
||||
* ucb1x00_reg_read - read a UCB1x00 register
|
||||
* @ucb: UCB1x00 structure describing chip
|
||||
* @reg: UCB1x00 4-bit register index to write
|
||||
*
|
||||
* Read the UCB1x00 register @reg and return its value. The SIB
|
||||
* clock must be running for this function to return.
|
||||
*/
|
||||
static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
|
||||
{
|
||||
return mcp_reg_read(ucb->mcp, reg);
|
||||
}
|
||||
/**
|
||||
* ucb1x00_set_audio_divisor -
|
||||
* @ucb: UCB1x00 structure describing chip
|
||||
* @div: SIB clock divisor
|
||||
*/
|
||||
static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
|
||||
{
|
||||
mcp_set_audio_divisor(ucb->mcp, div);
|
||||
}
|
||||
|
||||
/**
|
||||
* ucb1x00_set_telecom_divisor -
|
||||
* @ucb: UCB1x00 structure describing chip
|
||||
* @div: SIB clock divisor
|
||||
*/
|
||||
static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
|
||||
{
|
||||
mcp_set_telecom_divisor(ucb->mcp, div);
|
||||
}
|
||||
|
||||
void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
|
||||
void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
|
||||
unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
|
||||
|
||||
#define UCB_NOSYNC (0)
|
||||
#define UCB_SYNC (1)
|
||||
|
||||
unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
|
||||
void ucb1x00_adc_enable(struct ucb1x00 *ucb);
|
||||
void ucb1x00_adc_disable(struct ucb1x00 *ucb);
|
||||
|
||||
/*
|
||||
* Which edges of the IRQ do you want to control today?
|
||||
*/
|
||||
#define UCB_RISING (1 << 0)
|
||||
#define UCB_FALLING (1 << 1)
|
||||
|
||||
int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid);
|
||||
void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
|
||||
void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
|
||||
int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user