forked from luck/tmp_suning_uos_patched
powerpc/dma: remove set_dma_offset
There is no good reason for this helper, just opencode it. Signed-off-by: Christoph Hellwig <hch@lst.de> Tested-by: Christian Zigotzky <chzigotzky@xenosoft.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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7610fdf5e0
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0617fc0ca4
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@ -43,11 +43,5 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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return NULL;
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}
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static inline void set_dma_offset(struct device *dev, dma_addr_t off)
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{
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if (dev)
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dev->archdata.dma_offset = off;
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_DMA_MAPPING_H */
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@ -966,7 +966,7 @@ static void pcibios_setup_device(struct pci_dev *dev)
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/* Hook up default DMA ops */
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set_dma_ops(&dev->dev, pci_dma_ops);
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set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
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dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
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/* Additional platform DMA/iommu setup */
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phb = pci_bus_to_host(dev->bus);
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@ -577,10 +577,10 @@ static void cell_dma_dev_setup(struct device *dev)
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u64 addr = cell_iommu_get_fixed_address(dev);
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if (addr != OF_BAD_ADDR)
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set_dma_offset(dev, addr + dma_iommu_fixed_base);
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dev->archdata.dma_offset = addr + dma_iommu_fixed_base;
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set_iommu_table_base(dev, cell_get_iommu_table(dev));
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} else {
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set_dma_offset(dev, cell_dma_nommu_offset);
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dev->archdata.dma_offset = cell_dma_nommu_offset;
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}
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}
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@ -1746,7 +1746,7 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev
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pe = &phb->ioda.pe_array[pdn->pe_number];
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WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
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set_dma_offset(&pdev->dev, pe->tce_bypass_base);
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pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
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set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
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/*
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* Note: iommu_add_device() will fail here as
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@ -1859,7 +1859,7 @@ static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
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if (rc)
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return rc;
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/* 4GB offset bypasses 32-bit space */
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set_dma_offset(&pdev->dev, (1ULL << 32));
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pdev->dev.archdata.dma_offset = (1ULL << 32);
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return true;
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}
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@ -1872,7 +1872,7 @@ static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
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list_for_each_entry(dev, &bus->devices, bus_list) {
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set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
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set_dma_offset(&dev->dev, pe->tce_bypass_base);
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dev->dev.archdata.dma_offset = pe->tce_bypass_base;
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if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
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pnv_ioda_setup_bus_dma(pe, dev->subordinate);
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@ -1202,7 +1202,6 @@ static bool iommu_bypass_supported_pSeriesLP(struct pci_dev *pdev, u64 dma_mask)
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{
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struct device_node *dn = pci_device_to_OF_node(pdev), *pdn;
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const __be32 *dma_window = NULL;
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u64 dma_offset;
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/* only attempt to use a new window if 64-bit DMA is requested */
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if (dma_mask < DMA_BIT_MASK(64))
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@ -1224,11 +1223,9 @@ static bool iommu_bypass_supported_pSeriesLP(struct pci_dev *pdev, u64 dma_mask)
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}
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if (pdn && PCI_DN(pdn)) {
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dma_offset = enable_ddw(pdev, pdn);
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if (dma_offset != 0) {
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set_dma_offset(&pdev->dev, dma_offset);
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pdev->dev.archdata.dma_offset = enable_ddw(pdev, pdn);
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if (pdev->dev.archdata.dma_offset)
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return true;
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}
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}
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return false;
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@ -386,7 +386,7 @@ static bool dart_device_on_pcie(struct device *dev)
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static void pci_dma_dev_setup_dart(struct pci_dev *dev)
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{
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if (dart_is_u4 && dart_device_on_pcie(&dev->dev))
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set_dma_offset(&dev->dev, DART_U4_BYPASS_BASE);
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dev->dev.archdata.dma_offset = DART_U4_BYPASS_BASE;
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set_iommu_table_base(&dev->dev, &iommu_table_dart);
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}
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@ -139,7 +139,7 @@ static void fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
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*/
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if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) {
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dev->bus_dma_mask = 0;
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set_dma_offset(dev, pci64_dma_offset);
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dev->archdata.dma_offset = pci64_dma_offset;
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}
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}
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@ -43,7 +43,7 @@ static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
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return false;
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}
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set_dma_offset(&dev->dev, PAGE_OFFSET);
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dev->dev.archdata.dma_offset = PAGE_OFFSET;
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/*
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* Allocate a context to do cxl things too. If we eventually do real
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