forked from luck/tmp_suning_uos_patched
Renesas driver updates for v5.5 (take two)
- Initial support for the R-Car M3-W+ (r8a77961) SoC, - A minor fix. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXbxFoQAKCRCKwlD9ZEnx cF74AQD1/ZIzny7w792bZ4Pb5yhI9n/Af5Yv+6FZ2iLJITYbpwEA49dcEoq5qGQq wP3BMNwmqg94Y6pkuIUvkJXuStUlTws= =rY64 -----END PGP SIGNATURE----- Merge tag 'renesas-drivers-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v5.5 (take two) - Initial support for the R-Car M3-W+ (r8a77961) SoC, - A minor fix. * tag 'renesas-drivers-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: rcar-sysc: Add R8A77961 support soc: renesas: rcar-rst: Add R8A77961 support soc: renesas: Identify R-Car M3-W+ soc: renesas: Add ARCH_R8A77961 for new R-Car M3-W+ soc: renesas: Add ARCH_R8A77960 for existing R-Car M3-W soc: renesas: Rename SYSC_R8A7796 to SYSC_R8A77960 soc: renesas: Add missing check for non-zero product register address dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions dt-bindings: power: Add r8a77961 SYSC power domain definitions Link: https://lore.kernel.org/r/20191101155842.31467-6-geert+renesas@glider.be Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
064652ad88
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@ -199,13 +199,24 @@ config ARCH_R8A7795
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help
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This enables support for the Renesas R-Car H3 SoC.
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config ARCH_R8A77960
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bool
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select ARCH_RCAR_GEN3
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select SYSC_R8A77960
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config ARCH_R8A7796
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bool "Renesas R-Car M3-W SoC Platform"
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select ARCH_RCAR_GEN3
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select SYSC_R8A7796
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select ARCH_R8A77960
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help
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This enables support for the Renesas R-Car M3-W SoC.
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config ARCH_R8A77961
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bool "Renesas R-Car M3-W+ SoC Platform"
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select ARCH_RCAR_GEN3
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select SYSC_R8A77961
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help
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This enables support for the Renesas R-Car M3-W+ SoC.
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config ARCH_R8A77965
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bool "Renesas R-Car M3-N SoC Platform"
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select ARCH_RCAR_GEN3
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@ -292,10 +303,14 @@ config SYSC_R8A7795
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bool "R-Car H3 System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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config SYSC_R8A7796
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config SYSC_R8A77960
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bool "R-Car M3-W System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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config SYSC_R8A77961
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bool "R-Car M3-W+ System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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config SYSC_R8A77965
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bool "R-Car M3-N System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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@ -15,7 +15,8 @@ obj-$(CONFIG_SYSC_R8A7791) += r8a7791-sysc.o
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obj-$(CONFIG_SYSC_R8A7792) += r8a7792-sysc.o
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obj-$(CONFIG_SYSC_R8A7794) += r8a7794-sysc.o
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obj-$(CONFIG_SYSC_R8A7795) += r8a7795-sysc.o
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obj-$(CONFIG_SYSC_R8A7796) += r8a7796-sysc.o
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obj-$(CONFIG_SYSC_R8A77960) += r8a7796-sysc.o
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obj-$(CONFIG_SYSC_R8A77961) += r8a7796-sysc.o
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obj-$(CONFIG_SYSC_R8A77965) += r8a77965-sysc.o
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obj-$(CONFIG_SYSC_R8A77970) += r8a77970-sysc.o
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obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o
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@ -1,19 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas R-Car M3-W System Controller
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* Renesas R-Car M3-W/W+ System Controller
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*
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* Copyright (C) 2016 Glider bvba
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* Copyright (C) 2018-2019 Renesas Electronics Corporation
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*/
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#include <linux/bits.h>
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#include <linux/kernel.h>
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#include <linux/sys_soc.h>
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#include <dt-bindings/power/r8a7796-sysc.h>
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#include "rcar-sysc.h"
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static const struct rcar_sysc_area r8a7796_areas[] __initconst = {
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static struct rcar_sysc_area r8a7796_areas[] __initdata = {
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{ "always-on", 0, 0, R8A7796_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
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{ "ca57-scu", 0x1c0, 0, R8A7796_PD_CA57_SCU, R8A7796_PD_ALWAYS_ON,
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PD_SCU },
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@ -41,24 +41,27 @@ static const struct rcar_sysc_area r8a7796_areas[] __initconst = {
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};
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/* Fixups for R-Car M3-W ES1.x revision */
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static const struct soc_device_attribute r8a7796es1[] __initconst = {
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{ .soc_id = "r8a7796", .revision = "ES1.*" },
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{ /* sentinel */ }
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#ifdef CONFIG_SYSC_R8A77960
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const struct rcar_sysc_info r8a77960_sysc_info __initconst = {
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.areas = r8a7796_areas,
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.num_areas = ARRAY_SIZE(r8a7796_areas),
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};
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#endif /* CONFIG_SYSC_R8A77960 */
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static int __init r8a7796_sysc_init(void)
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#ifdef CONFIG_SYSC_R8A77961
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static int __init r8a77961_sysc_init(void)
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{
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if (soc_device_match(r8a7796es1))
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r8a7796_sysc_info.extmask_val = 0;
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rcar_sysc_nullify(r8a7796_areas, ARRAY_SIZE(r8a7796_areas),
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R8A7796_PD_A2VC0);
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return 0;
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}
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struct rcar_sysc_info r8a7796_sysc_info __initdata = {
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.init = r8a7796_sysc_init,
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const struct rcar_sysc_info r8a77961_sysc_info __initconst = {
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.init = r8a77961_sysc_init,
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.areas = r8a7796_areas,
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.num_areas = ARRAY_SIZE(r8a7796_areas),
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.extmask_offs = 0x2f8,
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.extmask_val = BIT(0),
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};
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#endif /* CONFIG_SYSC_R8A77961 */
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@ -59,6 +59,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
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/* R-Car Gen3 */
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{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a77961-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
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@ -313,8 +313,11 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
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#ifdef CONFIG_SYSC_R8A7795
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{ .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
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#endif
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#ifdef CONFIG_SYSC_R8A7796
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{ .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info },
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#ifdef CONFIG_SYSC_R8A77960
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{ .compatible = "renesas,r8a7796-sysc", .data = &r8a77960_sysc_info },
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#endif
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#ifdef CONFIG_SYSC_R8A77961
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{ .compatible = "renesas,r8a77961-sysc", .data = &r8a77961_sysc_info },
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#endif
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#ifdef CONFIG_SYSC_R8A77965
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{ .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },
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@ -61,7 +61,8 @@ extern const struct rcar_sysc_info r8a7791_sysc_info;
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extern const struct rcar_sysc_info r8a7792_sysc_info;
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extern const struct rcar_sysc_info r8a7794_sysc_info;
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extern struct rcar_sysc_info r8a7795_sysc_info;
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extern struct rcar_sysc_info r8a7796_sysc_info;
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extern const struct rcar_sysc_info r8a77960_sysc_info;
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extern const struct rcar_sysc_info r8a77961_sysc_info;
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extern const struct rcar_sysc_info r8a77965_sysc_info;
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extern const struct rcar_sysc_info r8a77970_sysc_info;
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extern const struct rcar_sysc_info r8a77980_sysc_info;
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@ -262,9 +262,12 @@ static const struct of_device_id renesas_socs[] __initconst = {
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#ifdef CONFIG_ARCH_R8A7795
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{ .compatible = "renesas,r8a7795", .data = &soc_rcar_h3 },
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#endif
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#ifdef CONFIG_ARCH_R8A7796
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#ifdef CONFIG_ARCH_R8A77960
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{ .compatible = "renesas,r8a7796", .data = &soc_rcar_m3_w },
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#endif
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#ifdef CONFIG_ARCH_R8A77961
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{ .compatible = "renesas,r8a77961", .data = &soc_rcar_m3_w },
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#endif
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#ifdef CONFIG_ARCH_R8A77965
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{ .compatible = "renesas,r8a77965", .data = &soc_rcar_m3_n },
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#endif
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@ -334,7 +337,7 @@ static int __init renesas_soc_init(void)
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if (np) {
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chipid = of_iomap(np, 0);
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of_node_put(np);
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} else if (soc->id) {
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} else if (soc->id && family->reg) {
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chipid = ioremap(family->reg, 4);
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}
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if (chipid) {
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65
include/dt-bindings/clock/r8a77961-cpg-mssr.h
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65
include/dt-bindings/clock/r8a77961-cpg-mssr.h
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@ -0,0 +1,65 @@
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/* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a77961 CPG Core Clocks */
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#define R8A77961_CLK_Z 0
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#define R8A77961_CLK_Z2 1
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#define R8A77961_CLK_ZR 2
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#define R8A77961_CLK_ZG 3
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#define R8A77961_CLK_ZTR 4
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#define R8A77961_CLK_ZTRD2 5
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#define R8A77961_CLK_ZT 6
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#define R8A77961_CLK_ZX 7
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#define R8A77961_CLK_S0D1 8
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#define R8A77961_CLK_S0D2 9
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#define R8A77961_CLK_S0D3 10
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#define R8A77961_CLK_S0D4 11
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#define R8A77961_CLK_S0D6 12
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#define R8A77961_CLK_S0D8 13
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#define R8A77961_CLK_S0D12 14
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#define R8A77961_CLK_S1D1 15
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#define R8A77961_CLK_S1D2 16
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#define R8A77961_CLK_S1D4 17
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#define R8A77961_CLK_S2D1 18
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#define R8A77961_CLK_S2D2 19
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#define R8A77961_CLK_S2D4 20
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#define R8A77961_CLK_S3D1 21
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#define R8A77961_CLK_S3D2 22
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#define R8A77961_CLK_S3D4 23
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#define R8A77961_CLK_LB 24
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#define R8A77961_CLK_CL 25
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#define R8A77961_CLK_ZB3 26
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#define R8A77961_CLK_ZB3D2 27
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#define R8A77961_CLK_ZB3D4 28
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#define R8A77961_CLK_CR 29
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#define R8A77961_CLK_CRD2 30
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#define R8A77961_CLK_SD0H 31
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#define R8A77961_CLK_SD0 32
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#define R8A77961_CLK_SD1H 33
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#define R8A77961_CLK_SD1 34
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#define R8A77961_CLK_SD2H 35
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#define R8A77961_CLK_SD2 36
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#define R8A77961_CLK_SD3H 37
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#define R8A77961_CLK_SD3 38
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#define R8A77961_CLK_SSP2 39
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#define R8A77961_CLK_SSP1 40
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#define R8A77961_CLK_SSPRS 41
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#define R8A77961_CLK_RPC 42
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#define R8A77961_CLK_RPCD2 43
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#define R8A77961_CLK_MSO 44
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#define R8A77961_CLK_CANFD 45
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#define R8A77961_CLK_HDMI 46
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#define R8A77961_CLK_CSI0 47
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/* CLK_CSIREF was removed */
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#define R8A77961_CLK_CP 49
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#define R8A77961_CLK_CPEX 50
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#define R8A77961_CLK_R 51
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#define R8A77961_CLK_OSC 52
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#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */
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32
include/dt-bindings/power/r8a77961-sysc.h
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32
include/dt-bindings/power/r8a77961-sysc.h
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2019 Glider bvba
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*/
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#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A77961_PD_CA57_CPU0 0
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#define R8A77961_PD_CA57_CPU1 1
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#define R8A77961_PD_CA53_CPU0 5
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#define R8A77961_PD_CA53_CPU1 6
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#define R8A77961_PD_CA53_CPU2 7
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#define R8A77961_PD_CA53_CPU3 8
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#define R8A77961_PD_CA57_SCU 12
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#define R8A77961_PD_CR7 13
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#define R8A77961_PD_A3VC 14
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#define R8A77961_PD_3DG_A 17
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#define R8A77961_PD_3DG_B 18
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#define R8A77961_PD_CA53_SCU 21
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#define R8A77961_PD_A3IR 24
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#define R8A77961_PD_A2VC1 26
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/* Always-on power area */
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#define R8A77961_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */
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