forked from luck/tmp_suning_uos_patched
[SCSI] qla1280: don't use bitfields for hardware access in isp_config
Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Thiemo Seufer <ths@linux-mips.org> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
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5c79d6154f
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0888f4c331
@ -2189,9 +2189,9 @@ qla1280_set_defaults(struct scsi_qla_host *ha)
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/* nv->cntr_flags_1.disable_loading_risc_code = 1; */
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nv->firmware_feature.f.enable_fast_posting = 1;
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nv->firmware_feature.f.disable_synchronous_backoff = 1;
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nv->termination.f.scsi_bus_0_control = 3;
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nv->termination.f.scsi_bus_1_control = 3;
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nv->termination.f.auto_term_support = 1;
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nv->termination.scsi_bus_0_control = 3;
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nv->termination.scsi_bus_1_control = 3;
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nv->termination.auto_term_support = 1;
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/*
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* Set default FIFO magic - What appropriate values would be here
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@ -2201,7 +2201,12 @@ qla1280_set_defaults(struct scsi_qla_host *ha)
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* header file provided by QLogic seems to be bogus or incomplete
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* at best.
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*/
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nv->isp_config.c = ISP_CFG1_BENAB|ISP_CFG1_F128;
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nv->isp_config.burst_enable = 1;
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if (IS_ISP1040(ha))
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nv->isp_config.fifo_threshold |= 3;
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else
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nv->isp_config.fifo_threshold |= 4;
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if (IS_ISP1x160(ha))
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nv->isp_parameter = 0x01; /* fast memory enable */
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@ -2362,31 +2367,40 @@ qla1280_nvram_config(struct scsi_qla_host *ha)
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hwrev = RD_REG_WORD(®->cfg_0) & ISP_CFG0_HWMSK;
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cfg1 = RD_REG_WORD(®->cfg_1);
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cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6);
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cdma_conf = RD_REG_WORD(®->cdma_cfg);
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ddma_conf = RD_REG_WORD(®->ddma_cfg);
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/* Busted fifo, says mjacob. */
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if (hwrev == ISP_CFG0_1040A)
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WRT_REG_WORD(®->cfg_1, cfg1 | ISP_CFG1_F64);
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else
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WRT_REG_WORD(®->cfg_1, cfg1 | ISP_CFG1_F64 | ISP_CFG1_BENAB);
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if (hwrev != ISP_CFG0_1040A)
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cfg1 |= nv->isp_config.fifo_threshold << 4;
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cfg1 |= nv->isp_config.burst_enable << 2;
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WRT_REG_WORD(®->cfg_1, cfg1);
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WRT_REG_WORD(®->cdma_cfg, cdma_conf | CDMA_CONF_BENAB);
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WRT_REG_WORD(®->ddma_cfg, cdma_conf | DDMA_CONF_BENAB);
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} else {
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uint16_t cfg1, term;
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/* Set ISP hardware DMA burst */
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mb[0] = nv->isp_config.c;
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cfg1 = nv->isp_config.fifo_threshold << 4;
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cfg1 |= nv->isp_config.burst_enable << 2;
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/* Enable DMA arbitration on dual channel controllers */
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if (ha->ports > 1)
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mb[0] |= BIT_13;
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WRT_REG_WORD(®->cfg_1, mb[0]);
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cfg1 |= BIT_13;
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WRT_REG_WORD(®->cfg_1, cfg1);
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/* Set SCSI termination. */
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WRT_REG_WORD(®->gpio_enable, (BIT_3 + BIT_2 + BIT_1 + BIT_0));
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mb[0] = nv->termination.c & (BIT_3 + BIT_2 + BIT_1 + BIT_0);
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WRT_REG_WORD(®->gpio_data, mb[0]);
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WRT_REG_WORD(®->gpio_enable,
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BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
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term = nv->termination.scsi_bus_1_control;
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term |= nv->termination.scsi_bus_0_control << 2;
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term |= nv->termination.auto_term_support << 7;
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RD_REG_WORD(®->id_l); /* Flush PCI write */
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WRT_REG_WORD(®->gpio_data, term);
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}
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RD_REG_WORD(®->id_l); /* Flush PCI write */
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/* ISP parameter word. */
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mb[0] = MBC_SET_SYSTEM_PARAMETER;
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@ -375,29 +375,23 @@ struct nvram {
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uint16_t unused_12; /* 12, 13 */
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uint16_t unused_14; /* 14, 15 */
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union {
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uint8_t c;
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struct {
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uint8_t reserved:2;
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uint8_t burst_enable:1;
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uint8_t reserved_1:1;
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uint8_t fifo_threshold:4;
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} f;
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struct {
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uint8_t reserved:2;
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uint8_t burst_enable:1;
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uint8_t reserved_1:1;
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uint8_t fifo_threshold:4;
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} isp_config; /* 16 */
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/* Termination
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* 0 = Disable, 1 = high only, 3 = Auto term
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*/
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union {
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uint8_t c;
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struct {
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uint8_t scsi_bus_1_control:2;
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uint8_t scsi_bus_0_control:2;
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uint8_t unused_0:1;
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uint8_t unused_1:1;
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uint8_t unused_2:1;
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uint8_t auto_term_support:1;
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} f;
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struct {
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uint8_t scsi_bus_1_control:2;
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uint8_t scsi_bus_0_control:2;
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uint8_t unused_0:1;
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uint8_t unused_1:1;
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uint8_t unused_2:1;
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uint8_t auto_term_support:1;
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} termination; /* 17 */
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uint16_t isp_parameter; /* 18, 19 */
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