forked from luck/tmp_suning_uos_patched
ARM: S5PV210: Add MOUT_DMC0 and SCLK_DMC0 clocks
This patch adds MOUT_DMC0 and SCLK_DMC0 for checking the dmc0 clock in CPUFREQ driver. Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Sangbeom Kim <sbkim73@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -261,6 +261,36 @@ static struct clksrc_clk clk_sclk_vpll = {
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
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};
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static struct clk *clkset_moutdmc0src_list[] = {
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[0] = &clk_sclk_a2m.clk,
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[1] = &clk_mout_mpll.clk,
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[2] = NULL,
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[3] = NULL,
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};
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static struct clksrc_sources clkset_moutdmc0src = {
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.sources = clkset_moutdmc0src_list,
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.nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list),
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};
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static struct clksrc_clk clk_mout_dmc0 = {
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.clk = {
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.name = "mout_dmc0",
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.id = -1,
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},
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.sources = &clkset_moutdmc0src,
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.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
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};
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static struct clksrc_clk clk_sclk_dmc0 = {
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.clk = {
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.name = "sclk_dmc0",
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.id = -1,
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.parent = &clk_mout_dmc0.clk,
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},
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.reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
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};
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static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / 2;
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@ -964,6 +994,8 @@ static struct clksrc_clk *sysclks[] = {
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&clk_sclk_dac,
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&clk_sclk_pixel,
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&clk_sclk_hdmi,
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&clk_mout_dmc0,
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&clk_sclk_dmc0,
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};
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void __init_or_cpufreq s5pv210_setup_clocks(void)
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