AcoSail/kernel_optimize_test
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ARM: S3C64XX: Add support for Compact Flash driver on SMDK6410

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Following is added for the CF-ATA driver:
	- Platform data strucure instantiation
	- Platform device enabling code
	- Addition of cfcon clock
	- Platform-specific gpio setup code

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Abhilash Kesavan 2010-06-08 16:55:45 +09:00 committed by Kukjin Kim
parent db90005b5b
commit 0ab0b6d226
8 changed files with 79 additions and 0 deletions
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7
arch/arm/mach-s3c64xx/Kconfig
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@ -57,6 +57,11 @@ config S3C64XX_SETUP_I2C1
help
Common setup code for i2c bus 1.
config S3C64XX_SETUP_IDE
bool
help
Common setup code for S3C64XX IDE.
config S3C64XX_SETUP_FB_24BPP
bool
help
@ -95,6 +100,7 @@ config MACH_SMDK6410
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_I2C1
select SAMSUNG_DEV_IDE
select S3C_DEV_FB
select SAMSUNG_DEV_TS
select S3C_DEV_USB_HOST
@ -103,6 +109,7 @@ config MACH_SMDK6410
select HAVE_S3C2410_WATCHDOG
select S3C64XX_SETUP_SDHCI
select S3C64XX_SETUP_I2C1
select S3C64XX_SETUP_IDE
select S3C64XX_SETUP_FB_24BPP
help
Machine support for the Samsung SMDK6410

1
arch/arm/mach-s3c64xx/Makefile
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@ -35,6 +35,7 @@ obj-$(CONFIG_S3C64XX_DMA) += dma.o
obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o

6
arch/arm/mach-s3c64xx/clock.c
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@ -310,6 +310,12 @@ static struct clk init_clocks[] = {
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_AC97,
}, {
.name = "cfcon",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_IHOST,
}
};

4
arch/arm/mach-s3c64xx/include/mach/map.h
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@ -86,6 +86,9 @@
#define S3C64XX_SZ_GPIO SZ_4K
#define S3C64XX_PA_SDRAM (0x50000000)
#define S3C64XX_PA_CFCON (0x70300000)
#define S3C64XX_PA_VIC0 (0x71200000)
#define S3C64XX_PA_VIC1 (0x71300000)
@ -120,5 +123,6 @@
#define S3C_PA_WDT S3C64XX_PA_WATCHDOG
#define SAMSUNG_PA_ADC S3C64XX_PA_ADC
#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON
#endif /* __ASM_ARCH_6400_MAP_H */

5
arch/arm/mach-s3c64xx/include/mach/regs-clock.h
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@ -34,6 +34,7 @@
#define S3C_SCLK_GATE S3C_CLKREG(0x38)
#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C)
#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120)
/* CLKDIV0 */
#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
@ -154,4 +155,8 @@
#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
#define S3C6400_CLKSRC_MFC (1 << 4)
/* MEM_SYS_CFG */
#define MEM_SYS_CFG_INDEP_CF 0x4000
#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30
#endif /* _PLAT_REGS_CLOCK_H */

8
arch/arm/mach-s3c64xx/mach-smdk6410.c
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@ -56,6 +56,7 @@
#include <mach/regs-gpio.h>
#include <mach/regs-sys.h>
#include <mach/regs-srom.h>
#include <plat/ata.h>
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
@ -242,6 +243,10 @@ static struct platform_device smdk6410_b_pwr_5v = {
};
#endif
static struct s3c_ide_platdata smdk6410_ide_pdata __initdata = {
.setup_gpio = s3c64xx_ide_setup_gpio,
};
static struct map_desc smdk6410_iodesc[] = {};
static struct platform_device *smdk6410_devices[] __initdata = {
@ -265,6 +270,7 @@ static struct platform_device *smdk6410_devices[] __initdata = {
&smdk6410_smsc911x,
&s3c_device_adc,
&s3c_device_cfcon,
&s3c_device_ts,
&s3c_device_wdt,
};
@ -665,6 +671,8 @@ static void __init smdk6410_machine_init(void)
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
s3c_ide_set_platdata(&smdk6410_ide_pdata);
platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
}

2
arch/arm/mach-s3c64xx/s3c6410.c
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@ -37,6 +37,7 @@
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/sdhci.h>
#include <plat/ata-core.h>
#include <plat/iic-core.h>
#include <plat/adc.h>
#include <plat/onenand-core.h>
@ -58,6 +59,7 @@ void __init s3c6410_map_io(void)
s3c_device_nand.name = "s3c6400-nand";
s3c_onenand_setname("s3c6410-onenand");
s3c64xx_onenand1_setname("s3c6410-onenand");
s3c_cfcon_setname("s3c64xx-pata");
}
void __init s3c6410_init_clocks(int xtal)

46
arch/arm/mach-s3c64xx/setup-ide.c Normal file
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@ -0,0 +1,46 @@
/* linux/arch/arm/mach-s3c64xx/setup-ide.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S3C64XX setup information for IDE
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/gpio-cfg.h>
void s3c64xx_ide_setup_gpio(void)
{
u32 reg;
u32 gpio = 0;
reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
/* Independent CF interface, CF chip select configuration */
writel(reg | MEM_SYS_CFG_INDEP_CF |
MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
/* Set XhiDATA[15:0] pins as CF Data[15:0] */
for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++)
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5));
/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++)
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++)
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
}