forked from luck/tmp_suning_uos_patched
Merge branch 'for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
Pull libata updates from Tejun Heo: - libata has always been limiting the maximum queue depth to 31, with one entry set aside mostly for historical reasons. This didn't use to make much difference but Jens found out that modern hard drives can actually perform measurably better with the extra one queue depth. Jens updated libata core so that it can make use of full 32 queue depth - Damien updated command retry logic in error handling so that it doesn't unnecessarily retry when upper layer (SCSI) is gonna handle them - A couple misc changes * 'for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: sata_fsl: use the right type for tag bitshift ahci: enable full queue depth of 32 libata: don't clamp queue depth to ATA_MAX_QUEUE - 1 libata: add extra internal command sata_nv: set host can_queue count appropriately libata: remove assumption that ATA_MAX_QUEUE - 1 is the max libata: use ata_tag_internal() consistently libata: bump ->qc_active to a 64-bit type libata: convert core and drivers to ->hw_tag usage libata: introduce notion of separate hardware tags libata: Fix command retry decision libata: Honor RQF_QUIET flag libata: Make ata_dev_set_mode() less verbose libata: Fix ata_err_string() libata: Fix comment typo in ata_eh_analyze_tf() sata_nv: don't use block layer bounce buffer ata: hpt37x: Convert to use match_string() helper
This commit is contained in:
Linus Torvalds
commit
0bbddb8cbe
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@ -271,7 +271,7 @@ static void acard_ahci_qc_prep(struct ata_queued_cmd *qc)
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* Fill in command table information. First, the header,
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* a SATA Register - Host to Device command FIS.
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*/
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cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
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cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
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ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
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if (is_atapi) {
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@ -294,7 +294,7 @@ static void acard_ahci_qc_prep(struct ata_queued_cmd *qc)
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if (is_atapi)
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opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
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ahci_fill_cmd_slot(pp, qc->tag, opts);
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ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
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}
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static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
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@ -390,7 +390,7 @@ extern struct device_attribute *ahci_sdev_attrs[];
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*/
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#define AHCI_SHT(drv_name) \
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ATA_NCQ_SHT(drv_name), \
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.can_queue = AHCI_MAX_CMDS - 1, \
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.can_queue = AHCI_MAX_CMDS, \
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.sg_tablesize = AHCI_MAX_SG, \
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.dma_boundary = AHCI_DMA_BOUNDARY, \
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.shost_attrs = ahci_shost_attrs, \
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@ -1649,7 +1649,7 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
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* Fill in command table information. First, the header,
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* a SATA Register - Host to Device command FIS.
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*/
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cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
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cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
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ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
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if (is_atapi) {
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@ -1670,7 +1670,7 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
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if (is_atapi)
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opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
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ahci_fill_cmd_slot(pp, qc->tag, opts);
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ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
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}
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static void ahci_fbs_dec_intr(struct ata_port *ap)
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@ -2006,7 +2006,7 @@ unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
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pp->active_link = qc->dev->link;
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if (ata_is_ncq(qc->tf.protocol))
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writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
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writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
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if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
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u32 fbs = readl(port_mmio + PORT_FBS);
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@ -2016,7 +2016,7 @@ unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
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pp->fbs_last_dev = qc->dev->link->pmp;
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}
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writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
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writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
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ahci_sw_activity(qc->dev->link);
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@ -759,7 +759,7 @@ int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
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tf->flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
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tf->flags |= tf_flags;
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if (ata_ncq_enabled(dev) && likely(tag != ATA_TAG_INTERNAL)) {
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if (ata_ncq_enabled(dev) && !ata_tag_internal(tag)) {
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/* yay, NCQ */
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if (!lba_48_ok(block, n_block))
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return -ERANGE;
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@ -1570,8 +1570,9 @@ unsigned ata_exec_internal_sg(struct ata_device *dev,
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u8 command = tf->command;
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int auto_timeout = 0;
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struct ata_queued_cmd *qc;
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unsigned int tag, preempted_tag;
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u32 preempted_sactive, preempted_qc_active;
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unsigned int preempted_tag;
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u32 preempted_sactive;
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u64 preempted_qc_active;
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int preempted_nr_active_links;
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DECLARE_COMPLETION_ONSTACK(wait);
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unsigned long flags;
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@ -1587,20 +1588,10 @@ unsigned ata_exec_internal_sg(struct ata_device *dev,
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}
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/* initialize internal qc */
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qc = __ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
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/* XXX: Tag 0 is used for drivers with legacy EH as some
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* drivers choke if any other tag is given. This breaks
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* ata_tag_internal() test for those drivers. Don't use new
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* EH stuff without converting to it.
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*/
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if (ap->ops->error_handler)
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tag = ATA_TAG_INTERNAL;
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else
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tag = 0;
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qc = __ata_qc_from_tag(ap, tag);
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qc->tag = tag;
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qc->tag = ATA_TAG_INTERNAL;
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qc->hw_tag = 0;
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qc->scsicmd = NULL;
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qc->ap = ap;
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qc->dev = dev;
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@ -2295,7 +2286,7 @@ static int ata_dev_config_ncq(struct ata_device *dev,
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return 0;
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}
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if (ap->flags & ATA_FLAG_NCQ) {
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hdepth = min(ap->scsi_host->can_queue, ATA_MAX_QUEUE - 1);
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hdepth = min(ap->scsi_host->can_queue, ATA_MAX_QUEUE);
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dev->flags |= ATA_DFLAG_NCQ;
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}
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@ -3573,9 +3564,11 @@ static int ata_dev_set_mode(struct ata_device *dev)
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DPRINTK("xfer_shift=%u, xfer_mode=0x%x\n",
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dev->xfer_shift, (int)dev->xfer_mode);
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ata_dev_info(dev, "configured for %s%s\n",
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ata_mode_string(ata_xfer_mode2mask(dev->xfer_mode)),
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dev_err_whine);
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if (!(ehc->i.flags & ATA_EHI_QUIET) ||
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ehc->i.flags & ATA_EHI_DID_HARDRESET)
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ata_dev_info(dev, "configured for %s%s\n",
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ata_mode_string(ata_xfer_mode2mask(dev->xfer_mode)),
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dev_err_whine);
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return 0;
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@ -5133,7 +5126,7 @@ struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev, int tag)
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}
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qc = __ata_qc_from_tag(ap, tag);
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qc->tag = tag;
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qc->tag = qc->hw_tag = tag;
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qc->scsicmd = NULL;
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qc->ap = ap;
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qc->dev = dev;
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@ -5163,7 +5156,7 @@ void ata_qc_free(struct ata_queued_cmd *qc)
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qc->flags = 0;
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tag = qc->tag;
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if (likely(ata_tag_valid(tag))) {
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if (ata_tag_valid(tag)) {
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qc->tag = ATA_TAG_POISON;
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if (ap->flags & ATA_FLAG_SAS_HOST)
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ata_sas_free_tag(tag, ap);
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@ -5185,7 +5178,7 @@ void __ata_qc_complete(struct ata_queued_cmd *qc)
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/* command should be marked inactive atomically with qc completion */
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if (ata_is_ncq(qc->tf.protocol)) {
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link->sactive &= ~(1 << qc->tag);
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link->sactive &= ~(1 << qc->hw_tag);
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if (!link->sactive)
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ap->nr_active_links--;
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} else {
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@ -5203,7 +5196,7 @@ void __ata_qc_complete(struct ata_queued_cmd *qc)
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* is called. (when rc != 0 and atapi request sense is needed)
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*/
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qc->flags &= ~ATA_QCFLAG_ACTIVE;
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ap->qc_active &= ~(1 << qc->tag);
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ap->qc_active &= ~(1ULL << qc->tag);
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/* call completion callback */
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qc->complete_fn(qc);
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@ -5360,29 +5353,29 @@ void ata_qc_complete(struct ata_queued_cmd *qc)
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* RETURNS:
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* Number of completed commands on success, -errno otherwise.
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*/
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int ata_qc_complete_multiple(struct ata_port *ap, u32 qc_active)
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int ata_qc_complete_multiple(struct ata_port *ap, u64 qc_active)
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{
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int nr_done = 0;
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u32 done_mask;
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u64 done_mask;
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done_mask = ap->qc_active ^ qc_active;
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if (unlikely(done_mask & qc_active)) {
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ata_port_err(ap, "illegal qc_active transition (%08x->%08x)\n",
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ata_port_err(ap, "illegal qc_active transition (%08llx->%08llx)\n",
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ap->qc_active, qc_active);
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return -EINVAL;
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}
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while (done_mask) {
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struct ata_queued_cmd *qc;
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unsigned int tag = __ffs(done_mask);
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unsigned int tag = __ffs64(done_mask);
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qc = ata_qc_from_tag(ap, tag);
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if (qc) {
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ata_qc_complete(qc);
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nr_done++;
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}
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done_mask &= ~(1 << tag);
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done_mask &= ~(1ULL << tag);
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}
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return nr_done;
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@ -5413,11 +5406,11 @@ void ata_qc_issue(struct ata_queued_cmd *qc)
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WARN_ON_ONCE(ap->ops->error_handler && ata_tag_valid(link->active_tag));
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if (ata_is_ncq(prot)) {
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WARN_ON_ONCE(link->sactive & (1 << qc->tag));
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WARN_ON_ONCE(link->sactive & (1 << qc->hw_tag));
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if (!link->sactive)
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ap->nr_active_links++;
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link->sactive |= 1 << qc->tag;
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link->sactive |= 1 << qc->hw_tag;
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} else {
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WARN_ON_ONCE(link->sactive);
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@ -5426,7 +5419,7 @@ void ata_qc_issue(struct ata_queued_cmd *qc)
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}
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qc->flags |= ATA_QCFLAG_ACTIVE;
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ap->qc_active |= 1 << qc->tag;
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ap->qc_active |= 1ULL << qc->tag;
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/*
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* We guarantee to LLDs that they will have at least one
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@ -6425,7 +6418,7 @@ void ata_host_init(struct ata_host *host, struct device *dev,
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{
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spin_lock_init(&host->lock);
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mutex_init(&host->eh_mutex);
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host->n_tags = ATA_MAX_QUEUE - 1;
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host->n_tags = ATA_MAX_QUEUE;
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host->dev = dev;
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host->ops = ops;
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}
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@ -6507,7 +6500,7 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht)
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{
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int i, rc;
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host->n_tags = clamp(sht->can_queue, 1, ATA_MAX_QUEUE - 1);
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host->n_tags = clamp(sht->can_queue, 1, ATA_MAX_QUEUE);
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/* host must have been started */
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if (!(host->flags & ATA_HOST_STARTED)) {
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@ -822,9 +822,12 @@ static int ata_eh_nr_in_flight(struct ata_port *ap)
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int nr = 0;
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/* count only non-internal commands */
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for (tag = 0; tag < ATA_MAX_QUEUE - 1; tag++)
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for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
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if (ata_tag_internal(tag))
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continue;
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if (ata_qc_from_tag(ap, tag))
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nr++;
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}
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return nr;
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}
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@ -849,7 +852,7 @@ void ata_eh_fastdrain_timerfn(struct timer_list *t)
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/* No progress during the last interval, tag all
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* in-flight qcs as timed out and freeze the port.
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*/
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for (tag = 0; tag < ATA_MAX_QUEUE - 1; tag++) {
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for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
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struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
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if (qc)
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qc->err_mask |= AC_ERR_TIMEOUT;
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@ -1003,7 +1006,8 @@ static int ata_do_link_abort(struct ata_port *ap, struct ata_link *link)
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/* we're gonna abort all commands, no need for fast drain */
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ata_eh_set_pending(ap, 0);
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for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
|
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/* include internal tag in iteration */
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for (tag = 0; tag <= ATA_MAX_QUEUE; tag++) {
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struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
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if (qc && (!link || qc->dev->link == link)) {
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|
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@ -1432,6 +1436,10 @@ static const char *ata_err_string(unsigned int err_mask)
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return "invalid argument";
|
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if (err_mask & AC_ERR_DEV)
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return "device error";
|
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if (err_mask & AC_ERR_NCQ)
|
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return "NCQ error";
|
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if (err_mask & AC_ERR_NODEV_HINT)
|
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return "Polling detection error";
|
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return "unknown error";
|
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}
|
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|
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|
|
@ -1815,10 +1823,10 @@ static unsigned int ata_eh_analyze_tf(struct ata_queued_cmd *qc,
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if (qc->flags & ATA_QCFLAG_SENSE_VALID) {
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int ret = scsi_check_sense(qc->scsicmd);
|
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/*
|
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* SUCCESS here means that the sense code could
|
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* SUCCESS here means that the sense code could be
|
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* evaluated and should be passed to the upper layers
|
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* for correct evaluation.
|
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* FAILED means the sense code could not interpreted
|
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* FAILED means the sense code could not be interpreted
|
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* and the device would need to be reset.
|
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* NEEDS_RETRY and ADD_TO_MLQUEUE means that the
|
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* command would need to be retried.
|
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|
|
@ -2098,6 +2106,21 @@ static inline int ata_eh_worth_retry(struct ata_queued_cmd *qc)
|
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return qc->err_mask != AC_ERR_DEV; /* retry if not dev error */
|
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}
|
||||
|
||||
/**
|
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* ata_eh_quiet - check if we need to be quiet about a command error
|
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* @qc: qc to check
|
||||
*
|
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* Look at the qc flags anbd its scsi command request flags to determine
|
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* if we need to be quiet about the command failure.
|
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*/
|
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static inline bool ata_eh_quiet(struct ata_queued_cmd *qc)
|
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{
|
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if (qc->scsicmd &&
|
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qc->scsicmd->request->rq_flags & RQF_QUIET)
|
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qc->flags |= ATA_QCFLAG_QUIET;
|
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return qc->flags & ATA_QCFLAG_QUIET;
|
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}
|
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|
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/**
|
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* ata_eh_link_autopsy - analyze error and determine recovery action
|
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* @link: host link to perform autopsy on
|
||||
|
|
@ -2115,7 +2138,7 @@ static void ata_eh_link_autopsy(struct ata_link *link)
|
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struct ata_eh_context *ehc = &link->eh_context;
|
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struct ata_device *dev;
|
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unsigned int all_err_mask = 0, eflags = 0;
|
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int tag;
|
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int tag, nr_failed = 0, nr_quiet = 0;
|
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u32 serror;
|
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int rc;
|
||||
|
||||
|
|
@ -2167,12 +2190,16 @@ static void ata_eh_link_autopsy(struct ata_link *link)
|
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if (qc->err_mask & ~AC_ERR_OTHER)
|
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qc->err_mask &= ~AC_ERR_OTHER;
|
||||
|
||||
/* SENSE_VALID trumps dev/unknown error and revalidation */
|
||||
/*
|
||||
* SENSE_VALID trumps dev/unknown error and revalidation. Upper
|
||||
* layers will determine whether the command is worth retrying
|
||||
* based on the sense data and device class/type. Otherwise,
|
||||
* determine directly if the command is worth retrying using its
|
||||
* error mask and flags.
|
||||
*/
|
||||
if (qc->flags & ATA_QCFLAG_SENSE_VALID)
|
||||
qc->err_mask &= ~(AC_ERR_DEV | AC_ERR_OTHER);
|
||||
|
||||
/* determine whether the command is worth retrying */
|
||||
if (ata_eh_worth_retry(qc))
|
||||
else if (ata_eh_worth_retry(qc))
|
||||
qc->flags |= ATA_QCFLAG_RETRY;
|
||||
|
||||
/* accumulate error info */
|
||||
|
|
@ -2181,8 +2208,17 @@ static void ata_eh_link_autopsy(struct ata_link *link)
|
|||
if (qc->flags & ATA_QCFLAG_IO)
|
||||
eflags |= ATA_EFLAG_IS_IO;
|
||||
trace_ata_eh_link_autopsy_qc(qc);
|
||||
|
||||
/* Count quiet errors */
|
||||
if (ata_eh_quiet(qc))
|
||||
nr_quiet++;
|
||||
nr_failed++;
|
||||
}
|
||||
|
||||
/* If all failed commands requested silence, then be quiet */
|
||||
if (nr_quiet == nr_failed)
|
||||
ehc->i.flags |= ATA_EHI_QUIET;
|
||||
|
||||
/* enforce default EH actions */
|
||||
if (ap->pflags & ATA_PFLAG_FROZEN ||
|
||||
all_err_mask & (AC_ERR_HSM | AC_ERR_TIMEOUT))
|
||||
|
|
|
|||
|
|
@ -872,6 +872,9 @@ static struct ata_queued_cmd *ata_scsi_qc_new(struct ata_device *dev,
|
|||
|
||||
qc->sg = scsi_sglist(cmd);
|
||||
qc->n_elem = scsi_sg_count(cmd);
|
||||
|
||||
if (cmd->request->rq_flags & RQF_QUIET)
|
||||
qc->flags |= ATA_QCFLAG_QUIET;
|
||||
} else {
|
||||
cmd->result = (DID_OK << 16) | (QUEUE_FULL << 1);
|
||||
cmd->scsi_done(cmd);
|
||||
|
|
@ -1316,7 +1319,7 @@ static int ata_scsi_dev_config(struct scsi_device *sdev,
|
|||
int depth;
|
||||
|
||||
depth = min(sdev->host->can_queue, ata_id_queue_depth(dev->id));
|
||||
depth = min(ATA_MAX_QUEUE - 1, depth);
|
||||
depth = min(ATA_MAX_QUEUE, depth);
|
||||
scsi_change_queue_depth(sdev, depth);
|
||||
}
|
||||
|
||||
|
|
@ -1429,7 +1432,7 @@ int __ata_change_queue_depth(struct ata_port *ap, struct scsi_device *sdev,
|
|||
/* limit and apply queue depth */
|
||||
queue_depth = min(queue_depth, sdev->host->can_queue);
|
||||
queue_depth = min(queue_depth, ata_id_queue_depth(dev->id));
|
||||
queue_depth = min(queue_depth, ATA_MAX_QUEUE - 1);
|
||||
queue_depth = min(queue_depth, ATA_MAX_QUEUE);
|
||||
|
||||
if (sdev->queue_depth == queue_depth)
|
||||
return -EINVAL;
|
||||
|
|
@ -1895,7 +1898,7 @@ static unsigned int ata_scsi_rw_xlat(struct ata_queued_cmd *qc)
|
|||
qc->nbytes = n_block * scmd->device->sector_size;
|
||||
|
||||
rc = ata_build_rw_tf(&qc->tf, qc->dev, block, n_block, tf_flags,
|
||||
qc->tag, class);
|
||||
qc->hw_tag, class);
|
||||
|
||||
if (likely(rc == 0))
|
||||
return 0;
|
||||
|
|
@ -3233,7 +3236,7 @@ static unsigned int ata_scsi_pass_thru(struct ata_queued_cmd *qc)
|
|||
|
||||
/* For NCQ commands copy the tag value */
|
||||
if (ata_is_ncq(tf->protocol))
|
||||
tf->nsect = qc->tag << 3;
|
||||
tf->nsect = qc->hw_tag << 3;
|
||||
|
||||
/* enforce correct master/slave bit */
|
||||
tf->device = dev->devno ?
|
||||
|
|
@ -3513,7 +3516,7 @@ static unsigned int ata_scsi_write_same_xlat(struct ata_queued_cmd *qc)
|
|||
tf->protocol = ATA_PROT_NCQ;
|
||||
tf->command = ATA_CMD_FPDMA_SEND;
|
||||
tf->hob_nsect = ATA_SUBCMD_FPDMA_SEND_DSM & 0x1f;
|
||||
tf->nsect = qc->tag << 3;
|
||||
tf->nsect = qc->hw_tag << 3;
|
||||
tf->hob_feature = (size / 512) >> 8;
|
||||
tf->feature = size / 512;
|
||||
|
||||
|
|
@ -3733,7 +3736,7 @@ static unsigned int ata_scsi_zbc_in_xlat(struct ata_queued_cmd *qc)
|
|||
tf->protocol = ATA_PROT_NCQ;
|
||||
tf->command = ATA_CMD_FPDMA_RECV;
|
||||
tf->hob_nsect = ATA_SUBCMD_FPDMA_RECV_ZAC_MGMT_IN & 0x1f;
|
||||
tf->nsect = qc->tag << 3;
|
||||
tf->nsect = qc->hw_tag << 3;
|
||||
tf->feature = sect & 0xff;
|
||||
tf->hob_feature = (sect >> 8) & 0xff;
|
||||
tf->auxiliary = ATA_SUBCMD_ZAC_MGMT_IN_REPORT_ZONES | (options << 8);
|
||||
|
|
@ -3812,7 +3815,7 @@ static unsigned int ata_scsi_zbc_out_xlat(struct ata_queued_cmd *qc)
|
|||
tf->protocol = ATA_PROT_NCQ_NODATA;
|
||||
tf->command = ATA_CMD_NCQ_NON_DATA;
|
||||
tf->feature = ATA_SUBCMD_NCQ_NON_DATA_ZAC_MGMT_OUT;
|
||||
tf->nsect = qc->tag << 3;
|
||||
tf->nsect = qc->hw_tag << 3;
|
||||
tf->auxiliary = sa | ((u16)all << 8);
|
||||
} else {
|
||||
tf->protocol = ATA_PROT_NODATA;
|
||||
|
|
@ -5117,7 +5120,7 @@ int ata_sas_allocate_tag(struct ata_port *ap)
|
|||
tag = tag < max_queue ? tag : 0;
|
||||
|
||||
/* the last tag is reserved for internal command. */
|
||||
if (tag == ATA_TAG_INTERNAL)
|
||||
if (ata_tag_internal(tag))
|
||||
continue;
|
||||
|
||||
if (!test_and_set_bit(tag, &ap->sas_tag_allocated)) {
|
||||
|
|
|
|||
|
|
@ -224,17 +224,14 @@ static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
|
|||
const char * const list[])
|
||||
{
|
||||
unsigned char model_num[ATA_ID_PROD_LEN + 1];
|
||||
int i = 0;
|
||||
int i;
|
||||
|
||||
ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
|
||||
|
||||
while (list[i] != NULL) {
|
||||
if (!strcmp(list[i], model_num)) {
|
||||
pr_warn("%s is not supported for %s\n",
|
||||
modestr, list[i]);
|
||||
return 1;
|
||||
}
|
||||
i++;
|
||||
i = match_string(list, -1, model_num);
|
||||
if (i >= 0) {
|
||||
pr_warn("%s is not supported for %s\n", modestr, list[i]);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -761,7 +761,7 @@ static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
|
|||
if (tag > 0) {
|
||||
dev_info(ap->dev,
|
||||
"%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n",
|
||||
__func__, qc->tag, qc->tf.command,
|
||||
__func__, qc->hw_tag, qc->tf.command,
|
||||
get_dma_dir_descript(qc->dma_dir),
|
||||
get_prot_descript(qc->tf.protocol),
|
||||
sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
|
||||
|
|
@ -789,7 +789,7 @@ static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
|
|||
{
|
||||
u8 status = 0;
|
||||
u32 mask = 0x0;
|
||||
u8 tag = qc->tag;
|
||||
u8 tag = qc->hw_tag;
|
||||
struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
|
||||
struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
|
||||
hsdev->sactive_queued = 0;
|
||||
|
|
@ -997,7 +997,7 @@ static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
|
|||
|
||||
static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
|
||||
{
|
||||
u8 tag = qc->tag;
|
||||
u8 tag = qc->hw_tag;
|
||||
|
||||
if (ata_is_ncq(qc->tf.protocol)) {
|
||||
dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
|
||||
|
|
@ -1059,7 +1059,7 @@ static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
|
|||
|
||||
static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
|
||||
{
|
||||
u8 tag = qc->tag;
|
||||
u8 tag = qc->hw_tag;
|
||||
|
||||
if (ata_is_ncq(qc->tf.protocol)) {
|
||||
dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
|
||||
|
|
@ -1074,17 +1074,17 @@ static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
|
|||
static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
|
||||
{
|
||||
u32 sactive;
|
||||
u8 tag = qc->tag;
|
||||
u8 tag = qc->hw_tag;
|
||||
struct ata_port *ap = qc->ap;
|
||||
struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
|
||||
|
||||
#ifdef DEBUG_NCQ
|
||||
if (qc->tag > 0 || ap->link.sactive > 1)
|
||||
if (qc->hw_tag > 0 || ap->link.sactive > 1)
|
||||
dev_info(ap->dev,
|
||||
"%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
|
||||
__func__, ap->print_id, qc->tf.command,
|
||||
ata_get_cmd_descript(qc->tf.command),
|
||||
qc->tag, get_prot_descript(qc->tf.protocol),
|
||||
qc->hw_tag, get_prot_descript(qc->tf.protocol),
|
||||
ap->link.active_tag, ap->link.sactive);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -519,7 +519,7 @@ static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
|
|||
struct sata_fsl_port_priv *pp = ap->private_data;
|
||||
struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
||||
void __iomem *hcr_base = host_priv->hcr_base;
|
||||
unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
|
||||
unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
|
||||
struct command_desc *cd;
|
||||
u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
|
||||
u32 num_prde = 0;
|
||||
|
|
@ -566,7 +566,7 @@ static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
|
|||
struct ata_port *ap = qc->ap;
|
||||
struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
||||
void __iomem *hcr_base = host_priv->hcr_base;
|
||||
unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
|
||||
unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
|
||||
|
||||
VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
|
||||
ioread32(CQ + hcr_base),
|
||||
|
|
@ -595,7 +595,7 @@ static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
|
|||
struct sata_fsl_port_priv *pp = qc->ap->private_data;
|
||||
struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
|
||||
void __iomem *hcr_base = host_priv->hcr_base;
|
||||
unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
|
||||
unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
|
||||
struct command_desc *cd;
|
||||
|
||||
cd = pp->cmdentry + tag;
|
||||
|
|
@ -1266,7 +1266,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
|
|||
}
|
||||
|
||||
VPRINTK("Status of all queues :\n");
|
||||
VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
|
||||
VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n",
|
||||
done_mask,
|
||||
ioread32(hcr_base + CA),
|
||||
ioread32(hcr_base + CE),
|
||||
|
|
@ -1293,7 +1293,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
|
|||
ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
|
||||
return;
|
||||
|
||||
} else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
|
||||
} else if ((ap->qc_active & (1ULL << ATA_TAG_INTERNAL))) {
|
||||
iowrite32(1, hcr_base + CC);
|
||||
qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
|
||||
|
||||
|
|
|
|||
|
|
@ -1802,7 +1802,7 @@ static void mv_fill_sg(struct ata_queued_cmd *qc)
|
|||
struct mv_sg *mv_sg, *last_sg = NULL;
|
||||
unsigned int si;
|
||||
|
||||
mv_sg = pp->sg_tbl[qc->tag];
|
||||
mv_sg = pp->sg_tbl[qc->hw_tag];
|
||||
for_each_sg(qc->sg, sg, qc->n_elem, si) {
|
||||
dma_addr_t addr = sg_dma_address(sg);
|
||||
u32 sg_len = sg_dma_len(sg);
|
||||
|
|
@ -1903,9 +1903,9 @@ static void mv_bmdma_setup(struct ata_queued_cmd *qc)
|
|||
writel(0, port_mmio + BMDMA_CMD);
|
||||
|
||||
/* load PRD table addr. */
|
||||
writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
|
||||
writel((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16,
|
||||
port_mmio + BMDMA_PRD_HIGH);
|
||||
writelfl(pp->sg_tbl_dma[qc->tag],
|
||||
writelfl(pp->sg_tbl_dma[qc->hw_tag],
|
||||
port_mmio + BMDMA_PRD_LOW);
|
||||
|
||||
/* issue r/w command */
|
||||
|
|
@ -2071,17 +2071,17 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
|
|||
*/
|
||||
if (!(tf->flags & ATA_TFLAG_WRITE))
|
||||
flags |= CRQB_FLAG_READ;
|
||||
WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
|
||||
flags |= qc->tag << CRQB_TAG_SHIFT;
|
||||
WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag);
|
||||
flags |= qc->hw_tag << CRQB_TAG_SHIFT;
|
||||
flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
|
||||
|
||||
/* get current queue index from software */
|
||||
in_index = pp->req_idx;
|
||||
|
||||
pp->crqb[in_index].sg_addr =
|
||||
cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
|
||||
cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff);
|
||||
pp->crqb[in_index].sg_addr_hi =
|
||||
cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
|
||||
cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16);
|
||||
pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
|
||||
|
||||
cw = &pp->crqb[in_index].ata_cmd[0];
|
||||
|
|
@ -2164,17 +2164,17 @@ static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
|
|||
if (!(tf->flags & ATA_TFLAG_WRITE))
|
||||
flags |= CRQB_FLAG_READ;
|
||||
|
||||
WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
|
||||
flags |= qc->tag << CRQB_TAG_SHIFT;
|
||||
flags |= qc->tag << CRQB_HOSTQ_SHIFT;
|
||||
WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag);
|
||||
flags |= qc->hw_tag << CRQB_TAG_SHIFT;
|
||||
flags |= qc->hw_tag << CRQB_HOSTQ_SHIFT;
|
||||
flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
|
||||
|
||||
/* get current queue index from software */
|
||||
in_index = pp->req_idx;
|
||||
|
||||
crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
|
||||
crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
|
||||
crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
|
||||
crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff);
|
||||
crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16);
|
||||
crqb->flags = cpu_to_le32(flags);
|
||||
|
||||
crqb->ata_cmd[0] = cpu_to_le32(
|
||||
|
|
@ -2539,7 +2539,7 @@ static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
|
|||
failed_links = hweight16(new_map);
|
||||
|
||||
ata_port_info(ap,
|
||||
"%s: pmp_map=%04x qc_map=%04x failed_links=%d nr_active_links=%d\n",
|
||||
"%s: pmp_map=%04x qc_map=%04llx failed_links=%d nr_active_links=%d\n",
|
||||
__func__, pp->delayed_eh_pmp_map,
|
||||
ap->qc_active, failed_links,
|
||||
ap->nr_active_links);
|
||||
|
|
|
|||
|
|
@ -400,7 +400,7 @@ static struct scsi_host_template nv_adma_sht = {
|
|||
|
||||
static struct scsi_host_template nv_swncq_sht = {
|
||||
ATA_NCQ_SHT(DRV_NAME),
|
||||
.can_queue = ATA_MAX_QUEUE,
|
||||
.can_queue = ATA_MAX_QUEUE - 1,
|
||||
.sg_tablesize = LIBATA_MAX_PRD,
|
||||
.dma_boundary = ATA_DMA_BOUNDARY,
|
||||
.slave_configure = nv_swncq_slave_config,
|
||||
|
|
@ -740,32 +740,16 @@ static int nv_adma_slave_config(struct scsi_device *sdev)
|
|||
sdev1 = ap->host->ports[1]->link.device[0].sdev;
|
||||
if ((port0->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
|
||||
(port1->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)) {
|
||||
/** We have to set the DMA mask to 32-bit if either port is in
|
||||
ATAPI mode, since they are on the same PCI device which is
|
||||
used for DMA mapping. If we set the mask we also need to set
|
||||
the bounce limit on both ports to ensure that the block
|
||||
layer doesn't feed addresses that cause DMA mapping to
|
||||
choke. If either SCSI device is not allocated yet, it's OK
|
||||
since that port will discover its correct setting when it
|
||||
does get allocated.
|
||||
Note: Setting 32-bit mask should not fail. */
|
||||
if (sdev0)
|
||||
blk_queue_bounce_limit(sdev0->request_queue,
|
||||
ATA_DMA_MASK);
|
||||
if (sdev1)
|
||||
blk_queue_bounce_limit(sdev1->request_queue,
|
||||
ATA_DMA_MASK);
|
||||
|
||||
dma_set_mask(&pdev->dev, ATA_DMA_MASK);
|
||||
/*
|
||||
* We have to set the DMA mask to 32-bit if either port is in
|
||||
* ATAPI mode, since they are on the same PCI device which is
|
||||
* used for DMA mapping. If either SCSI device is not allocated
|
||||
* yet, it's OK since that port will discover its correct
|
||||
* setting when it does get allocated.
|
||||
*/
|
||||
rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
|
||||
} else {
|
||||
/** This shouldn't fail as it was set to this value before */
|
||||
dma_set_mask(&pdev->dev, pp->adma_dma_mask);
|
||||
if (sdev0)
|
||||
blk_queue_bounce_limit(sdev0->request_queue,
|
||||
pp->adma_dma_mask);
|
||||
if (sdev1)
|
||||
blk_queue_bounce_limit(sdev1->request_queue,
|
||||
pp->adma_dma_mask);
|
||||
rc = dma_set_mask(&pdev->dev, pp->adma_dma_mask);
|
||||
}
|
||||
|
||||
blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
|
||||
|
|
@ -1131,12 +1115,11 @@ static int nv_adma_port_start(struct ata_port *ap)
|
|||
|
||||
VPRINTK("ENTER\n");
|
||||
|
||||
/* Ensure DMA mask is set to 32-bit before allocating legacy PRD and
|
||||
pad buffers */
|
||||
rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
|
||||
if (rc)
|
||||
return rc;
|
||||
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
|
||||
/*
|
||||
* Ensure DMA mask is set to 32-bit before allocating legacy PRD and
|
||||
* pad buffers.
|
||||
*/
|
||||
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
|
|
@ -1156,13 +1139,16 @@ static int nv_adma_port_start(struct ata_port *ap)
|
|||
pp->notifier_clear_block = pp->gen_block +
|
||||
NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no);
|
||||
|
||||
/* Now that the legacy PRD and padding buffer are allocated we can
|
||||
safely raise the DMA mask to allocate the CPB/APRD table.
|
||||
These are allowed to fail since we store the value that ends up
|
||||
being used to set as the bounce limit in slave_config later if
|
||||
needed. */
|
||||
dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
|
||||
dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
|
||||
/*
|
||||
* Now that the legacy PRD and padding buffer are allocated we can
|
||||
* try to raise the DMA mask to allocate the CPB/APRD table.
|
||||
*/
|
||||
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
|
||||
if (rc) {
|
||||
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
||||
if (rc)
|
||||
return rc;
|
||||
}
|
||||
pp->adma_dma_mask = *dev->dma_mask;
|
||||
|
||||
mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
|
||||
|
|
@ -1356,11 +1342,11 @@ static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
|
|||
|
||||
for_each_sg(qc->sg, sg, qc->n_elem, si) {
|
||||
aprd = (si < 5) ? &cpb->aprd[si] :
|
||||
&pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (si-5)];
|
||||
&pp->aprd[NV_ADMA_SGTBL_LEN * qc->hw_tag + (si-5)];
|
||||
nv_adma_fill_aprd(qc, sg, si, aprd);
|
||||
}
|
||||
if (si > 5)
|
||||
cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
|
||||
cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->hw_tag)));
|
||||
else
|
||||
cpb->next_aprd = cpu_to_le64(0);
|
||||
}
|
||||
|
|
@ -1385,7 +1371,7 @@ static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
|
|||
static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
|
||||
{
|
||||
struct nv_adma_port_priv *pp = qc->ap->private_data;
|
||||
struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
|
||||
struct nv_adma_cpb *cpb = &pp->cpb[qc->hw_tag];
|
||||
u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
|
||||
NV_CPB_CTL_IEN;
|
||||
|
||||
|
|
@ -1403,7 +1389,7 @@ static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
|
|||
wmb();
|
||||
|
||||
cpb->len = 3;
|
||||
cpb->tag = qc->tag;
|
||||
cpb->tag = qc->hw_tag;
|
||||
cpb->next_cpb_idx = 0;
|
||||
|
||||
/* turn on NCQ flags for NCQ commands */
|
||||
|
|
@ -1466,9 +1452,9 @@ static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
|
|||
pp->last_issue_ncq = curr_ncq;
|
||||
}
|
||||
|
||||
writew(qc->tag, mmio + NV_ADMA_APPEND);
|
||||
writew(qc->hw_tag, mmio + NV_ADMA_APPEND);
|
||||
|
||||
DPRINTK("Issued tag %u\n", qc->tag);
|
||||
DPRINTK("Issued tag %u\n", qc->hw_tag);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1730,8 +1716,8 @@ static void nv_swncq_qc_to_dq(struct ata_port *ap, struct ata_queued_cmd *qc)
|
|||
|
||||
/* queue is full */
|
||||
WARN_ON(dq->tail - dq->head == ATA_MAX_QUEUE);
|
||||
dq->defer_bits |= (1 << qc->tag);
|
||||
dq->tag[dq->tail++ & (ATA_MAX_QUEUE - 1)] = qc->tag;
|
||||
dq->defer_bits |= (1 << qc->hw_tag);
|
||||
dq->tag[dq->tail++ & (ATA_MAX_QUEUE - 1)] = qc->hw_tag;
|
||||
}
|
||||
|
||||
static struct ata_queued_cmd *nv_swncq_qc_from_dq(struct ata_port *ap)
|
||||
|
|
@ -1796,7 +1782,7 @@ static void nv_swncq_ncq_stop(struct ata_port *ap)
|
|||
u32 sactive;
|
||||
u32 done_mask;
|
||||
|
||||
ata_port_err(ap, "EH in SWNCQ mode,QC:qc_active 0x%X sactive 0x%X\n",
|
||||
ata_port_err(ap, "EH in SWNCQ mode,QC:qc_active 0x%llX sactive 0x%X\n",
|
||||
ap->qc_active, ap->link.sactive);
|
||||
ata_port_err(ap,
|
||||
"SWNCQ:qc_active 0x%X defer_bits 0x%X last_issue_tag 0x%x\n "
|
||||
|
|
@ -2010,7 +1996,7 @@ static void nv_swncq_fill_sg(struct ata_queued_cmd *qc)
|
|||
struct ata_bmdma_prd *prd;
|
||||
unsigned int si, idx;
|
||||
|
||||
prd = pp->prd + ATA_MAX_PRD * qc->tag;
|
||||
prd = pp->prd + ATA_MAX_PRD * qc->hw_tag;
|
||||
|
||||
idx = 0;
|
||||
for_each_sg(qc->sg, sg, qc->n_elem, si) {
|
||||
|
|
@ -2048,16 +2034,16 @@ static unsigned int nv_swncq_issue_atacmd(struct ata_port *ap,
|
|||
|
||||
DPRINTK("Enter\n");
|
||||
|
||||
writel((1 << qc->tag), pp->sactive_block);
|
||||
pp->last_issue_tag = qc->tag;
|
||||
pp->dhfis_bits &= ~(1 << qc->tag);
|
||||
pp->dmafis_bits &= ~(1 << qc->tag);
|
||||
pp->qc_active |= (0x1 << qc->tag);
|
||||
writel((1 << qc->hw_tag), pp->sactive_block);
|
||||
pp->last_issue_tag = qc->hw_tag;
|
||||
pp->dhfis_bits &= ~(1 << qc->hw_tag);
|
||||
pp->dmafis_bits &= ~(1 << qc->hw_tag);
|
||||
pp->qc_active |= (0x1 << qc->hw_tag);
|
||||
|
||||
ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
|
||||
ap->ops->sff_exec_command(ap, &qc->tf);
|
||||
|
||||
DPRINTK("Issued tag %u\n", qc->tag);
|
||||
DPRINTK("Issued tag %u\n", qc->hw_tag);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -2207,7 +2193,7 @@ static void nv_swncq_dmafis(struct ata_port *ap)
|
|||
rw = qc->tf.flags & ATA_TFLAG_WRITE;
|
||||
|
||||
/* load PRD table addr. */
|
||||
iowrite32(pp->prd_dma + ATA_PRD_TBL_SZ * qc->tag,
|
||||
iowrite32(pp->prd_dma + ATA_PRD_TBL_SZ * qc->hw_tag,
|
||||
ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
|
||||
|
||||
/* specify data direction, triple-check start bit is clear */
|
||||
|
|
|
|||
|
|
@ -849,7 +849,7 @@ static void sil24_qc_prep(struct ata_queued_cmd *qc)
|
|||
struct sil24_sge *sge;
|
||||
u16 ctrl = 0;
|
||||
|
||||
cb = &pp->cmd_block[sil24_tag(qc->tag)];
|
||||
cb = &pp->cmd_block[sil24_tag(qc->hw_tag)];
|
||||
|
||||
if (!ata_is_atapi(qc->tf.protocol)) {
|
||||
prb = &cb->ata.prb;
|
||||
|
|
@ -891,7 +891,7 @@ static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
|
|||
struct ata_port *ap = qc->ap;
|
||||
struct sil24_port_priv *pp = ap->private_data;
|
||||
void __iomem *port = sil24_port_base(ap);
|
||||
unsigned int tag = sil24_tag(qc->tag);
|
||||
unsigned int tag = sil24_tag(qc->hw_tag);
|
||||
dma_addr_t paddr;
|
||||
void __iomem *activate;
|
||||
|
||||
|
|
@ -911,7 +911,7 @@ static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
|
|||
|
||||
static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
|
||||
{
|
||||
sil24_read_tf(qc->ap, qc->tag, &qc->result_tf);
|
||||
sil24_read_tf(qc->ap, qc->hw_tag, &qc->result_tf);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -125,9 +125,8 @@ enum {
|
|||
LIBATA_MAX_PRD = ATA_MAX_PRD / 2,
|
||||
LIBATA_DUMB_MAX_PRD = ATA_MAX_PRD / 4, /* Worst case */
|
||||
ATA_DEF_QUEUE = 1,
|
||||
/* tag ATA_MAX_QUEUE - 1 is reserved for internal commands */
|
||||
ATA_MAX_QUEUE = 32,
|
||||
ATA_TAG_INTERNAL = ATA_MAX_QUEUE - 1,
|
||||
ATA_TAG_INTERNAL = ATA_MAX_QUEUE,
|
||||
ATA_SHORT_PAUSE = 16,
|
||||
|
||||
ATAPI_MAX_DRAIN = 16 << 10,
|
||||
|
|
@ -637,7 +636,8 @@ struct ata_queued_cmd {
|
|||
u8 cdb[ATAPI_CDB_LEN];
|
||||
|
||||
unsigned long flags; /* ATA_QCFLAG_xxx */
|
||||
unsigned int tag;
|
||||
unsigned int tag; /* libata core tag */
|
||||
unsigned int hw_tag; /* driver tag */
|
||||
unsigned int n_elem;
|
||||
unsigned int orig_n_elem;
|
||||
|
||||
|
|
@ -849,9 +849,9 @@ struct ata_port {
|
|||
unsigned int udma_mask;
|
||||
unsigned int cbl; /* cable type; ATA_CBL_xxx */
|
||||
|
||||
struct ata_queued_cmd qcmd[ATA_MAX_QUEUE];
|
||||
struct ata_queued_cmd qcmd[ATA_MAX_QUEUE + 1];
|
||||
unsigned long sas_tag_allocated; /* for sas tag allocation only */
|
||||
unsigned int qc_active;
|
||||
u64 qc_active;
|
||||
int nr_active_links; /* #links with active qcs */
|
||||
unsigned int sas_last_tag; /* track next tag hw expects */
|
||||
|
||||
|
|
@ -1183,7 +1183,7 @@ extern void ata_id_c_string(const u16 *id, unsigned char *s,
|
|||
extern unsigned int ata_do_dev_read_id(struct ata_device *dev,
|
||||
struct ata_taskfile *tf, u16 *id);
|
||||
extern void ata_qc_complete(struct ata_queued_cmd *qc);
|
||||
extern int ata_qc_complete_multiple(struct ata_port *ap, u32 qc_active);
|
||||
extern int ata_qc_complete_multiple(struct ata_port *ap, u64 qc_active);
|
||||
extern void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd);
|
||||
extern int ata_std_bios_param(struct scsi_device *sdev,
|
||||
struct block_device *bdev,
|
||||
|
|
@ -1483,16 +1483,16 @@ extern void ata_port_pbar_desc(struct ata_port *ap, int bar, ssize_t offset,
|
|||
const char *name);
|
||||
#endif
|
||||
|
||||
static inline unsigned int ata_tag_valid(unsigned int tag)
|
||||
{
|
||||
return (tag < ATA_MAX_QUEUE) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline unsigned int ata_tag_internal(unsigned int tag)
|
||||
static inline bool ata_tag_internal(unsigned int tag)
|
||||
{
|
||||
return tag == ATA_TAG_INTERNAL;
|
||||
}
|
||||
|
||||
static inline bool ata_tag_valid(unsigned int tag)
|
||||
{
|
||||
return tag < ATA_MAX_QUEUE || ata_tag_internal(tag);
|
||||
}
|
||||
|
||||
/*
|
||||
* device helpers
|
||||
*/
|
||||
|
|
@ -1653,7 +1653,7 @@ static inline void ata_qc_set_polling(struct ata_queued_cmd *qc)
|
|||
static inline struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
|
||||
unsigned int tag)
|
||||
{
|
||||
if (likely(ata_tag_valid(tag)))
|
||||
if (ata_tag_valid(tag))
|
||||
return &ap->qcmd[tag];
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user