forked from luck/tmp_suning_uos_patched
arm64: KVM: vgic-v3: Reset LRs at boot time
In order to let the GICv3 code be more lazy in the way it accesses the LRs, it is necessary to start with a clean slate. Let's reset the LRs on each CPU when the vgic is probed (which includes a round trip to EL2...). Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -42,6 +42,7 @@ extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
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extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
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extern u64 __vgic_v3_get_ich_vtr_el2(void);
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extern void __vgic_v3_init_lrs(void);
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extern u32 __kvm_get_mdcr_el2(void);
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@ -321,6 +321,15 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
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}
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}
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void __hyp_text __vgic_v3_init_lrs(void)
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{
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int max_lr_idx = vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2));
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int i;
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for (i = 0; i <= max_lr_idx; i++)
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__gic_v3_set_lr(0, i);
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}
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static u64 __hyp_text __vgic_v3_read_ich_vtr_el2(void)
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{
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return read_gicreg(ICH_VTR_EL2);
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@ -216,6 +216,11 @@ static const struct vgic_ops vgic_v3_ops = {
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static struct vgic_params vgic_v3_params;
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static void vgic_cpu_init_lrs(void *params)
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{
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kvm_call_hyp(__vgic_v3_init_lrs);
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}
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/**
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* vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
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* @node: pointer to the DT node
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@ -284,6 +289,8 @@ int vgic_v3_probe(struct device_node *vgic_node,
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kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
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vcpu_res.start, vgic->maint_irq);
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on_each_cpu(vgic_cpu_init_lrs, vgic, 1);
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*ops = &vgic_v3_ops;
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*params = vgic;
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