forked from luck/tmp_suning_uos_patched
ARM: OMAP: DMTimer: Use posted mode
This patch adds the use of write posting for the timer. Previously, every write could lock the requestor for almost 3x32KHz cycles. This patch only synchronizes before writes and reads instead of after them and it does it on per register basis. Doing it this way there is some chance to hide some of the sync latency. It also removes some needless reads when non-posted mode is there. With out this fix the read/writes take almost 2% CPU load @500MHz just waiting on tick timer registers. Also define new 34xx only registers. Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Richard Woodruff
Tony Lindgren
parent
4621d588e0
commit
0f0d080709
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@ -38,34 +38,113 @@
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#include <asm/arch/irqs.h>
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/* register offsets */
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#define OMAP_TIMER_ID_REG 0x00
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#define OMAP_TIMER_OCP_CFG_REG 0x10
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#define OMAP_TIMER_SYS_STAT_REG 0x14
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#define OMAP_TIMER_STAT_REG 0x18
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#define OMAP_TIMER_INT_EN_REG 0x1c
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#define OMAP_TIMER_WAKEUP_EN_REG 0x20
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#define OMAP_TIMER_CTRL_REG 0x24
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#define OMAP_TIMER_COUNTER_REG 0x28
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#define OMAP_TIMER_LOAD_REG 0x2c
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#define OMAP_TIMER_TRIGGER_REG 0x30
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#define OMAP_TIMER_WRITE_PEND_REG 0x34
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#define OMAP_TIMER_MATCH_REG 0x38
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#define OMAP_TIMER_CAPTURE_REG 0x3c
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#define OMAP_TIMER_IF_CTRL_REG 0x40
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#define _OMAP_TIMER_ID_OFFSET 0x00
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#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
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#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
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#define _OMAP_TIMER_STAT_OFFSET 0x18
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#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
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#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
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#define _OMAP_TIMER_CTRL_OFFSET 0x24
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#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
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#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
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#define OMAP_TIMER_CTRL_PT (1 << 12)
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#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
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#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
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#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
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#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
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#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
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#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
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#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
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#define OMAP_TIMER_CTRL_POSTED (1 << 2)
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#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
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#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
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#define _OMAP_TIMER_COUNTER_OFFSET 0x28
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#define _OMAP_TIMER_LOAD_OFFSET 0x2c
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#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
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#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
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#define WP_NONE 0 /* no write pending bit */
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#define WP_TCLR (1 << 0)
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#define WP_TCRR (1 << 1)
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#define WP_TLDR (1 << 2)
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#define WP_TTGR (1 << 3)
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#define WP_TMAR (1 << 4)
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#define WP_TPIR (1 << 5)
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#define WP_TNIR (1 << 6)
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#define WP_TCVR (1 << 7)
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#define WP_TOCR (1 << 8)
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#define WP_TOWR (1 << 9)
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#define _OMAP_TIMER_MATCH_OFFSET 0x38
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#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
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#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
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#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
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#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
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#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
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#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
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#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
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#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
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/* timer control reg bits */
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#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
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#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
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#define OMAP_TIMER_CTRL_PT (1 << 12)
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#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
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#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
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#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
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#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
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#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
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#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
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#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* how much to shift the prescaler value */
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#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
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#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
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/* register offsets with the write pending bit encoded */
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#define WPSHIFT 16
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#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
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| (WP_TCLR << WPSHIFT))
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#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
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| (WP_TCRR << WPSHIFT))
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#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
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| (WP_TLDR << WPSHIFT))
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#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
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| (WP_TTGR << WPSHIFT))
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#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
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| (WP_TMAR << WPSHIFT))
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#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
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| (WP_TPIR << WPSHIFT))
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#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
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| (WP_TNIR << WPSHIFT))
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#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
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| (WP_TCVR << WPSHIFT))
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#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
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(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
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#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
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(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
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struct omap_dm_timer {
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unsigned long phys_base;
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@ -76,6 +155,7 @@ struct omap_dm_timer {
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void __iomem *io_base;
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unsigned reserved:1;
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unsigned enabled:1;
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unsigned posted:1;
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};
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#ifdef CONFIG_ARCH_OMAP1
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@ -181,16 +261,34 @@ static struct clk **dm_source_clocks;
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static spinlock_t dm_timer_lock;
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static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
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/*
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* Reads timer registers in posted and non-posted mode. The posted mode bit
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* is encoded in reg. Note that in posted mode write pending bit must be
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* checked. Otherwise a read of a non completed write will produce an error.
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*/
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static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
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{
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return readl(timer->io_base + reg);
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if (timer->posted)
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while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
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& (reg >> WPSHIFT))
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cpu_relax();
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return readl(timer->io_base + (reg & 0xff));
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}
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static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
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/*
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* Writes timer registers in posted and non-posted mode. The posted mode bit
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* is encoded in reg. Note that in posted mode the write pending bit must be
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* checked. Otherwise a write on a register which has a pending write will be
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* lost.
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*/
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static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
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u32 value)
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{
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writel(value, timer->io_base + reg);
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while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
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;
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if (timer->posted)
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while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
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& (reg >> WPSHIFT))
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cpu_relax();
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writel(value, timer->io_base + (reg & 0xff));
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}
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static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
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@ -217,17 +315,23 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
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}
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omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
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/* Set to smart-idle mode */
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
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l |= 0x02 << 3;
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l |= 0x02 << 3; /* Set to smart-idle mode */
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l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
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if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
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/* Enable wake-up only for GPT1 on OMAP2 CPUs*/
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/*
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* Enable wake-up only for GPT1 on OMAP2 CPUs.
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* FIXME: All timers should have wake-up enabled and clear
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* PRCM status.
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*/
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if (cpu_class_is_omap2() && (timer == &dm_timers[0]))
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l |= 1 << 2;
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/* Non-posted mode */
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
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}
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omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
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/* Match hardware reset default of posted mode */
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
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OMAP_TIMER_CTRL_POSTED);
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timer->posted = 1;
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}
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static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
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@ -434,6 +538,11 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
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l &= ~OMAP_TIMER_CTRL_AR;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
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/* REVISIT: hw feature, ttgr overtaking tldr? */
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while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)))
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cpu_relax();
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omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
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}
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