forked from luck/tmp_suning_uos_patched
clk: tegra: Allow PLLE training to succeed
Under some circumstances the PLLE needs to be retrained, in which case access to the PMC registers is required. Fix this by passing a pointer to the PMC registers instead of NULL when registering the PLLE clock. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -703,7 +703,7 @@ static void tegra20_pll_init(void)
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clks[pll_a_out0] = clk;
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/* PLLE */
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clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL,
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clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
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0, 100000000, &pll_e_params,
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0, pll_e_freq_table, NULL);
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clk_register_clkdev(clk, "pll_e", NULL);
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