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[TG3]: add 5780 basic jumbo frame support

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Add basic jumbo frames support for 5780. This chip supports jumbo frames
on the standard receive ring without the jumbo ring. The
TG3_FLAG_JUMBO_ENABLE is changed to TG3_FLAG_JUMBO_RING_ENABLE to
indicate using the jumbo ring on 5704 and older chips. A new
TG3_FLG2_JUMBO_CAPABLE flag is added to indicate jumbo frames support
with or without the jumbo ring.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan 2005-07-25 12:30:38 -07:00 committed by David S. Miller
parent 4cf78e4fb6
commit 0f893dc6ec
2 changed files with 20 additions and 13 deletions
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30
drivers/net/tg3.c
View File

@ -90,7 +90,7 @@
/* hardware minimum and maximum for a single frame's data payload */ /* hardware minimum and maximum for a single frame's data payload */
#define TG3_MIN_MTU 60 #define TG3_MIN_MTU 60
#define TG3_MAX_MTU(tp) \ #define TG3_MAX_MTU(tp) \
(!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500) ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
/* These numbers seem to be hard coded in the NIC firmware somehow. /* These numbers seem to be hard coded in the NIC firmware somehow.
* You can't change the ring sizes, but you can change where you place * You can't change the ring sizes, but you can change where you place
@ -914,7 +914,7 @@ static int tg3_phy_reset(struct tg3 *tp)
if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
/* Cannot do read-modify-write on 5401 */ /* Cannot do read-modify-write on 5401 */
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
} else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
u32 phy_reg; u32 phy_reg;
/* Set bit 14 with read-modify-write to preserve other bits */ /* Set bit 14 with read-modify-write to preserve other bits */
@ -926,7 +926,7 @@ static int tg3_phy_reset(struct tg3 *tp)
/* Set phy register 0x10 bit 0 to high fifo elasticity to support /* Set phy register 0x10 bit 0 to high fifo elasticity to support
* jumbo frames transmission. * jumbo frames transmission.
*/ */
if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
u32 phy_reg; u32 phy_reg;
if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg)) if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
@ -3444,9 +3444,9 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
dev->mtu = new_mtu; dev->mtu = new_mtu;
if (new_mtu > ETH_DATA_LEN) if (new_mtu > ETH_DATA_LEN)
tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE; tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
else else
tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE; tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
} }
static int tg3_change_mtu(struct net_device *dev, int new_mtu) static int tg3_change_mtu(struct net_device *dev, int new_mtu)
@ -3588,7 +3588,7 @@ static void tg3_init_rings(struct tg3 *tp)
(i << RXD_OPAQUE_INDEX_SHIFT)); (i << RXD_OPAQUE_INDEX_SHIFT));
} }
if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) { if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
struct tg3_rx_buffer_desc *rxd; struct tg3_rx_buffer_desc *rxd;
@ -3609,7 +3609,7 @@ static void tg3_init_rings(struct tg3 *tp)
break; break;
} }
if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) { if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
for (i = 0; i < tp->rx_jumbo_pending; i++) { for (i = 0; i < tp->rx_jumbo_pending; i++) {
if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO, if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
-1, i) < 0) -1, i) < 0)
@ -5277,7 +5277,7 @@ static int tg3_reset_hw(struct tg3 *tp)
} }
#endif #endif
if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) { if (tp->dev->mtu <= ETH_DATA_LEN) {
tw32(BUFMGR_MB_RDMA_LOW_WATER, tw32(BUFMGR_MB_RDMA_LOW_WATER,
tp->bufmgr_config.mbuf_read_dma_low_water); tp->bufmgr_config.mbuf_read_dma_low_water);
tw32(BUFMGR_MB_MACRX_LOW_WATER, tw32(BUFMGR_MB_MACRX_LOW_WATER,
@ -5352,7 +5352,7 @@ static int tg3_reset_hw(struct tg3 *tp)
/* Setup replenish threshold. */ /* Setup replenish threshold. */
tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) { if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
((u64) tp->rx_jumbo_mapping >> 32)); ((u64) tp->rx_jumbo_mapping >> 32));
tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
@ -5413,7 +5413,7 @@ static int tg3_reset_hw(struct tg3 *tp)
tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
tp->rx_std_ptr); tp->rx_std_ptr);
tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ? tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
tp->rx_jumbo_pending : 0; tp->rx_jumbo_pending : 0;
tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
tp->rx_jumbo_ptr); tp->rx_jumbo_ptr);
@ -8991,6 +8991,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
tp->tg3_flags2 |= TG3_FLG2_HW_TSO; tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0) if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
@ -9117,8 +9122,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
/* Derive initial jumbo mode from MTU assigned in /* Derive initial jumbo mode from MTU assigned in
* ether_setup() via the alloc_etherdev() call * ether_setup() via the alloc_etherdev() call
*/ */
if (tp->dev->mtu > ETH_DATA_LEN) if (tp->dev->mtu > ETH_DATA_LEN &&
tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE; GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780)
tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
/* Determine WakeOnLan speed to use. */ /* Determine WakeOnLan speed to use. */
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||

3
drivers/net/tg3.h
View File

@ -2125,7 +2125,7 @@ struct tg3 {
#define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000 #define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000
#define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000 #define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000
#define TG3_FLAG_SERDES_WOL_CAP 0x00400000 #define TG3_FLAG_SERDES_WOL_CAP 0x00400000
#define TG3_FLAG_JUMBO_ENABLE 0x00800000 #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
#define TG3_FLAG_10_100_ONLY 0x01000000 #define TG3_FLAG_10_100_ONLY 0x01000000
#define TG3_FLAG_PAUSE_AUTONEG 0x02000000 #define TG3_FLAG_PAUSE_AUTONEG 0x02000000
#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
@ -2155,6 +2155,7 @@ struct tg3 {
#define TG3_FLG2_5750_PLUS 0x00080000 #define TG3_FLG2_5750_PLUS 0x00080000
#define TG3_FLG2_PROTECTED_NVRAM 0x00100000 #define TG3_FLG2_PROTECTED_NVRAM 0x00100000
#define TG3_FLG2_USING_MSI 0x00200000 #define TG3_FLG2_USING_MSI 0x00200000
#define TG3_FLG2_JUMBO_CAPABLE 0x00400000
u32 split_mode_max_reqs; u32 split_mode_max_reqs;
#define SPLIT_MODE_5704_MAX_REQ 3 #define SPLIT_MODE_5704_MAX_REQ 3