forked from luck/tmp_suning_uos_patched
gpio: davinci: coding style correction
Make some minor coding style fixes. Use proper multi-line commenting style, and use a macro for register offset. Signed-off-by: Philip Avinash <avinashphilip@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> [nsekhar@ti.com: drop changes which are considered unnecessary churn - line break fixes variable name changes and include file reordering] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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@ -31,6 +31,8 @@ struct davinci_gpio_regs {
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u32 intstat;
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};
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#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
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#define chip2controller(chip) \
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container_of(chip, struct davinci_gpio_controller, chip)
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@ -304,7 +306,8 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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/* NOTE: we assume for now that only irqs in the first gpio_chip
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/*
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* NOTE: we assume for now that only irqs in the first gpio_chip
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* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
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*/
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if (offset < soc_info->gpio_unbanked)
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@ -368,7 +371,8 @@ static int __init davinci_gpio_irq_setup(void)
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}
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clk_prepare_enable(clk);
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/* Arrange gpio_to_irq() support, handling either direct IRQs or
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/*
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* Arrange gpio_to_irq() support, handling either direct IRQs or
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* banked IRQs. Having GPIOs in the first GPIO bank use direct
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* IRQs, while the others use banked IRQs, would need some setup
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* tweaks to recognize hardware which can do that.
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@ -450,10 +454,11 @@ static int __init davinci_gpio_irq_setup(void)
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}
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done:
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/* BINTEN -- per-bank interrupt enable. genirq would also let these
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/*
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* BINTEN -- per-bank interrupt enable. genirq would also let these
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* bits be set/cleared dynamically.
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*/
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__raw_writel(binten, gpio_base + 0x08);
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__raw_writel(binten, gpio_base + BINTEN);
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printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
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