forked from luck/tmp_suning_uos_patched
[IA64-SGI] driver bugfixes and hardware workarounds for CE1.0 asic
Various bugfixes and hardware bug workarounds necessary for the rev 1.0 version of the altix TIO CE asic. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Mark Maule
Tony Luck
parent
3ee68c4af3
commit
13938ca7a1
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@ -15,6 +15,124 @@
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#include <asm/sn/pcidev.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/tioce_provider.h>
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#include <asm/sn/sn2/sn_hwperf.h>
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/*
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* 1/26/2006
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*
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* WAR for SGI PV 944642. For revA TIOCE, need to use the following recipe
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* (taken from the above PV) before and after accessing tioce internal MMR's
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* to avoid tioce lockups.
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*
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* The recipe as taken from the PV:
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*
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* if(mmr address < 0x45000) {
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* if(mmr address == 0 or 0x80)
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* mmr wrt or read address 0xc0
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* else if(mmr address == 0x148 or 0x200)
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* mmr wrt or read address 0x28
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* else
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* mmr wrt or read address 0x158
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*
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* do desired mmr access (rd or wrt)
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*
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* if(mmr address == 0x100)
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* mmr wrt or read address 0x38
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* mmr wrt or read address 0xb050
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* } else
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* do desired mmr access
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*
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* According to hw, we can use reads instead of writes to the above addres
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*
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* Note this WAR can only to be used for accessing internal MMR's in the
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* TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff. This includes the
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* "Local CE Registers and Memories" and "PCI Compatible Config Space" address
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* spaces from table 2-1 of the "CE Programmer's Reference Overview" document.
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*
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* All registers defined in struct tioce will meet that criteria.
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*/
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static void inline
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tioce_mmr_war_pre(struct tioce_kernel *kern, void *mmr_addr)
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{
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u64 mmr_base;
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u64 mmr_offset;
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if (kern->ce_common->ce_rev != TIOCE_REV_A)
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return;
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mmr_base = kern->ce_common->ce_pcibus.bs_base;
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mmr_offset = (u64)mmr_addr - mmr_base;
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if (mmr_offset < 0x45000) {
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u64 mmr_war_offset;
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if (mmr_offset == 0 || mmr_offset == 0x80)
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mmr_war_offset = 0xc0;
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else if (mmr_offset == 0x148 || mmr_offset == 0x200)
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mmr_war_offset = 0x28;
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else
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mmr_war_offset = 0x158;
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readq_relaxed((void *)(mmr_base + mmr_war_offset));
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}
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}
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static void inline
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tioce_mmr_war_post(struct tioce_kernel *kern, void *mmr_addr)
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{
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u64 mmr_base;
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u64 mmr_offset;
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if (kern->ce_common->ce_rev != TIOCE_REV_A)
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return;
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mmr_base = kern->ce_common->ce_pcibus.bs_base;
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mmr_offset = (u64)mmr_addr - mmr_base;
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if (mmr_offset < 0x45000) {
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if (mmr_offset == 0x100)
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readq_relaxed((void *)(mmr_base + 0x38));
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readq_relaxed((void *)(mmr_base + 0xb050));
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}
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}
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/* load mmr contents into a variable */
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#define tioce_mmr_load(kern, mmrp, varp) do {\
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tioce_mmr_war_pre(kern, mmrp); \
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*(varp) = readq_relaxed(mmrp); \
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tioce_mmr_war_post(kern, mmrp); \
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} while (0)
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/* store variable contents into mmr */
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#define tioce_mmr_store(kern, mmrp, varp) do {\
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tioce_mmr_war_pre(kern, mmrp); \
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writeq(*varp, mmrp); \
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tioce_mmr_war_post(kern, mmrp); \
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} while (0)
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/* store immediate value into mmr */
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#define tioce_mmr_storei(kern, mmrp, val) do {\
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tioce_mmr_war_pre(kern, mmrp); \
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writeq(val, mmrp); \
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tioce_mmr_war_post(kern, mmrp); \
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} while (0)
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/* set bits (immediate value) into mmr */
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#define tioce_mmr_seti(kern, mmrp, bits) do {\
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u64 tmp; \
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tioce_mmr_load(kern, mmrp, &tmp); \
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tmp |= (bits); \
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tioce_mmr_store(kern, mmrp, &tmp); \
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} while (0)
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/* clear bits (immediate value) into mmr */
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#define tioce_mmr_clri(kern, mmrp, bits) do { \
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u64 tmp; \
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tioce_mmr_load(kern, mmrp, &tmp); \
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tmp &= ~(bits); \
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tioce_mmr_store(kern, mmrp, &tmp); \
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} while (0)
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/**
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* Bus address ranges for the 5 flavors of TIOCE DMA
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@ -62,9 +180,9 @@
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#define TIOCE_ATE_M40 2
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#define TIOCE_ATE_M40S 3
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#define KB(x) ((x) << 10)
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#define MB(x) ((x) << 20)
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#define GB(x) ((x) << 30)
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#define KB(x) ((u64)(x) << 10)
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#define MB(x) ((u64)(x) << 20)
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#define GB(x) ((u64)(x) << 30)
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/**
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* tioce_dma_d64 - create a DMA mapping using 64-bit direct mode
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@ -151,7 +269,7 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
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int last;
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int entries;
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int nates;
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int pagesize;
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u64 pagesize;
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u64 *ate_shadow;
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u64 *ate_reg;
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u64 addr;
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@ -228,7 +346,7 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
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ate = ATE_MAKE(addr, pagesize);
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ate_shadow[i + j] = ate;
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writeq(ate, &ate_reg[i + j]);
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tioce_mmr_storei(ce_kern, &ate_reg[i + j], ate);
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addr += pagesize;
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}
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@ -272,7 +390,8 @@ tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr)
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u64 tmp;
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ce_kern->ce_port[port].dirmap_shadow = ct_upper;
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writeq(ct_upper, &ce_mmr->ce_ure_dir_map[port]);
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tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port],
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ct_upper);
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tmp = ce_mmr->ce_ure_dir_map[port];
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dma_ok = 1;
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} else
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@ -344,7 +463,8 @@ tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
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if (TIOCE_D32_ADDR(bus_addr)) {
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if (--ce_kern->ce_port[port].dirmap_refcnt == 0) {
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ce_kern->ce_port[port].dirmap_shadow = 0;
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writeq(0, &ce_mmr->ce_ure_dir_map[port]);
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tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port],
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0);
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}
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} else {
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struct tioce_dmamap *map;
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@ -365,7 +485,7 @@ tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
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} else if (--map->refcnt == 0) {
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for (i = 0; i < map->ate_count; i++) {
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map->ate_shadow[i] = 0;
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map->ate_hw[i] = 0;
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tioce_mmr_storei(ce_kern, &map->ate_hw[i], 0);
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}
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list_del(&map->ce_dmamap_list);
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@ -486,7 +606,7 @@ tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count,
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spin_unlock_irqrestore(&ce_kern->ce_lock, flags);
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dma_map_done:
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if (mapaddr & barrier)
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if (mapaddr && barrier)
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mapaddr = tioce_dma_barrier(mapaddr, 1);
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return mapaddr;
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@ -541,17 +661,61 @@ tioce_error_intr_handler(int irq, void *arg, struct pt_regs *pt)
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soft->ce_pcibus.bs_persist_segment,
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soft->ce_pcibus.bs_persist_busnum, 0, 0, 0, 0, 0);
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if (ret_stuff.v0)
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panic("tioce_error_intr_handler: Fatal TIOCE error");
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return IRQ_HANDLED;
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}
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/**
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* tioce_reserve_m32 - reserve M32 ate's for the indicated address range
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* @tioce_kernel: TIOCE context to reserve ate's for
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* @base: starting bus address to reserve
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* @limit: last bus address to reserve
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*
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* If base/limit falls within the range of bus space mapped through the
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* M32 space, reserve the resources corresponding to the range.
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*/
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static void
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tioce_reserve_m32(struct tioce_kernel *ce_kern, u64 base, u64 limit)
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{
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int ate_index, last_ate, ps;
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struct tioce *ce_mmr;
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if (!TIOCE_M32_ADDR(base))
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return;
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ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base;
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ps = ce_kern->ce_ate3240_pagesize;
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ate_index = ATE_PAGE(base, ps);
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last_ate = ate_index + ATE_NPAGES(base, limit-base+1, ps) - 1;
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if (ate_index < 64)
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ate_index = 64;
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while (ate_index <= last_ate) {
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u64 ate;
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ate = ATE_MAKE(0xdeadbeef, ps);
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ce_kern->ce_ate3240_shadow[ate_index] = ate;
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tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_ate3240[ate_index],
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ate);
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ate_index++;
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}
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}
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/**
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* tioce_kern_init - init kernel structures related to a given TIOCE
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* @tioce_common: ptr to a cached tioce_common struct that originated in prom
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*/ static struct tioce_kernel *
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*/
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static struct tioce_kernel *
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tioce_kern_init(struct tioce_common *tioce_common)
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{
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int i;
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int ps;
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int dev;
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u32 tmp;
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unsigned int seg, bus;
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struct tioce *tioce_mmr;
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struct tioce_kernel *tioce_kern;
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@ -572,9 +736,10 @@ tioce_kern_init(struct tioce_common *tioce_common)
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* here to use pci_read_config_xxx() so use the raw_pci_ops vector.
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*/
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raw_pci_ops->read(tioce_common->ce_pcibus.bs_persist_segment,
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tioce_common->ce_pcibus.bs_persist_busnum,
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PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1, &tmp);
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seg = tioce_common->ce_pcibus.bs_persist_segment;
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bus = tioce_common->ce_pcibus.bs_persist_busnum;
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raw_pci_ops->read(seg, bus, PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1,&tmp);
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tioce_kern->ce_port1_secondary = (u8) tmp;
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/*
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@ -583,18 +748,76 @@ tioce_kern_init(struct tioce_common *tioce_common)
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*/
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tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base;
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__sn_clrq_relaxed(&tioce_mmr->ce_ure_page_map, CE_URE_PAGESIZE_MASK);
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__sn_setq_relaxed(&tioce_mmr->ce_ure_page_map, CE_URE_256K_PAGESIZE);
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tioce_kern->ce_ate3240_pagesize = KB(256);
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tioce_mmr_clri(tioce_kern, &tioce_mmr->ce_ure_page_map,
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CE_URE_PAGESIZE_MASK);
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tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_ure_page_map,
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CE_URE_256K_PAGESIZE);
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ps = tioce_kern->ce_ate3240_pagesize = KB(256);
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for (i = 0; i < TIOCE_NUM_M40_ATES; i++) {
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tioce_kern->ce_ate40_shadow[i] = 0;
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writeq(0, &tioce_mmr->ce_ure_ate40[i]);
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tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate40[i], 0);
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}
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for (i = 0; i < TIOCE_NUM_M3240_ATES; i++) {
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tioce_kern->ce_ate3240_shadow[i] = 0;
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writeq(0, &tioce_mmr->ce_ure_ate3240[i]);
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tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate3240[i], 0);
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}
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/*
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* Reserve ATE's corresponding to reserved address ranges. These
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* include:
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*
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* Memory space covered by each PPB mem base/limit register
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* Memory space covered by each PPB prefetch base/limit register
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*
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* These bus ranges are for pio (downstream) traffic only, and so
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* cannot be used for DMA.
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*/
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for (dev = 1; dev <= 2; dev++) {
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u64 base, limit;
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/* mem base/limit */
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raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
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PCI_MEMORY_BASE, 2, &tmp);
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base = (u64)tmp << 16;
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raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
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PCI_MEMORY_LIMIT, 2, &tmp);
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limit = (u64)tmp << 16;
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limit |= 0xfffffUL;
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if (base < limit)
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tioce_reserve_m32(tioce_kern, base, limit);
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/*
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* prefetch mem base/limit. The tioce ppb's have 64-bit
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* decoders, so read the upper portions w/o checking the
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* attributes.
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*/
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raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
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PCI_PREF_MEMORY_BASE, 2, &tmp);
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base = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16;
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raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
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PCI_PREF_BASE_UPPER32, 4, &tmp);
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base |= (u64)tmp << 32;
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raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
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PCI_PREF_MEMORY_LIMIT, 2, &tmp);
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limit = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16;
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limit |= 0xfffffUL;
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raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
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PCI_PREF_LIMIT_UPPER32, 4, &tmp);
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limit |= (u64)tmp << 32;
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if ((base < limit) && TIOCE_M32_ADDR(base))
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tioce_reserve_m32(tioce_kern, base, limit);
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}
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return tioce_kern;
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@ -614,6 +837,7 @@ tioce_force_interrupt(struct sn_irq_info *sn_irq_info)
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{
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struct pcidev_info *pcidev_info;
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struct tioce_common *ce_common;
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struct tioce_kernel *ce_kern;
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struct tioce *ce_mmr;
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u64 force_int_val;
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@ -629,6 +853,29 @@ tioce_force_interrupt(struct sn_irq_info *sn_irq_info)
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ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
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ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base;
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ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
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/*
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* TIOCE Rev A workaround (PV 945826), force an interrupt by writing
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* the TIO_INTx register directly (1/26/2006)
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*/
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if (ce_common->ce_rev == TIOCE_REV_A) {
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u64 int_bit_mask = (1ULL << sn_irq_info->irq_int_bit);
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u64 status;
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tioce_mmr_load(ce_kern, &ce_mmr->ce_adm_int_status, &status);
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if (status & int_bit_mask) {
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u64 force_irq = (1 << 8) | sn_irq_info->irq_irq;
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u64 ctalk = sn_irq_info->irq_xtalkaddr;
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u64 nasid, offset;
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nasid = (ctalk & CTALK_NASID_MASK) >> CTALK_NASID_SHFT;
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offset = (ctalk & CTALK_NODE_OFFSET);
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HUB_S(TIO_IOSPACE_ADDR(nasid, offset), force_irq);
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}
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return;
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}
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/*
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* irq_int_bit is originally set up by prom, and holds the interrupt
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@ -666,7 +913,7 @@ tioce_force_interrupt(struct sn_irq_info *sn_irq_info)
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default:
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return;
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}
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writeq(force_int_val, &ce_mmr->ce_adm_force_int);
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tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_force_int, force_int_val);
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}
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/**
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@ -685,6 +932,7 @@ tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
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{
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struct pcidev_info *pcidev_info;
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struct tioce_common *ce_common;
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struct tioce_kernel *ce_kern;
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struct tioce *ce_mmr;
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int bit;
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u64 vector;
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@ -695,14 +943,15 @@ tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
|
|||
|
||||
ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
|
||||
ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base;
|
||||
ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
|
||||
|
||||
bit = sn_irq_info->irq_int_bit;
|
||||
|
||||
__sn_setq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit));
|
||||
tioce_mmr_seti(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit));
|
||||
vector = (u64)sn_irq_info->irq_irq << INTR_VECTOR_SHFT;
|
||||
vector |= sn_irq_info->irq_xtalkaddr;
|
||||
writeq(vector, &ce_mmr->ce_adm_int_dest[bit]);
|
||||
__sn_clrq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit));
|
||||
tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_int_dest[bit], vector);
|
||||
tioce_mmr_clri(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit));
|
||||
|
||||
tioce_force_interrupt(sn_irq_info);
|
||||
}
|
||||
|
|
@ -721,7 +970,11 @@ tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
|
|||
static void *
|
||||
tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
|
||||
{
|
||||
int my_nasid;
|
||||
cnodeid_t my_cnode, mem_cnode;
|
||||
struct tioce_common *tioce_common;
|
||||
struct tioce_kernel *tioce_kern;
|
||||
struct tioce *tioce_mmr;
|
||||
|
||||
/*
|
||||
* Allocate kernel bus soft and copy from prom.
|
||||
|
|
@ -734,11 +987,23 @@ tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
|
|||
memcpy(tioce_common, prom_bussoft, sizeof(struct tioce_common));
|
||||
tioce_common->ce_pcibus.bs_base |= __IA64_UNCACHED_OFFSET;
|
||||
|
||||
if (tioce_kern_init(tioce_common) == NULL) {
|
||||
tioce_kern = tioce_kern_init(tioce_common);
|
||||
if (tioce_kern == NULL) {
|
||||
kfree(tioce_common);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear out any transient errors before registering the error
|
||||
* interrupt handler.
|
||||
*/
|
||||
|
||||
tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base;
|
||||
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_int_status_alias, ~0ULL);
|
||||
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_error_summary_alias,
|
||||
~0ULL);
|
||||
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_dre_comp_err_addr, ~0ULL);
|
||||
|
||||
if (request_irq(SGI_PCIASIC_ERROR,
|
||||
tioce_error_intr_handler,
|
||||
SA_SHIRQ, "TIOCE error", (void *)tioce_common))
|
||||
|
|
@ -750,6 +1015,21 @@ tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
|
|||
tioce_common->ce_pcibus.bs_persist_segment,
|
||||
tioce_common->ce_pcibus.bs_persist_busnum);
|
||||
|
||||
/*
|
||||
* identify closest nasid for memory allocations
|
||||
*/
|
||||
|
||||
my_nasid = NASID_GET(tioce_common->ce_pcibus.bs_base);
|
||||
my_cnode = nasid_to_cnodeid(my_nasid);
|
||||
|
||||
if (sn_hwperf_get_nearest_node(my_cnode, &mem_cnode, NULL) < 0) {
|
||||
printk(KERN_WARNING "tioce_bus_fixup: failed to find "
|
||||
"closest node with MEM to TIO node %d\n", my_cnode);
|
||||
mem_cnode = (cnodeid_t)-1; /* use any node */
|
||||
}
|
||||
|
||||
controller->node = mem_cnode;
|
||||
|
||||
return tioce_common;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -283,5 +283,13 @@
|
|||
#define REMOTE_HUB_L(n, a) HUB_L(REMOTE_HUB_ADDR((n), (a)))
|
||||
#define REMOTE_HUB_S(n, a, d) HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
|
||||
|
||||
/*
|
||||
* Coretalk address breakdown
|
||||
*/
|
||||
#define CTALK_NASID_SHFT 40
|
||||
#define CTALK_NASID_MASK (0x3FFFULL << CTALK_NASID_SHFT)
|
||||
#define CTALK_CID_SHFT 38
|
||||
#define CTALK_CID_MASK (0x3ULL << CTALK_CID_SHFT)
|
||||
#define CTALK_NODE_OFFSET 0x3FFFFFFFFF
|
||||
|
||||
#endif /* _ASM_IA64_SN_ADDRS_H */
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
|
||||
/* CE ASIC part & mfgr information */
|
||||
#define TIOCE_PART_NUM 0xCE00
|
||||
#define TIOCE_MFGR_NUM 0x36
|
||||
#define TIOCE_SRC_ID 0x01
|
||||
#define TIOCE_REV_A 0x1
|
||||
|
||||
/* CE Virtual PPB Vendor/Device IDs */
|
||||
|
|
@ -20,7 +20,7 @@
|
|||
|
||||
/* CE Host Bridge Vendor/Device IDs */
|
||||
#define CE_HOST_BRIDGE_VENDOR_ID 0x10a9
|
||||
#define CE_HOST_BRIDGE_DEVICE_ID 0x4003
|
||||
#define CE_HOST_BRIDGE_DEVICE_ID 0x4001
|
||||
|
||||
|
||||
#define TIOCE_NUM_M40_ATES 4096
|
||||
|
|
@ -463,6 +463,25 @@ typedef volatile struct tioce {
|
|||
u64 ce_end_of_struct; /* 0x044400 */
|
||||
} tioce_t;
|
||||
|
||||
/* ce_lsiX_gb_cfg1 register bit masks & shifts */
|
||||
#define CE_LSI_GB_CFG1_RXL0S_THS_SHFT 0
|
||||
#define CE_LSI_GB_CFG1_RXL0S_THS_MASK (0xffULL << 0)
|
||||
#define CE_LSI_GB_CFG1_RXL0S_SMP_SHFT 8
|
||||
#define CE_LSI_GB_CFG1_RXL0S_SMP_MASK (0xfULL << 8);
|
||||
#define CE_LSI_GB_CFG1_RXL0S_ADJ_SHFT 12
|
||||
#define CE_LSI_GB_CFG1_RXL0S_ADJ_MASK (0x7ULL << 12)
|
||||
#define CE_LSI_GB_CFG1_RXL0S_FLT_SHFT 15
|
||||
#define CE_LSI_GB_CFG1_RXL0S_FLT_MASK (0x1ULL << 15)
|
||||
#define CE_LSI_GB_CFG1_LPBK_SEL_SHFT 16
|
||||
#define CE_LSI_GB_CFG1_LPBK_SEL_MASK (0x3ULL << 16)
|
||||
#define CE_LSI_GB_CFG1_LPBK_EN_SHFT 18
|
||||
#define CE_LSI_GB_CFG1_LPBK_EN_MASK (0x1ULL << 18)
|
||||
#define CE_LSI_GB_CFG1_RVRS_LB_SHFT 19
|
||||
#define CE_LSI_GB_CFG1_RVRS_LB_MASK (0x1ULL << 19)
|
||||
#define CE_LSI_GB_CFG1_RVRS_CLK_SHFT 20
|
||||
#define CE_LSI_GB_CFG1_RVRS_CLK_MASK (0x3ULL << 20)
|
||||
#define CE_LSI_GB_CFG1_SLF_TS_SHFT 24
|
||||
#define CE_LSI_GB_CFG1_SLF_TS_MASK (0xfULL << 24)
|
||||
|
||||
/* ce_adm_int_mask/ce_adm_int_status register bit defines */
|
||||
#define CE_ADM_INT_CE_ERROR_SHFT 0
|
||||
|
|
@ -592,6 +611,11 @@ typedef volatile struct tioce {
|
|||
#define CE_URE_RD_MRG_ENABLE (0x1ULL << 0)
|
||||
#define CE_URE_WRT_MRG_ENABLE1 (0x1ULL << 4)
|
||||
#define CE_URE_WRT_MRG_ENABLE2 (0x1ULL << 5)
|
||||
#define CE_URE_WRT_MRG_TIMER_SHFT 12
|
||||
#define CE_URE_WRT_MRG_TIMER_MASK (0x7FFULL << CE_URE_WRT_MRG_TIMER_SHFT)
|
||||
#define CE_URE_WRT_MRG_TIMER(x) (((u64)(x) << \
|
||||
CE_URE_WRT_MRG_TIMER_SHFT) & \
|
||||
CE_URE_WRT_MRG_TIMER_MASK)
|
||||
#define CE_URE_RSPQ_BYPASS_DISABLE (0x1ULL << 24)
|
||||
#define CE_URE_UPS_DAT1_PAR_DISABLE (0x1ULL << 32)
|
||||
#define CE_URE_UPS_HDR1_PAR_DISABLE (0x1ULL << 33)
|
||||
|
|
@ -653,8 +677,12 @@ typedef volatile struct tioce {
|
|||
#define CE_URE_SI (0x1ULL << 0)
|
||||
#define CE_URE_ELAL_SHFT 4
|
||||
#define CE_URE_ELAL_MASK (0x7ULL << CE_URE_ELAL_SHFT)
|
||||
#define CE_URE_ELAL_SET(n) (((u64)(n) << CE_URE_ELAL_SHFT) & \
|
||||
CE_URE_ELAL_MASK)
|
||||
#define CE_URE_ELAL1_SHFT 8
|
||||
#define CE_URE_ELAL1_MASK (0x7ULL << CE_URE_ELAL1_SHFT)
|
||||
#define CE_URE_ELAL1_SET(n) (((u64)(n) << CE_URE_ELAL1_SHFT) & \
|
||||
CE_URE_ELAL1_MASK)
|
||||
#define CE_URE_SCC (0x1ULL << 12)
|
||||
#define CE_URE_PN1_SHFT 16
|
||||
#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT)
|
||||
|
|
@ -675,8 +703,12 @@ typedef volatile struct tioce {
|
|||
#define CE_URE_HPC (0x1ULL << 6)
|
||||
#define CE_URE_SPLV_SHFT 7
|
||||
#define CE_URE_SPLV_MASK (0xFFULL << CE_URE_SPLV_SHFT)
|
||||
#define CE_URE_SPLV_SET(n) (((u64)(n) << CE_URE_SPLV_SHFT) & \
|
||||
CE_URE_SPLV_MASK)
|
||||
#define CE_URE_SPLS_SHFT 15
|
||||
#define CE_URE_SPLS_MASK (0x3ULL << CE_URE_SPLS_SHFT)
|
||||
#define CE_URE_SPLS_SET(n) (((u64)(n) << CE_URE_SPLS_SHFT) & \
|
||||
CE_URE_SPLS_MASK)
|
||||
#define CE_URE_PSN1_SHFT 19
|
||||
#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT)
|
||||
#define CE_URE_PSN2_SHFT 32
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user