riscv: move sifive_l2_cache.h to include/soc

The commit 9209fb5189 ("riscv: move sifive_l2_cache.c to drivers/soc")
moves the sifive L2 cache driver to driver/soc. It did not move the
header file along with the driver. Therefore this patch moves the header
file to driver/soc

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
[paul.walmsley@sifive.com: updated to fix the include guard]
Fixes: 9209fb5189 ("riscv: move sifive_l2_cache.c to drivers/soc")
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
This commit is contained in:
Yash Shah 2020-01-07 22:09:06 -08:00 committed by Paul Walmsley
parent c79f46a282
commit 13cf4cf030
3 changed files with 5 additions and 5 deletions

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@ -10,7 +10,7 @@
#include <linux/edac.h> #include <linux/edac.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include "edac_module.h" #include "edac_module.h"
#include <asm/sifive_l2_cache.h> #include <soc/sifive/sifive_l2_cache.h>
#define DRVNAME "sifive_edac" #define DRVNAME "sifive_edac"

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@ -9,7 +9,7 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/of_irq.h> #include <linux/of_irq.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <asm/sifive_l2_cache.h> #include <soc/sifive/sifive_l2_cache.h>
#define SIFIVE_L2_DIRECCFIX_LOW 0x100 #define SIFIVE_L2_DIRECCFIX_LOW 0x100
#define SIFIVE_L2_DIRECCFIX_HIGH 0x104 #define SIFIVE_L2_DIRECCFIX_HIGH 0x104

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@ -4,8 +4,8 @@
* *
*/ */
#ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H #ifndef __SOC_SIFIVE_L2_CACHE_H
#define _ASM_RISCV_SIFIVE_L2_CACHE_H #define __SOC_SIFIVE_L2_CACHE_H
extern int register_sifive_l2_error_notifier(struct notifier_block *nb); extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
@ -13,4 +13,4 @@ extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
#define SIFIVE_L2_ERR_TYPE_CE 0 #define SIFIVE_L2_ERR_TYPE_CE 0
#define SIFIVE_L2_ERR_TYPE_UE 1 #define SIFIVE_L2_ERR_TYPE_UE 1
#endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */ #endif /* __SOC_SIFIVE_L2_CACHE_H */