forked from luck/tmp_suning_uos_patched
i2c: Adding support for Intel iSMT SMBus 2.0 host controller
The iSMT (Intel SMBus Message Transport) supports multi-master I2C/SMBus, as well as IPMI. It's operation is DMA-based and utilizes descriptors to initiate transactions on the bus. The iSMT hardware can act as both a master and a target, although this driver only supports being a master. Signed-off-by: Neil Horman <nhorman@tuxdriver.com> Signed-off-by: Bill Brown <bill.e.brown@intel.com> Tested-by: Seth Heasley <seth.heasley@intel.com> Reviewed-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
This commit is contained in:
Neil Horman
Wolfram Sang
parent
e789029761
commit
13f35ac14c
36
Documentation/i2c/busses/i2c-ismt
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36
Documentation/i2c/busses/i2c-ismt
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@ -0,0 +1,36 @@
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Kernel driver i2c-ismt
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Supported adapters:
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* Intel S12xx series SOCs
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Authors:
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Bill Brown <bill.e.brown@intel.com>
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Module Parameters
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-----------------
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* bus_speed (unsigned int)
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Allows changing of the bus speed. Normally, the bus speed is set by the BIOS
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and never needs to be changed. However, some SMBus analyzers are too slow for
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monitoring the bus during debug, thus the need for this module parameter.
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Specify the bus speed in kHz.
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Available bus frequency settings:
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0 no change
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80 kHz
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100 kHz
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400 kHz
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1000 kHz
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Description
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-----------
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The S12xx series of SOCs have a pair of integrated SMBus 2.0 controllers
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targeted primarily at the microserver and storage markets.
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The S12xx series contain a pair of PCI functions. An output of lspci will show
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something similar to the following:
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00:13.0 System peripheral: Intel Corporation Centerton SMBus 2.0 Controller 0
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00:13.1 System peripheral: Intel Corporation Centerton SMBus 2.0 Controller 1
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@ -122,6 +122,16 @@ config I2C_ISCH
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This driver can also be built as a module. If so, the module
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This driver can also be built as a module. If so, the module
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will be called i2c-isch.
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will be called i2c-isch.
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config I2C_ISMT
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tristate "Intel iSMT SMBus Controller"
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depends on PCI && X86
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help
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If you say yes to this option, support will be included for the Intel
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iSMT SMBus host controller interface.
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This driver can also be built as a module. If so, the module will be
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called i2c-ismt.
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config I2C_PIIX4
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config I2C_PIIX4
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tristate "Intel PIIX4 and compatible (ATI/AMD/Serverworks/Broadcom/SMSC)"
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tristate "Intel PIIX4 and compatible (ATI/AMD/Serverworks/Broadcom/SMSC)"
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depends on PCI
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depends on PCI
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@ -14,6 +14,7 @@ obj-$(CONFIG_I2C_AMD756_S4882) += i2c-amd756-s4882.o
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obj-$(CONFIG_I2C_AMD8111) += i2c-amd8111.o
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obj-$(CONFIG_I2C_AMD8111) += i2c-amd8111.o
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obj-$(CONFIG_I2C_I801) += i2c-i801.o
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obj-$(CONFIG_I2C_I801) += i2c-i801.o
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obj-$(CONFIG_I2C_ISCH) += i2c-isch.o
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obj-$(CONFIG_I2C_ISCH) += i2c-isch.o
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obj-$(CONFIG_I2C_ISMT) += i2c-ismt.o
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obj-$(CONFIG_I2C_NFORCE2) += i2c-nforce2.o
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obj-$(CONFIG_I2C_NFORCE2) += i2c-nforce2.o
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obj-$(CONFIG_I2C_NFORCE2_S4985) += i2c-nforce2-s4985.o
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obj-$(CONFIG_I2C_NFORCE2_S4985) += i2c-nforce2-s4985.o
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obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o
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obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o
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963
drivers/i2c/busses/i2c-ismt.c
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963
drivers/i2c/busses/i2c-ismt.c
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@ -0,0 +1,963 @@
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2012 Intel Corporation. All rights reserved.
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*
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* GPL LICENSE SUMMARY
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* BSD LICENSE
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
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* S12xx Product Family.
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*
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* Features supported by this driver:
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* Hardware PEC yes
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* Block buffer yes
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* Block process call transaction no
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* Slave mode no
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/completion.h>
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#include <linux/dma-mapping.h>
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#include <linux/i2c.h>
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#include <linux/acpi.h>
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#include <linux/interrupt.h>
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#include <asm-generic/io-64-nonatomic-lo-hi.h>
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/* PCI Address Constants */
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#define SMBBAR 0
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/* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
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#define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
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#define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
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#define ISMT_DESC_ENTRIES 32 /* number of descriptor entries */
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#define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */
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/* Hardware Descriptor Constants - Control Field */
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#define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
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#define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */
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#define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */
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#define ISMT_DESC_PEC 0x10 /* Packet Error Code */
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#define ISMT_DESC_I2C 0x20 /* I2C Enable */
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#define ISMT_DESC_INT 0x40 /* Interrupt */
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#define ISMT_DESC_SOE 0x80 /* Stop On Error */
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/* Hardware Descriptor Constants - Status Field */
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#define ISMT_DESC_SCS 0x01 /* Success */
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#define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */
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#define ISMT_DESC_NAK 0x08 /* NAK Received */
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#define ISMT_DESC_CRC 0x10 /* CRC Error */
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#define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */
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#define ISMT_DESC_COL 0x40 /* Collisions */
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#define ISMT_DESC_LPR 0x80 /* Large Packet Received */
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/* Macros */
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#define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
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/* iSMT General Register address offsets (SMBBAR + <addr>) */
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#define ISMT_GR_GCTRL 0x000 /* General Control */
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#define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */
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#define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */
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#define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */
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#define ISMT_GR_ERRSTS 0x018 /* Error Status */
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#define ISMT_GR_ERRINFO 0x01c /* Error Information */
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/* iSMT Master Registers */
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#define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
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#define ISMT_MSTR_MCTRL 0x108 /* Master Control */
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#define ISMT_MSTR_MSTS 0x10c /* Master Status */
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#define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */
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#define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */
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/* iSMT Miscellaneous Registers */
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#define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */
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/* General Control Register (GCTRL) bit definitions */
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#define ISMT_GCTRL_TRST 0x04 /* Target Reset */
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#define ISMT_GCTRL_KILL 0x08 /* Kill */
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#define ISMT_GCTRL_SRST 0x40 /* Soft Reset */
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/* Master Control Register (MCTRL) bit definitions */
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#define ISMT_MCTRL_SS 0x01 /* Start/Stop */
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#define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */
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#define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */
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/* Master Status Register (MSTS) bit definitions */
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#define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */
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#define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */
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#define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */
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#define ISMT_MSTS_IP 0x01 /* In Progress */
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/* Master Descriptor Size (MDS) bit definitions */
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#define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */
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/* SMBus PHY Global Timing Register (SPGT) bit definitions */
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#define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */
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#define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
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#define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
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#define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */
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#define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */
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/* MSI Control Register (MSICTL) bit definitions */
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#define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
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/* iSMT Hardware Descriptor */
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struct ismt_desc {
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u8 tgtaddr_rw; /* target address & r/w bit */
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u8 wr_len_cmd; /* write length in bytes or a command */
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u8 rd_len; /* read length */
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u8 control; /* control bits */
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u8 status; /* status bits */
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u8 retry; /* collision retry and retry count */
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u8 rxbytes; /* received bytes */
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u8 txbytes; /* transmitted bytes */
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u32 dptr_low; /* lower 32 bit of the data pointer */
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u32 dptr_high; /* upper 32 bit of the data pointer */
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} __packed;
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struct ismt_priv {
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struct i2c_adapter adapter;
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void *smba; /* PCI BAR */
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struct pci_dev *pci_dev;
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struct ismt_desc *hw; /* descriptor virt base addr */
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dma_addr_t io_rng_dma; /* descriptor HW base addr */
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u8 head; /* ring buffer head pointer */
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struct completion cmp; /* interrupt completion */
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u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* temp R/W data buffer */
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bool using_msi; /* type of interrupt flag */
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};
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/**
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* ismt_ids - PCI device IDs supported by this driver
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*/
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static const DEFINE_PCI_DEVICE_TABLE(ismt_ids) = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, ismt_ids);
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/* Bus speed control bits for slow debuggers - refer to the docs for usage */
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static unsigned int bus_speed;
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module_param(bus_speed, uint, S_IRUGO);
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MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
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/**
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* __ismt_desc_dump() - dump the contents of a specific descriptor
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*/
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static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
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{
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dev_dbg(dev, "Descriptor struct: %p\n", desc);
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dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
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dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
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dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len);
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dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control);
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dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status);
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dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry);
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dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes);
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dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes);
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dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low);
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dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
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}
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/**
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* ismt_desc_dump() - dump the contents of a descriptor for debug purposes
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* @priv: iSMT private data
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*/
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static void ismt_desc_dump(struct ismt_priv *priv)
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{
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struct device *dev = &priv->pci_dev->dev;
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struct ismt_desc *desc = &priv->hw[priv->head];
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dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head);
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__ismt_desc_dump(dev, desc);
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}
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/**
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* ismt_gen_reg_dump() - dump the iSMT General Registers
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* @priv: iSMT private data
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*/
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static void ismt_gen_reg_dump(struct ismt_priv *priv)
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{
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struct device *dev = &priv->pci_dev->dev;
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dev_dbg(dev, "Dump of the iSMT General Registers\n");
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dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n",
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priv->smba + ISMT_GR_GCTRL,
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readl(priv->smba + ISMT_GR_GCTRL));
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dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n",
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priv->smba + ISMT_GR_SMTICL,
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(long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
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dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n",
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priv->smba + ISMT_GR_ERRINTMSK,
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readl(priv->smba + ISMT_GR_ERRINTMSK));
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dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n",
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priv->smba + ISMT_GR_ERRAERMSK,
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readl(priv->smba + ISMT_GR_ERRAERMSK));
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||||||
|
dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n",
|
||||||
|
priv->smba + ISMT_GR_ERRSTS,
|
||||||
|
readl(priv->smba + ISMT_GR_ERRSTS));
|
||||||
|
dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n",
|
||||||
|
priv->smba + ISMT_GR_ERRINFO,
|
||||||
|
readl(priv->smba + ISMT_GR_ERRINFO));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_mstr_reg_dump() - dump the iSMT Master Registers
|
||||||
|
* @priv: iSMT private data
|
||||||
|
*/
|
||||||
|
static void ismt_mstr_reg_dump(struct ismt_priv *priv)
|
||||||
|
{
|
||||||
|
struct device *dev = &priv->pci_dev->dev;
|
||||||
|
|
||||||
|
dev_dbg(dev, "Dump of the iSMT Master Registers\n");
|
||||||
|
dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n",
|
||||||
|
priv->smba + ISMT_MSTR_MDBA,
|
||||||
|
(long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
|
||||||
|
dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n",
|
||||||
|
priv->smba + ISMT_MSTR_MCTRL,
|
||||||
|
readl(priv->smba + ISMT_MSTR_MCTRL));
|
||||||
|
dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n",
|
||||||
|
priv->smba + ISMT_MSTR_MSTS,
|
||||||
|
readl(priv->smba + ISMT_MSTR_MSTS));
|
||||||
|
dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n",
|
||||||
|
priv->smba + ISMT_MSTR_MDS,
|
||||||
|
readl(priv->smba + ISMT_MSTR_MDS));
|
||||||
|
dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n",
|
||||||
|
priv->smba + ISMT_MSTR_RPOLICY,
|
||||||
|
readl(priv->smba + ISMT_MSTR_RPOLICY));
|
||||||
|
dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n",
|
||||||
|
priv->smba + ISMT_SPGT,
|
||||||
|
readl(priv->smba + ISMT_SPGT));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_submit_desc() - add a descriptor to the ring
|
||||||
|
* @priv: iSMT private data
|
||||||
|
*/
|
||||||
|
static void ismt_submit_desc(struct ismt_priv *priv)
|
||||||
|
{
|
||||||
|
uint fmhp;
|
||||||
|
uint val;
|
||||||
|
|
||||||
|
ismt_desc_dump(priv);
|
||||||
|
ismt_gen_reg_dump(priv);
|
||||||
|
ismt_mstr_reg_dump(priv);
|
||||||
|
|
||||||
|
/* Set the FMHP (Firmware Master Head Pointer)*/
|
||||||
|
fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
|
||||||
|
val = readl(priv->smba + ISMT_MSTR_MCTRL);
|
||||||
|
writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
|
||||||
|
priv->smba + ISMT_MSTR_MCTRL);
|
||||||
|
|
||||||
|
/* Set the start bit */
|
||||||
|
val = readl(priv->smba + ISMT_MSTR_MCTRL);
|
||||||
|
writel(val | ISMT_MCTRL_SS,
|
||||||
|
priv->smba + ISMT_MSTR_MCTRL);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_process_desc() - handle the completion of the descriptor
|
||||||
|
* @desc: the iSMT hardware descriptor
|
||||||
|
* @data: data buffer from the upper layer
|
||||||
|
* @priv: ismt_priv struct holding our dma buffer
|
||||||
|
* @size: SMBus transaction type
|
||||||
|
* @read_write: flag to indicate if this is a read or write
|
||||||
|
*/
|
||||||
|
static int ismt_process_desc(const struct ismt_desc *desc,
|
||||||
|
union i2c_smbus_data *data,
|
||||||
|
struct ismt_priv *priv, int size,
|
||||||
|
char read_write)
|
||||||
|
{
|
||||||
|
u8 *dma_buffer = priv->dma_buffer;
|
||||||
|
|
||||||
|
dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
|
||||||
|
__ismt_desc_dump(&priv->pci_dev->dev, desc);
|
||||||
|
|
||||||
|
if (desc->status & ISMT_DESC_SCS) {
|
||||||
|
if (read_write == I2C_SMBUS_WRITE &&
|
||||||
|
size != I2C_SMBUS_PROC_CALL)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
switch (size) {
|
||||||
|
case I2C_SMBUS_BYTE:
|
||||||
|
case I2C_SMBUS_BYTE_DATA:
|
||||||
|
data->byte = dma_buffer[0];
|
||||||
|
break;
|
||||||
|
case I2C_SMBUS_WORD_DATA:
|
||||||
|
case I2C_SMBUS_PROC_CALL:
|
||||||
|
data->word = dma_buffer[0] | (dma_buffer[1] << 8);
|
||||||
|
break;
|
||||||
|
case I2C_SMBUS_BLOCK_DATA:
|
||||||
|
memcpy(&data->block[1], dma_buffer, desc->rxbytes);
|
||||||
|
data->block[0] = desc->rxbytes;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (likely(desc->status & ISMT_DESC_NAK))
|
||||||
|
return -ENXIO;
|
||||||
|
|
||||||
|
if (desc->status & ISMT_DESC_CRC)
|
||||||
|
return -EBADMSG;
|
||||||
|
|
||||||
|
if (desc->status & ISMT_DESC_COL)
|
||||||
|
return -EAGAIN;
|
||||||
|
|
||||||
|
if (desc->status & ISMT_DESC_LPR)
|
||||||
|
return -EPROTO;
|
||||||
|
|
||||||
|
if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_access() - process an SMBus command
|
||||||
|
* @adap: the i2c host adapter
|
||||||
|
* @addr: address of the i2c/SMBus target
|
||||||
|
* @flags: command options
|
||||||
|
* @read_write: read from or write to device
|
||||||
|
* @command: the i2c/SMBus command to issue
|
||||||
|
* @size: SMBus transaction type
|
||||||
|
* @data: read/write data buffer
|
||||||
|
*/
|
||||||
|
static int ismt_access(struct i2c_adapter *adap, u16 addr,
|
||||||
|
unsigned short flags, char read_write, u8 command,
|
||||||
|
int size, union i2c_smbus_data *data)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
dma_addr_t dma_addr = 0; /* address of the data buffer */
|
||||||
|
u8 dma_size = 0;
|
||||||
|
enum dma_data_direction dma_direction = 0;
|
||||||
|
struct ismt_desc *desc;
|
||||||
|
struct ismt_priv *priv = i2c_get_adapdata(adap);
|
||||||
|
struct device *dev = &priv->pci_dev->dev;
|
||||||
|
|
||||||
|
desc = &priv->hw[priv->head];
|
||||||
|
|
||||||
|
/* Initialize the descriptor */
|
||||||
|
memset(desc, 0, sizeof(struct ismt_desc));
|
||||||
|
desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
|
||||||
|
|
||||||
|
/* Initialize common control bits */
|
||||||
|
if (likely(priv->using_msi))
|
||||||
|
desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
|
||||||
|
else
|
||||||
|
desc->control = ISMT_DESC_FAIR;
|
||||||
|
|
||||||
|
if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
|
||||||
|
&& (size != I2C_SMBUS_I2C_BLOCK_DATA))
|
||||||
|
desc->control |= ISMT_DESC_PEC;
|
||||||
|
|
||||||
|
switch (size) {
|
||||||
|
case I2C_SMBUS_QUICK:
|
||||||
|
dev_dbg(dev, "I2C_SMBUS_QUICK\n");
|
||||||
|
break;
|
||||||
|
|
||||||
|
case I2C_SMBUS_BYTE:
|
||||||
|
if (read_write == I2C_SMBUS_WRITE) {
|
||||||
|
/*
|
||||||
|
* Send Byte
|
||||||
|
* The command field contains the write data
|
||||||
|
*/
|
||||||
|
dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n");
|
||||||
|
desc->control |= ISMT_DESC_CWRL;
|
||||||
|
desc->wr_len_cmd = command;
|
||||||
|
} else {
|
||||||
|
/* Receive Byte */
|
||||||
|
dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n");
|
||||||
|
dma_size = 1;
|
||||||
|
dma_direction = DMA_FROM_DEVICE;
|
||||||
|
desc->rd_len = 1;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case I2C_SMBUS_BYTE_DATA:
|
||||||
|
if (read_write == I2C_SMBUS_WRITE) {
|
||||||
|
/*
|
||||||
|
* Write Byte
|
||||||
|
* Command plus 1 data byte
|
||||||
|
*/
|
||||||
|
dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n");
|
||||||
|
desc->wr_len_cmd = 2;
|
||||||
|
dma_size = 2;
|
||||||
|
dma_direction = DMA_TO_DEVICE;
|
||||||
|
priv->dma_buffer[0] = command;
|
||||||
|
priv->dma_buffer[1] = data->byte;
|
||||||
|
} else {
|
||||||
|
/* Read Byte */
|
||||||
|
dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n");
|
||||||
|
desc->control |= ISMT_DESC_CWRL;
|
||||||
|
desc->wr_len_cmd = command;
|
||||||
|
desc->rd_len = 1;
|
||||||
|
dma_size = 1;
|
||||||
|
dma_direction = DMA_FROM_DEVICE;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case I2C_SMBUS_WORD_DATA:
|
||||||
|
if (read_write == I2C_SMBUS_WRITE) {
|
||||||
|
/* Write Word */
|
||||||
|
dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n");
|
||||||
|
desc->wr_len_cmd = 3;
|
||||||
|
dma_size = 3;
|
||||||
|
dma_direction = DMA_TO_DEVICE;
|
||||||
|
priv->dma_buffer[0] = command;
|
||||||
|
priv->dma_buffer[1] = data->word & 0xff;
|
||||||
|
priv->dma_buffer[2] = data->word >> 8;
|
||||||
|
} else {
|
||||||
|
/* Read Word */
|
||||||
|
dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n");
|
||||||
|
desc->wr_len_cmd = command;
|
||||||
|
desc->control |= ISMT_DESC_CWRL;
|
||||||
|
desc->rd_len = 2;
|
||||||
|
dma_size = 2;
|
||||||
|
dma_direction = DMA_FROM_DEVICE;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case I2C_SMBUS_PROC_CALL:
|
||||||
|
dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
|
||||||
|
desc->wr_len_cmd = 3;
|
||||||
|
desc->rd_len = 2;
|
||||||
|
dma_size = 3;
|
||||||
|
dma_direction = DMA_BIDIRECTIONAL;
|
||||||
|
priv->dma_buffer[0] = command;
|
||||||
|
priv->dma_buffer[1] = data->word & 0xff;
|
||||||
|
priv->dma_buffer[2] = data->word >> 8;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case I2C_SMBUS_BLOCK_DATA:
|
||||||
|
if (read_write == I2C_SMBUS_WRITE) {
|
||||||
|
/* Block Write */
|
||||||
|
dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n");
|
||||||
|
dma_size = data->block[0] + 1;
|
||||||
|
dma_direction = DMA_TO_DEVICE;
|
||||||
|
desc->wr_len_cmd = dma_size;
|
||||||
|
desc->control |= ISMT_DESC_BLK;
|
||||||
|
priv->dma_buffer[0] = command;
|
||||||
|
memcpy(&priv->dma_buffer[1], &data->block[1], dma_size);
|
||||||
|
} else {
|
||||||
|
/* Block Read */
|
||||||
|
dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n");
|
||||||
|
dma_size = I2C_SMBUS_BLOCK_MAX;
|
||||||
|
dma_direction = DMA_FROM_DEVICE;
|
||||||
|
desc->rd_len = dma_size;
|
||||||
|
desc->wr_len_cmd = command;
|
||||||
|
desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
dev_err(dev, "Unsupported transaction %d\n",
|
||||||
|
size);
|
||||||
|
return -EOPNOTSUPP;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* map the data buffer */
|
||||||
|
if (dma_size != 0) {
|
||||||
|
dev_dbg(dev, " dev=%p\n", dev);
|
||||||
|
dev_dbg(dev, " data=%p\n", data);
|
||||||
|
dev_dbg(dev, " dma_buffer=%p\n", priv->dma_buffer);
|
||||||
|
dev_dbg(dev, " dma_size=%d\n", dma_size);
|
||||||
|
dev_dbg(dev, " dma_direction=%d\n", dma_direction);
|
||||||
|
|
||||||
|
dma_addr = dma_map_single(dev,
|
||||||
|
priv->dma_buffer,
|
||||||
|
dma_size,
|
||||||
|
dma_direction);
|
||||||
|
|
||||||
|
if (dma_mapping_error(dev, dma_addr)) {
|
||||||
|
dev_err(dev, "Error in mapping dma buffer %p\n",
|
||||||
|
priv->dma_buffer);
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
dev_dbg(dev, " dma_addr = 0x%016llX\n",
|
||||||
|
dma_addr);
|
||||||
|
|
||||||
|
desc->dptr_low = lower_32_bits(dma_addr);
|
||||||
|
desc->dptr_high = upper_32_bits(dma_addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
INIT_COMPLETION(priv->cmp);
|
||||||
|
|
||||||
|
/* Add the descriptor */
|
||||||
|
ismt_submit_desc(priv);
|
||||||
|
|
||||||
|
/* Now we wait for interrupt completion, 1s */
|
||||||
|
ret = wait_for_completion_timeout(&priv->cmp, HZ*1);
|
||||||
|
|
||||||
|
/* unmap the data buffer */
|
||||||
|
if (dma_size != 0)
|
||||||
|
dma_unmap_single(&adap->dev, dma_addr, dma_size, dma_direction);
|
||||||
|
|
||||||
|
if (unlikely(!ret)) {
|
||||||
|
dev_err(dev, "completion wait timed out\n");
|
||||||
|
ret = -ETIMEDOUT;
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* do any post processing of the descriptor here */
|
||||||
|
ret = ismt_process_desc(desc, data, priv, size, read_write);
|
||||||
|
|
||||||
|
out:
|
||||||
|
/* Update the ring pointer */
|
||||||
|
priv->head++;
|
||||||
|
priv->head %= ISMT_DESC_ENTRIES;
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_func() - report which i2c commands are supported by this adapter
|
||||||
|
* @adap: the i2c host adapter
|
||||||
|
*/
|
||||||
|
static u32 ismt_func(struct i2c_adapter *adap)
|
||||||
|
{
|
||||||
|
return I2C_FUNC_SMBUS_QUICK |
|
||||||
|
I2C_FUNC_SMBUS_BYTE |
|
||||||
|
I2C_FUNC_SMBUS_BYTE_DATA |
|
||||||
|
I2C_FUNC_SMBUS_WORD_DATA |
|
||||||
|
I2C_FUNC_SMBUS_PROC_CALL |
|
||||||
|
I2C_FUNC_SMBUS_BLOCK_DATA |
|
||||||
|
I2C_FUNC_SMBUS_PEC;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* smbus_algorithm - the adapter algorithm and supported functionality
|
||||||
|
* @smbus_xfer: the adapter algorithm
|
||||||
|
* @functionality: functionality supported by the adapter
|
||||||
|
*/
|
||||||
|
static const struct i2c_algorithm smbus_algorithm = {
|
||||||
|
.smbus_xfer = ismt_access,
|
||||||
|
.functionality = ismt_func,
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_handle_isr() - interrupt handler bottom half
|
||||||
|
* @priv: iSMT private data
|
||||||
|
*/
|
||||||
|
static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
|
||||||
|
{
|
||||||
|
complete(&priv->cmp);
|
||||||
|
|
||||||
|
return IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_do_interrupt() - IRQ interrupt handler
|
||||||
|
* @vec: interrupt vector
|
||||||
|
* @data: iSMT private data
|
||||||
|
*/
|
||||||
|
static irqreturn_t ismt_do_interrupt(int vec, void *data)
|
||||||
|
{
|
||||||
|
u32 val;
|
||||||
|
struct ismt_priv *priv = data;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* check to see it's our interrupt, return IRQ_NONE if not ours
|
||||||
|
* since we are sharing interrupt
|
||||||
|
*/
|
||||||
|
val = readl(priv->smba + ISMT_MSTR_MSTS);
|
||||||
|
|
||||||
|
if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
|
||||||
|
return IRQ_NONE;
|
||||||
|
else
|
||||||
|
writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
|
||||||
|
priv->smba + ISMT_MSTR_MSTS);
|
||||||
|
|
||||||
|
return ismt_handle_isr(priv);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_do_msi_interrupt() - MSI interrupt handler
|
||||||
|
* @vec: interrupt vector
|
||||||
|
* @data: iSMT private data
|
||||||
|
*/
|
||||||
|
static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
|
||||||
|
{
|
||||||
|
return ismt_handle_isr(data);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_hw_init() - initialize the iSMT hardware
|
||||||
|
* @priv: iSMT private data
|
||||||
|
*/
|
||||||
|
static void ismt_hw_init(struct ismt_priv *priv)
|
||||||
|
{
|
||||||
|
u32 val;
|
||||||
|
struct device *dev = &priv->pci_dev->dev;
|
||||||
|
|
||||||
|
/* initialize the Master Descriptor Base Address (MDBA) */
|
||||||
|
writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
|
||||||
|
|
||||||
|
/* initialize the Master Control Register (MCTRL) */
|
||||||
|
writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
|
||||||
|
|
||||||
|
/* initialize the Master Status Register (MSTS) */
|
||||||
|
writel(0, priv->smba + ISMT_MSTR_MSTS);
|
||||||
|
|
||||||
|
/* initialize the Master Descriptor Size (MDS) */
|
||||||
|
val = readl(priv->smba + ISMT_MSTR_MDS);
|
||||||
|
writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
|
||||||
|
priv->smba + ISMT_MSTR_MDS);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set the SMBus speed (could use this for slow HW debuggers)
|
||||||
|
*/
|
||||||
|
|
||||||
|
val = readl(priv->smba + ISMT_SPGT);
|
||||||
|
|
||||||
|
switch (bus_speed) {
|
||||||
|
case 0:
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 80:
|
||||||
|
dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
|
||||||
|
writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
|
||||||
|
priv->smba + ISMT_SPGT);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 100:
|
||||||
|
dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
|
||||||
|
writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
|
||||||
|
priv->smba + ISMT_SPGT);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 400:
|
||||||
|
dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
|
||||||
|
writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
|
||||||
|
priv->smba + ISMT_SPGT);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 1000:
|
||||||
|
dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
|
||||||
|
writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
|
||||||
|
priv->smba + ISMT_SPGT);
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
val = readl(priv->smba + ISMT_SPGT);
|
||||||
|
|
||||||
|
switch (val & ISMT_SPGT_SPD_MASK) {
|
||||||
|
case ISMT_SPGT_SPD_80K:
|
||||||
|
bus_speed = 80;
|
||||||
|
break;
|
||||||
|
case ISMT_SPGT_SPD_100K:
|
||||||
|
bus_speed = 100;
|
||||||
|
break;
|
||||||
|
case ISMT_SPGT_SPD_400K:
|
||||||
|
bus_speed = 400;
|
||||||
|
break;
|
||||||
|
case ISMT_SPGT_SPD_1M:
|
||||||
|
bus_speed = 1000;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_dev_init() - initialize the iSMT data structures
|
||||||
|
* @priv: iSMT private data
|
||||||
|
*/
|
||||||
|
static int ismt_dev_init(struct ismt_priv *priv)
|
||||||
|
{
|
||||||
|
/* allocate memory for the descriptor */
|
||||||
|
priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
|
||||||
|
(ISMT_DESC_ENTRIES
|
||||||
|
* sizeof(struct ismt_desc)),
|
||||||
|
&priv->io_rng_dma,
|
||||||
|
GFP_KERNEL);
|
||||||
|
if (!priv->hw)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)));
|
||||||
|
|
||||||
|
priv->head = 0;
|
||||||
|
init_completion(&priv->cmp);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_int_init() - initialize interrupts
|
||||||
|
* @priv: iSMT private data
|
||||||
|
*/
|
||||||
|
static int ismt_int_init(struct ismt_priv *priv)
|
||||||
|
{
|
||||||
|
int err;
|
||||||
|
|
||||||
|
/* Try using MSI interrupts */
|
||||||
|
err = pci_enable_msi(priv->pci_dev);
|
||||||
|
if (err) {
|
||||||
|
dev_warn(&priv->pci_dev->dev,
|
||||||
|
"Unable to use MSI interrupts, falling back to legacy\n");
|
||||||
|
goto intx;
|
||||||
|
}
|
||||||
|
|
||||||
|
err = devm_request_irq(&priv->pci_dev->dev,
|
||||||
|
priv->pci_dev->irq,
|
||||||
|
ismt_do_msi_interrupt,
|
||||||
|
0,
|
||||||
|
"ismt-msi",
|
||||||
|
priv);
|
||||||
|
if (err) {
|
||||||
|
pci_disable_msi(priv->pci_dev);
|
||||||
|
goto intx;
|
||||||
|
}
|
||||||
|
|
||||||
|
priv->using_msi = true;
|
||||||
|
goto done;
|
||||||
|
|
||||||
|
/* Try using legacy interrupts */
|
||||||
|
intx:
|
||||||
|
err = devm_request_irq(&priv->pci_dev->dev,
|
||||||
|
priv->pci_dev->irq,
|
||||||
|
ismt_do_interrupt,
|
||||||
|
IRQF_SHARED,
|
||||||
|
"ismt-intx",
|
||||||
|
priv);
|
||||||
|
if (err) {
|
||||||
|
dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
priv->using_msi = false;
|
||||||
|
|
||||||
|
done:
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct pci_driver ismt_driver;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_probe() - probe for iSMT devices
|
||||||
|
* @pdev: PCI-Express device
|
||||||
|
* @id: PCI-Express device ID
|
||||||
|
*/
|
||||||
|
static int
|
||||||
|
ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||||
|
{
|
||||||
|
int err;
|
||||||
|
struct ismt_priv *priv;
|
||||||
|
unsigned long start, len;
|
||||||
|
|
||||||
|
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||||
|
if (!priv)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
pci_set_drvdata(pdev, priv);
|
||||||
|
i2c_set_adapdata(&priv->adapter, priv);
|
||||||
|
priv->adapter.owner = THIS_MODULE;
|
||||||
|
|
||||||
|
priv->adapter.class = I2C_CLASS_HWMON;
|
||||||
|
|
||||||
|
priv->adapter.algo = &smbus_algorithm;
|
||||||
|
|
||||||
|
/* set up the sysfs linkage to our parent device */
|
||||||
|
priv->adapter.dev.parent = &pdev->dev;
|
||||||
|
|
||||||
|
/* number of retries on lost arbitration */
|
||||||
|
priv->adapter.retries = ISMT_MAX_RETRIES;
|
||||||
|
|
||||||
|
priv->pci_dev = pdev;
|
||||||
|
|
||||||
|
err = pcim_enable_device(pdev);
|
||||||
|
if (err) {
|
||||||
|
dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
|
||||||
|
err);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* enable bus mastering */
|
||||||
|
pci_set_master(pdev);
|
||||||
|
|
||||||
|
/* Determine the address of the SMBus area */
|
||||||
|
start = pci_resource_start(pdev, SMBBAR);
|
||||||
|
len = pci_resource_len(pdev, SMBBAR);
|
||||||
|
if (!start || !len) {
|
||||||
|
dev_err(&pdev->dev,
|
||||||
|
"SMBus base address uninitialized, upgrade BIOS\n");
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
snprintf(priv->adapter.name, sizeof(priv->adapter.name),
|
||||||
|
"SMBus iSMT adapter at %lx", start);
|
||||||
|
|
||||||
|
dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
|
||||||
|
dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
|
||||||
|
|
||||||
|
err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
|
||||||
|
if (err) {
|
||||||
|
dev_err(&pdev->dev, "ACPI resource conflict!\n");
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
|
||||||
|
if (err) {
|
||||||
|
dev_err(&pdev->dev,
|
||||||
|
"Failed to request SMBus region 0x%lx-0x%lx\n",
|
||||||
|
start, start + len);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
priv->smba = pcim_iomap(pdev, SMBBAR, len);
|
||||||
|
if (!priv->smba) {
|
||||||
|
dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
|
||||||
|
err = -ENODEV;
|
||||||
|
goto fail;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
|
||||||
|
(pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
|
||||||
|
if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
|
||||||
|
(pci_set_consistent_dma_mask(pdev,
|
||||||
|
DMA_BIT_MASK(32)) != 0)) {
|
||||||
|
dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
|
||||||
|
pdev);
|
||||||
|
goto fail;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
err = ismt_dev_init(priv);
|
||||||
|
if (err)
|
||||||
|
goto fail;
|
||||||
|
|
||||||
|
ismt_hw_init(priv);
|
||||||
|
|
||||||
|
err = ismt_int_init(priv);
|
||||||
|
if (err)
|
||||||
|
goto fail;
|
||||||
|
|
||||||
|
err = i2c_add_adapter(&priv->adapter);
|
||||||
|
if (err) {
|
||||||
|
dev_err(&pdev->dev, "Failed to add SMBus iSMT adapter\n");
|
||||||
|
err = -ENODEV;
|
||||||
|
goto fail;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
fail:
|
||||||
|
pci_release_region(pdev, SMBBAR);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_remove() - release driver resources
|
||||||
|
* @pdev: PCI-Express device
|
||||||
|
*/
|
||||||
|
static void ismt_remove(struct pci_dev *pdev)
|
||||||
|
{
|
||||||
|
struct ismt_priv *priv = pci_get_drvdata(pdev);
|
||||||
|
|
||||||
|
i2c_del_adapter(&priv->adapter);
|
||||||
|
pci_release_region(pdev, SMBBAR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_suspend() - place the device in suspend
|
||||||
|
* @pdev: PCI-Express device
|
||||||
|
* @mesg: PM message
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_PM
|
||||||
|
static int ismt_suspend(struct pci_dev *pdev, pm_message_t mesg)
|
||||||
|
{
|
||||||
|
pci_save_state(pdev);
|
||||||
|
pci_set_power_state(pdev, pci_choose_state(pdev, mesg));
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ismt_resume() - PCI resume code
|
||||||
|
* @pdev: PCI-Express device
|
||||||
|
*/
|
||||||
|
static int ismt_resume(struct pci_dev *pdev)
|
||||||
|
{
|
||||||
|
pci_set_power_state(pdev, PCI_D0);
|
||||||
|
pci_restore_state(pdev);
|
||||||
|
return pci_enable_device(pdev);
|
||||||
|
}
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
#define ismt_suspend NULL
|
||||||
|
#define ismt_resume NULL
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static struct pci_driver ismt_driver = {
|
||||||
|
.name = "ismt_smbus",
|
||||||
|
.id_table = ismt_ids,
|
||||||
|
.probe = ismt_probe,
|
||||||
|
.remove = ismt_remove,
|
||||||
|
.suspend = ismt_suspend,
|
||||||
|
.resume = ismt_resume,
|
||||||
|
};
|
||||||
|
|
||||||
|
module_pci_driver(ismt_driver);
|
||||||
|
|
||||||
|
MODULE_LICENSE("Dual BSD/GPL");
|
||||||
|
MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
|
||||||
|
MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");
|
||||||
Loading…
Reference in New Issue
Block a user