forked from luck/tmp_suning_uos_patched
[MIPS] Iomap implementation.
This implementation has support for the concept of one separate ioport address space by PCI domain. A pointer to the virtual address where the port space of a domain has been mapped has been added to struct pci_controller and systems should be fixed to fill in this value. For single domain systems this will be the same value as passed to set_io_port_base(). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
4c1569949a
commit
140c1729a2
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@ -5,7 +5,8 @@
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lib-y += csum_partial.o memcpy.o memset.o promlib.o \
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strlen_user.o strncpy_user.o strnlen_user.o uncached.o
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obj-y += iomap.o
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obj-y += iomap.o
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obj-$(CONFIG_PCI) += iomap-pci.o
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# libgcc-style stuff needed in the kernel
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lib-y += ashldi3.o ashrdi3.o lshrdi3.o
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74
arch/mips/lib/iomap-pci.c
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74
arch/mips/lib/iomap-pci.c
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@ -0,0 +1,74 @@
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/*
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* Implement the default iomap interfaces
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*
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* (C) Copyright 2004 Linus Torvalds
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* (C) Copyright 2006 Ralf Baechle <ralf@linux-mips.org>
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* (C) Copyright 2007 MIPS Technologies, Inc.
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <asm/io.h>
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static void __iomem *ioport_map_pci(struct pci_dev *dev,
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unsigned long port, unsigned int nr)
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{
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struct pci_controller *ctrl = dev->bus->sysdata;
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unsigned long base = ctrl->io_map_base;
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/* This will eventually become a BUG_ON but for now be gentle */
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if (unlikely(!ctrl->io_map_base)) {
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struct pci_bus *bus = dev->bus;
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char name[8];
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while (bus->parent)
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bus = bus->parent;
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ctrl->io_map_base = base = mips_io_port_base;
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sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number);
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printk(KERN_WARNING "io_map_base of root PCI bus %s unset. "
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"Trying to continue but you better\nfix this issue or "
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"report it to linux-mips@linux-mips.org or your "
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"vendor.\n", name);
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#ifdef CONFIG_PCI_DOMAINS
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panic("To avoid data corruption io_map_base MUST be set with "
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"multiple PCI domains.");
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#endif
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}
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return (void __iomem *) (ctrl->io_map_base + port);
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}
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/*
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* Create a virtual mapping cookie for a PCI BAR (memory or IO)
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*/
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
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{
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unsigned long start = pci_resource_start(dev, bar);
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unsigned long len = pci_resource_len(dev, bar);
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unsigned long flags = pci_resource_flags(dev, bar);
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if (!len || !start)
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return NULL;
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if (maxlen && len > maxlen)
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len = maxlen;
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if (flags & IORESOURCE_IO)
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return ioport_map_pci(dev, start, len);
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if (flags & IORESOURCE_MEM) {
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if (flags & IORESOURCE_CACHEABLE)
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return ioremap(start, len);
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return ioremap_nocache(start, len);
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}
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/* What? */
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return NULL;
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}
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EXPORT_SYMBOL(pci_iomap);
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void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
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{
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iounmap(addr);
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}
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EXPORT_SYMBOL(pci_iounmap);
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@ -1,78 +1,227 @@
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/*
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* iomap.c, Memory Mapped I/O routines for MIPS architecture.
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* Implement the default iomap interfaces
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*
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* This code is based on lib/iomap.c, by Linus Torvalds.
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*
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* Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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* (C) Copyright 2004 Linus Torvalds
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* (C) Copyright 2006 Ralf Baechle <ralf@linux-mips.org>
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* (C) Copyright 2007 MIPS Technologies, Inc.
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <asm/io.h>
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/*
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* Read/write from/to an (offsettable) iomem cookie. It might be a PIO
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* access or a MMIO access, these functions don't care. The info is
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* encoded in the hardware mapping set up by the mapping functions
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* (or the cookie itself, depending on implementation and hw).
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*
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* The generic routines don't assume any hardware mappings, and just
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* encode the PIO/MMIO as part of the cookie. They coldly assume that
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* the MMIO IO mappings are not in the low address range.
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*
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* Architectures for which this is not true can't use this generic
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* implementation and should do their own copy.
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*/
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#define PIO_MASK 0x0ffffUL
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unsigned int ioread8(void __iomem *addr)
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{
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return readb(addr);
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}
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EXPORT_SYMBOL(ioread8);
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unsigned int ioread16(void __iomem *addr)
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{
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return readw(addr);
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}
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EXPORT_SYMBOL(ioread16);
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unsigned int ioread16be(void __iomem *addr)
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{
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return be16_to_cpu(__raw_readw(addr));
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}
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EXPORT_SYMBOL(ioread16be);
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unsigned int ioread32(void __iomem *addr)
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{
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return readl(addr);
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}
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EXPORT_SYMBOL(ioread32);
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unsigned int ioread32be(void __iomem *addr)
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{
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return be32_to_cpu(__raw_readl(addr));
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}
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EXPORT_SYMBOL(ioread32be);
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void iowrite8(u8 val, void __iomem *addr)
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{
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writeb(val, addr);
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}
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EXPORT_SYMBOL(iowrite8);
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void iowrite16(u16 val, void __iomem *addr)
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{
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writew(val, addr);
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}
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EXPORT_SYMBOL(iowrite16);
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void iowrite16be(u16 val, void __iomem *addr)
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{
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__raw_writew(cpu_to_be16(val), addr);
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}
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EXPORT_SYMBOL(iowrite16be);
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void iowrite32(u32 val, void __iomem *addr)
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{
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writel(val, addr);
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}
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EXPORT_SYMBOL(iowrite32);
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void iowrite32be(u32 val, void __iomem *addr)
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{
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__raw_writel(cpu_to_be32(val), addr);
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}
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EXPORT_SYMBOL(iowrite32be);
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/*
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* These are the "repeat MMIO read/write" functions.
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* Note the "__raw" accesses, since we don't want to
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* convert to CPU byte order. We write in "IO byte
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* order" (we also don't have IO barriers).
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*/
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static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
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{
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while (--count >= 0) {
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u8 data = __raw_readb(addr);
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*dst = data;
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dst++;
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}
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}
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static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
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{
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while (--count >= 0) {
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u16 data = __raw_readw(addr);
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*dst = data;
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dst++;
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}
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}
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static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
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{
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while (--count >= 0) {
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u32 data = __raw_readl(addr);
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*dst = data;
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dst++;
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}
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}
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static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
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{
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while (--count >= 0) {
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__raw_writeb(*src, addr);
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src++;
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}
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}
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static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
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{
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while (--count >= 0) {
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__raw_writew(*src, addr);
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src++;
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}
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}
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static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
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{
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while (--count >= 0) {
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__raw_writel(*src, addr);
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src++;
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}
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}
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void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
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{
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mmio_insb(addr, dst, count);
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}
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EXPORT_SYMBOL(ioread8_rep);
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void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
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{
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mmio_insw(addr, dst, count);
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}
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EXPORT_SYMBOL(ioread16_rep);
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void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
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{
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mmio_insl(addr, dst, count);
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}
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EXPORT_SYMBOL(ioread32_rep);
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void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
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{
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mmio_outsb(addr, src, count);
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}
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EXPORT_SYMBOL(iowrite8_rep);
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void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
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{
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mmio_outsw(addr, src, count);
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}
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EXPORT_SYMBOL(iowrite16_rep);
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void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
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{
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mmio_outsl(addr, src, count);
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}
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EXPORT_SYMBOL(iowrite32_rep);
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/*
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* Create a virtual mapping cookie for an IO port range
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*
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* This uses the same mapping are as the in/out family which has to be setup
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* by the platform initialization code.
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*
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* Just to make matters somewhat more interesting on MIPS systems with
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* multiple host bridge each will have it's own ioport address space.
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*/
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static void __iomem *ioport_map_legacy(unsigned long port, unsigned int nr)
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{
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return (void __iomem *) (mips_io_port_base + port);
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}
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void __iomem *ioport_map(unsigned long port, unsigned int nr)
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{
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unsigned long end;
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end = port + nr - 1UL;
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if (ioport_resource.start > port ||
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ioport_resource.end < end || port > end)
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if (port > PIO_MASK)
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return NULL;
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return (void __iomem *)(mips_io_port_base + port);
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return ioport_map_legacy(port, nr);
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}
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EXPORT_SYMBOL(ioport_map);
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void ioport_unmap(void __iomem *addr)
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{
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/* Nothing to do */
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}
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EXPORT_SYMBOL(ioport_map);
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EXPORT_SYMBOL(ioport_unmap);
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
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{
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unsigned long start, len, flags;
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if (dev == NULL)
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return NULL;
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start = pci_resource_start(dev, bar);
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len = pci_resource_len(dev, bar);
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if (!start || !len)
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return NULL;
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if (maxlen != 0 && len > maxlen)
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len = maxlen;
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flags = pci_resource_flags(dev, bar);
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if (flags & IORESOURCE_IO)
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return ioport_map(start, len);
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if (flags & IORESOURCE_MEM) {
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if (flags & IORESOURCE_CACHEABLE)
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return ioremap_cachable(start, len);
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return ioremap_nocache(start, len);
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}
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return NULL;
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}
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void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
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{
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iounmap(addr);
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}
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EXPORT_SYMBOL(pci_iomap);
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EXPORT_SYMBOL(pci_iounmap);
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@ -79,6 +79,14 @@ void __init register_pci_controller(struct pci_controller *hose)
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{
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*hose_tail = hose;
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hose_tail = &hose->next;
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/*
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* Do not panic here but later - this might hapen before console init.
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*/
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if (!hose->io_map_base) {
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printk(KERN_WARNING
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"registering PCI controller with io_map_base unset\n");
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}
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}
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/* Most MIPS systems have straight-forward swizzling needs. */
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@ -20,6 +20,7 @@
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#include <asm/byteorder.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm-generic/iomap.h>
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#include <asm/page.h>
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#include <asm/pgtable-bits.h>
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#include <asm/processor.h>
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@ -517,34 +518,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
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memcpy((void __force *) dst, src, count);
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}
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/*
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* Memory Mapped I/O
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*/
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#define ioread8(addr) readb(addr)
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#define ioread16(addr) readw(addr)
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#define ioread32(addr) readl(addr)
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#define iowrite8(b,addr) writeb(b,addr)
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#define iowrite16(w,addr) writew(w,addr)
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#define iowrite32(l,addr) writel(l,addr)
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#define ioread8_rep(a,b,c) readsb(a,b,c)
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#define ioread16_rep(a,b,c) readsw(a,b,c)
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#define ioread32_rep(a,b,c) readsl(a,b,c)
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#define iowrite8_rep(a,b,c) writesb(a,b,c)
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#define iowrite16_rep(a,b,c) writesw(a,b,c)
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#define iowrite32_rep(a,b,c) writesl(a,b,c)
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/* Create a virtual mapping cookie for an IO port range */
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extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
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extern void ioport_unmap(void __iomem *);
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/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
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struct pci_dev;
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extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
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extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
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/*
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* ISA space is 'always mapped' on currently supported MIPS systems, no need
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* to explicitly ioremap() it. The fact that the ISA IO space is mapped
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@ -32,6 +32,7 @@ struct pci_controller {
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unsigned long mem_offset;
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struct resource *io_resource;
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unsigned long io_offset;
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unsigned long io_map_base;
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unsigned int index;
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/* For compatibility with current (as of July 2003) pciutils
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