forked from luck/tmp_suning_uos_patched
ethtool: Add support for 400Gbps (50Gbps per lane) link modes
Add support for 400Gbps speed, link modes of 50Gbps per lane Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -8,7 +8,7 @@
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const char *phy_speed_to_str(int speed)
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{
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BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 69,
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BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 74,
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"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
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"If a speed or mode has been added please update phy_speed_to_str "
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"and the PHY settings array.\n");
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@ -42,6 +42,8 @@ const char *phy_speed_to_str(int speed)
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return "100Gbps";
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case SPEED_200000:
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return "200Gbps";
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case SPEED_400000:
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return "400Gbps";
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case SPEED_UNKNOWN:
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return "Unknown";
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default:
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@ -70,6 +72,12 @@ EXPORT_SYMBOL_GPL(phy_duplex_to_str);
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.bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}
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static const struct phy_setting settings[] = {
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/* 400G */
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PHY_SETTING( 400000, FULL, 400000baseCR8_Full ),
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PHY_SETTING( 400000, FULL, 400000baseKR8_Full ),
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PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full ),
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PHY_SETTING( 400000, FULL, 400000baseDR8_Full ),
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PHY_SETTING( 400000, FULL, 400000baseSR8_Full ),
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/* 200G */
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PHY_SETTING( 200000, FULL, 200000baseCR4_Full ),
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PHY_SETTING( 200000, FULL, 200000baseKR4_Full ),
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@ -1507,6 +1507,11 @@ enum ethtool_link_mode_bit_indices {
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ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,
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ETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,
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ETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,
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ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69,
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ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70,
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ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,
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ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,
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ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,
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/* must be last entry */
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__ETHTOOL_LINK_MODE_MASK_NBITS
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@ -1618,6 +1623,7 @@ enum ethtool_link_mode_bit_indices {
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#define SPEED_56000 56000
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#define SPEED_100000 100000
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#define SPEED_200000 200000
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#define SPEED_400000 400000
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#define SPEED_UNKNOWN -1
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