forked from luck/tmp_suning_uos_patched
arm64: mm: Rename post_ttbr0_update_workaround
The post_ttbr0_update_workaround hook applies to any change to TTBRx_EL1. Since we're using TTBR1 for the ASID, rename the hook to make it clearer as to what it's doing. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Laura Abbott <labbott@redhat.com> Tested-by: Shanker Donthineni <shankerd@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -477,10 +477,9 @@ alternative_endif
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.endm
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/*
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/*
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* Errata workaround post TTBR0_EL1 update.
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* Errata workaround post TTBRx_EL1 update.
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*/
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.macro post_ttbr0_update_workaround
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.macro post_ttbr_update_workaround
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#ifdef CONFIG_CAVIUM_ERRATUM_27456
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alternative_if ARM64_WORKAROUND_CAVIUM_27456
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ic iallu
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@ -257,7 +257,7 @@ alternative_else_nop_endif
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* Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
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* corruption).
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*/
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post_ttbr0_update_workaround
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post_ttbr_update_workaround
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.endif
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1:
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.if \el != 0
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@ -145,7 +145,7 @@ ENTRY(cpu_do_switch_mm)
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isb
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msr ttbr0_el1, x0 // now update TTBR0
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isb
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post_ttbr0_update_workaround
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post_ttbr_update_workaround
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ret
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ENDPROC(cpu_do_switch_mm)
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