AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

ARM: dts: r8a7790: Convert to new LVDS DT bindings

Browse Source 
The internal LVDS encoder now has DT bindings separate from the DU. Port
the device tree over to the new model.

Fixes: c6a27fa41f ("drm: rcar-du: Convert LVDS encoder code to bridge driver")
Fixes: 4bdb7aa7dc ("ARM: dts: r8a7790: add soc node")
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Laurent Pinchart 2018-04-20 14:57:52 +03:00 committed by Simon Horman
parent 60cc43fc88
commit 15a1ff30d8
2 changed files with 74 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
arch/arm/boot/dts/r8a7790-lager.dts
View File

@ -379,7 +379,7 @@ ports {
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
remote-endpoint = <&lvds0_out>;
};
};
@ -467,10 +467,8 @@ &du {
status = "okay";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
<&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
"dclkin.0", "dclkin.1";
clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1";
ports {
port@0 {
@ -478,12 +476,26 @@ endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
endpoint {
remote-endpoint = <&adv7511_in>;
};
};
port@2 {
};
};
&lvds1 {
status = "okay";
ports {
port@1 {
lvds_connector: endpoint {
};
};

65
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -1627,18 +1627,13 @@ jpu: jpeg-codec@fe980000 {
du: display@feb00000 {
compatible = "renesas,du-r8a7790";
reg = <0 0xfeb00000 0 0x70000>,
<0 0xfeb90000 0 0x1c>,
<0 0xfeb94000 0 0x1c>;
reg-names = "du", "lvds.0", "lvds.1";
reg = <0 0xfeb00000 0 0x70000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
<&cpg CPG_MOD 725>;
clock-names = "du.0", "du.1", "du.2", "lvds.0",
"lvds.1";
<&cpg CPG_MOD 722>;
clock-names = "du.0", "du.1", "du.2";
status = "disabled";
ports {
@ -1653,11 +1648,65 @@ du_out_rgb: endpoint {
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
};
};
port@2 {
reg = <2>;
du_out_lvds1: endpoint {
remote-endpoint = <&lvds1_in>;
};
};
};
};
lvds0: lvds@feb90000 {
compatible = "renesas,r8a7790-lvds";
reg = <0 0xfeb90000 0 0x1c>;
clocks = <&cpg CPG_MOD 726>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 726>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
lvds1: lvds@feb94000 {
compatible = "renesas,r8a7790-lvds";
reg = <0 0xfeb94000 0 0x1c>;
clocks = <&cpg CPG_MOD 725>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 725>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds1_in: endpoint {
remote-endpoint = <&du_out_lvds1>;
};
};
port@1 {
reg = <1>;
lvds1_out: endpoint {
};
};
};