forked from luck/tmp_suning_uos_patched
bnx2x: Enable FC when parallel-detect is used
When parallel detect is used, flow-control is set to the req_fc_auto_adv instead of none. Motive: when 577xx is FC configuration is set to AUTO, while LP speed is set to FORCE mode and FC to force RX/TX, link would come up using parallel detect, and the FC will be set to NONE since FC capabilities were not negotiated, although the LP is setting FC to force RX/TX. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1621,6 +1621,39 @@ static u8 bnx2x_ext_phy_resolve_fc(struct link_params *params,
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return ret;
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}
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static u8 bnx2x_direct_parallel_detect_used(struct link_params *params)
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{
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struct bnx2x *bp = params->bp;
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u16 pd_10g, status2_1000x;
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_SERDES_DIGITAL,
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MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
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&status2_1000x);
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_SERDES_DIGITAL,
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MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
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&status2_1000x);
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if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
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DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
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params->port);
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return 1;
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}
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_10G_PARALLEL_DETECT,
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MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
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&pd_10g);
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if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
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DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
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params->port);
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return 1;
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}
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return 0;
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}
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static void bnx2x_flow_ctrl_resolve(struct link_params *params,
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struct link_vars *vars,
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@ -1639,6 +1672,10 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
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(!(vars->phy_flags & PHY_SGMII_FLAG)) &&
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(XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
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if (bnx2x_direct_parallel_detect_used(params)) {
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vars->flow_ctrl = params->req_fc_auto_adv;
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return;
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}
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if ((gp_status &
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(MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
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MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
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@ -4920,6 +4920,8 @@
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#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
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#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
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#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
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#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
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#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
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#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
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@ -4944,6 +4946,8 @@
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#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
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#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
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#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
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#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
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#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
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#define MDIO_SERDES_DIGITAL_MISC1 0x18
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#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
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#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
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