forked from luck/tmp_suning_uos_patched
ARM: dts: stm32: change pinctrl bindings definition
Initially each pin was declared in "include/dt-bindings/stm32<SOC>-pinfunc.h" and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX). Since this approach was approved, the number of supported MCU has increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new file in "include/dt-bindings" each time a new STM32 SOC arrives I propose a new approach which consist to use a macro to define pin muxing in device tree. All STM32 will use the common macro to define pinmux. Furthermore, it will make STM32 maintenance and integration of new SOC easier . Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Vikas MANOCHA <vikas.manocha@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Alexandre Torgue
parent
6d3b3745c5
commit
162d58c26d
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@ -143,6 +143,24 @@ Required properties:
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* 16 : Alternate Function 15
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* 17 : Analog
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To simplify the usage, macro is available to generate "pinmux" field.
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This macro is available here:
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- include/dt-bindings/pinctrl/stm32-pinfunc.h
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Some examples of using macro:
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/* GPIO A9 set as alernate function 2 */
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... {
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pinmux = <STM32_PINMUX('A', 9, AF2)>;
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};
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/* GPIO A9 set as GPIO */
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... {
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pinmux = <STM32_PINMUX('A', 9, GPIO)>;
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};
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/* GPIO A9 set as analog */
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... {
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pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
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};
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Optional properties:
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- GENERIC_PINCONFIG: is the generic pinconfig options to use.
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Available options are:
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@ -165,13 +183,13 @@ pin-controller {
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...
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usart1_pins_a: usart1@0 {
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pins1 {
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pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
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pinmux = <STM32_PINMUX('A', 9, AF7)>;
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
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pinmux = <STM32_PINMUX('A', 10, AF7)>;
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bias-disable;
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};
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};
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@ -40,7 +40,7 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include <dt-bindings/mfd/stm32f4-rcc.h>
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/ {
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@ -165,35 +165,35 @@ gpiok: gpio@40022800 {
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usart1_pins_a: usart1@0 {
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pins1 {
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pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
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pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
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pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
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bias-disable;
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};
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};
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usart3_pins_a: usart3@0 {
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pins1 {
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pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
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pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
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pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
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bias-disable;
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};
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};
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usbotg_fs_pins_a: usbotg_fs@0 {
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pins {
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pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
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<STM32F429_PA11_FUNC_OTG_FS_DM>,
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<STM32F429_PA12_FUNC_OTG_FS_DP>;
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pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
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<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
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<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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@ -202,9 +202,9 @@ pins {
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usbotg_fs_pins_b: usbotg_fs@1 {
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pins {
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pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
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<STM32F429_PB14_FUNC_OTG_HS_DM>,
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<STM32F429_PB15_FUNC_OTG_HS_DP>;
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pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
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<STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
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<STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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@ -213,18 +213,18 @@ pins {
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usbotg_hs_pins_a: usbotg_hs@0 {
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pins {
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pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
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<STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
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<STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
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<STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
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<STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
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<STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
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<STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
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<STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
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<STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
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<STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
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<STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
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<STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
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pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
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<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
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<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
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<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
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<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
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<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
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<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
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<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
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<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
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<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
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<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
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<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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@ -233,49 +233,49 @@ pins {
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ethernet_mii: mii@0 {
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pins {
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pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
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<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
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<STM32F429_PC2_FUNC_ETH_MII_TXD2>,
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<STM32F429_PB8_FUNC_ETH_MII_TXD3>,
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<STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
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<STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
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<STM32F429_PA2_FUNC_ETH_MDIO>,
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<STM32F429_PC1_FUNC_ETH_MDC>,
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<STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
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<STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
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<STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
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<STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
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<STM32F429_PH6_FUNC_ETH_MII_RXD2>,
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<STM32F429_PH7_FUNC_ETH_MII_RXD3>;
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pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
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<STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
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<STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
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<STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
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<STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
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<STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
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<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
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<STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
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<STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
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<STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
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<STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
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<STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
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<STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
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<STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
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slew-rate = <2>;
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};
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};
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adc3_in8_pin: adc@200 {
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pins {
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pinmux = <STM32F429_PF10_FUNC_ANALOG>;
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pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
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};
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};
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pwm1_pins: pwm@1 {
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pins {
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pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
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<STM32F429_PB13_FUNC_TIM1_CH1N>,
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<STM32F429_PB12_FUNC_TIM1_BKIN>;
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pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
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<STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
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<STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
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};
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};
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pwm3_pins: pwm@3 {
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pins {
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pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
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<STM32F429_PB5_FUNC_TIM3_CH2>;
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pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
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<STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
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};
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};
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i2c1_pins: i2c1@0 {
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pins {
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pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
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<STM32F429_PB6_FUNC_I2C1_SCL>;
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pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
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<STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
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bias-disable;
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drive-open-drain;
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slew-rate = <3>;
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@ -284,55 +284,55 @@ pins {
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ltdc_pins: ltdc@0 {
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pins {
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pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
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<STM32F429_PI13_FUNC_LCD_VSYNC>,
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<STM32F429_PI14_FUNC_LCD_CLK>,
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<STM32F429_PI15_FUNC_LCD_R0>,
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<STM32F429_PJ0_FUNC_LCD_R1>,
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<STM32F429_PJ1_FUNC_LCD_R2>,
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<STM32F429_PJ2_FUNC_LCD_R3>,
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<STM32F429_PJ3_FUNC_LCD_R4>,
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<STM32F429_PJ4_FUNC_LCD_R5>,
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<STM32F429_PJ5_FUNC_LCD_R6>,
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<STM32F429_PJ6_FUNC_LCD_R7>,
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<STM32F429_PJ7_FUNC_LCD_G0>,
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<STM32F429_PJ8_FUNC_LCD_G1>,
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<STM32F429_PJ9_FUNC_LCD_G2>,
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<STM32F429_PJ10_FUNC_LCD_G3>,
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<STM32F429_PJ11_FUNC_LCD_G4>,
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<STM32F429_PJ12_FUNC_LCD_B0>,
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<STM32F429_PJ13_FUNC_LCD_B1>,
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<STM32F429_PJ14_FUNC_LCD_B2>,
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<STM32F429_PJ15_FUNC_LCD_B3>,
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<STM32F429_PK0_FUNC_LCD_G5>,
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<STM32F429_PK1_FUNC_LCD_G6>,
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<STM32F429_PK2_FUNC_LCD_G7>,
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<STM32F429_PK3_FUNC_LCD_B4>,
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<STM32F429_PK4_FUNC_LCD_B5>,
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<STM32F429_PK5_FUNC_LCD_B6>,
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<STM32F429_PK6_FUNC_LCD_B7>,
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<STM32F429_PK7_FUNC_LCD_DE>;
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pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
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<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
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<STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
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<STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
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<STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
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<STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
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<STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
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<STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
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<STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
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<STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
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<STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
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<STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
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<STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
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<STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
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<STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
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<STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
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<STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
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<STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
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<STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
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<STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
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<STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
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<STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
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<STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
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<STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
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<STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
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<STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
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<STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
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<STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
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slew-rate = <2>;
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};
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};
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dcmi_pins: dcmi@0 {
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pins {
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pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
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<STM32F429_PB7_FUNC_DCMI_VSYNC>,
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<STM32F429_PA6_FUNC_DCMI_PIXCLK>,
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<STM32F429_PC6_FUNC_DCMI_D0>,
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<STM32F429_PC7_FUNC_DCMI_D1>,
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<STM32F429_PC8_FUNC_DCMI_D2>,
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<STM32F429_PC9_FUNC_DCMI_D3>,
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<STM32F429_PC11_FUNC_DCMI_D4>,
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<STM32F429_PD3_FUNC_DCMI_D5>,
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<STM32F429_PB8_FUNC_DCMI_D6>,
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<STM32F429_PE6_FUNC_DCMI_D7>,
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<STM32F429_PC10_FUNC_DCMI_D8>,
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<STM32F429_PC12_FUNC_DCMI_D9>,
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<STM32F429_PD6_FUNC_DCMI_D10>,
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<STM32F429_PD2_FUNC_DCMI_D11>;
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pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
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<STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
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<STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
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<STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
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<STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
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<STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
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<STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
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<STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
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<STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
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<STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
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<STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
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<STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
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<STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
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<STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
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<STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
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bias-disable;
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drive-push-pull;
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slew-rate = <3>;
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@ -42,7 +42,7 @@
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#include "skeleton.dtsi"
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#include "armv7-m.dtsi"
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#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include <dt-bindings/clock/stm32fx-clock.h>
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#include <dt-bindings/mfd/stm32f7-rcc.h>
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@ -619,7 +619,7 @@ gpiok: gpio@40022800 {
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cec_pins_a: cec@0 {
|
||||
pins {
|
||||
pinmux = <STM32F746_PA15_FUNC_HDMI_CEC>;
|
||||
pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
|
||||
slew-rate = <0>;
|
||||
drive-open-drain;
|
||||
bias-disable;
|
||||
|
|
@ -628,34 +628,34 @@ pins {
|
|||
|
||||
usart1_pins_a: usart1@0 {
|
||||
pins1 {
|
||||
pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
|
||||
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
|
||||
pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_pins_b: usart1@1 {
|
||||
pins1 {
|
||||
pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
|
||||
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
|
||||
pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_b: i2c1@0 {
|
||||
pins {
|
||||
pinmux = <STM32F746_PB9_FUNC_I2C1_SDA>,
|
||||
<STM32F746_PB8_FUNC_I2C1_SCL>;
|
||||
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
|
||||
<STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
|
||||
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
|
|
@ -141,26 +141,26 @@ gpiok: gpio@58022800 {
|
|||
|
||||
usart1_pins: usart1@0 {
|
||||
pins1 {
|
||||
pinmux = <STM32H7_PB14_FUNC_USART1_TX>;
|
||||
pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32H7_PB15_FUNC_USART1_RX>;
|
||||
pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart2_pins: usart2@0 {
|
||||
pins1 {
|
||||
pinmux = <STM32H7_PD5_FUNC_USART2_TX>;
|
||||
pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32H7_PD6_FUNC_USART2_RX>;
|
||||
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
30
include/dt-bindings/pinctrl/stm32-pinfunc.h
Normal file
30
include/dt-bindings/pinctrl/stm32-pinfunc.h
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
#ifndef _DT_BINDINGS_STM32_PINFUNC_H
|
||||
#define _DT_BINDINGS_STM32_PINFUNC_H
|
||||
|
||||
/* define PIN modes */
|
||||
#define GPIO 0x0
|
||||
#define AF0 0x1
|
||||
#define AF1 0x2
|
||||
#define AF2 0x3
|
||||
#define AF3 0x4
|
||||
#define AF4 0x5
|
||||
#define AF5 0x6
|
||||
#define AF6 0x7
|
||||
#define AF7 0x8
|
||||
#define AF8 0x9
|
||||
#define AF9 0xa
|
||||
#define AF10 0xb
|
||||
#define AF11 0xc
|
||||
#define AF12 0xd
|
||||
#define AF13 0xe
|
||||
#define AF14 0xf
|
||||
#define AF15 0x10
|
||||
#define ANALOG 0x11
|
||||
|
||||
/* define Pins number*/
|
||||
#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
|
||||
|
||||
#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user