forked from luck/tmp_suning_uos_patched
Merge branches 'clk-vc5', 'clk-hsdk', 'clk-mediatek' and 'clk-baikal' into clk-next
- Support IDT VersaClock 5P49V5925 - Bunch of updates for HSDK clock generation unit (CGU) driver - New clk driver for Baikal-T1 SoCs * clk-vc5: dt: Add bindings for IDT VersaClock 5P49V5925 clk: vc5: Add support for IDT VersaClock 5P49V6965 * clk-hsdk: CLK: HSDK: CGU: add support for 148.5MHz clock CLK: HSDK: CGU: support PLL bypassing CLK: HSDK: CGU: check if PLL is bypassed first * clk-mediatek: clk: mediatek: assign the initial value to clk_init_data of mtk_mux clk: mediatek: Add MT6765 clock support clk: mediatek: add mt6765 clock IDs dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC * clk-baikal: clk: Add Baikal-T1 CCU Dividers driver clk: Add Baikal-T1 CCU PLLs driver dt-bindings: clk: Add Baikal-T1 CCU Dividers binding dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
This commit is contained in:
Stephen Boyd
commit
166e4b4841
|
|
@ -8,6 +8,7 @@ Required Properties:
|
|||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-apmixedsys"
|
||||
- "mediatek,mt2712-apmixedsys", "syscon"
|
||||
- "mediatek,mt6765-apmixedsys", "syscon"
|
||||
- "mediatek,mt6779-apmixedsys", "syscon"
|
||||
- "mediatek,mt6797-apmixedsys"
|
||||
- "mediatek,mt7622-apmixedsys"
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ Required Properties:
|
|||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-audsys", "syscon"
|
||||
- "mediatek,mt6765-audsys", "syscon"
|
||||
- "mediatek,mt6779-audio", "syscon"
|
||||
- "mediatek,mt7622-audsys", "syscon"
|
||||
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ The MediaTek camsys controller provides various clocks to the system.
|
|||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6765-camsys", "syscon"
|
||||
- "mediatek,mt6779-camsys", "syscon"
|
||||
- "mediatek,mt8183-camsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ Required Properties:
|
|||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-imgsys", "syscon"
|
||||
- "mediatek,mt2712-imgsys", "syscon"
|
||||
- "mediatek,mt6765-imgsys", "syscon"
|
||||
- "mediatek,mt6779-imgsys", "syscon"
|
||||
- "mediatek,mt6797-imgsys", "syscon"
|
||||
- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ Required Properties:
|
|||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-infracfg", "syscon"
|
||||
- "mediatek,mt2712-infracfg", "syscon"
|
||||
- "mediatek,mt6765-infracfg", "syscon"
|
||||
- "mediatek,mt6779-infracfg_ao", "syscon"
|
||||
- "mediatek,mt6797-infracfg", "syscon"
|
||||
- "mediatek,mt7622-infracfg", "syscon"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,28 @@
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|||
Mediatek mipi0a (mipi_rx_ana_csi0a) controller
|
||||
============================
|
||||
|
||||
The Mediatek mipi0a controller provides various clocks
|
||||
to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6765-mipi0a", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The mipi0a controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
The mipi0a controller also uses the common power domain from
|
||||
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||
The available power doamins are defined in dt-bindings/power/mt*-power.h.
|
||||
|
||||
Example:
|
||||
|
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mipi0a: clock-controller@11c10000 {
|
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compatible = "mediatek,mt6765-mipi0a", "syscon";
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reg = <0 0x11c10000 0 0x1000>;
|
||||
power-domains = <&scpsys MT6765_POWER_DOMAIN_CAM>;
|
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#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -8,6 +8,7 @@ Required Properties:
|
|||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-mmsys", "syscon"
|
||||
- "mediatek,mt2712-mmsys", "syscon"
|
||||
- "mediatek,mt6765-mmsys", "syscon"
|
||||
- "mediatek,mt6779-mmsys", "syscon"
|
||||
- "mediatek,mt6797-mmsys", "syscon"
|
||||
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ Required Properties:
|
|||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-pericfg", "syscon"
|
||||
- "mediatek,mt2712-pericfg", "syscon"
|
||||
- "mediatek,mt6765-pericfg", "syscon"
|
||||
- "mediatek,mt7622-pericfg", "syscon"
|
||||
- "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"
|
||||
- "mediatek,mt7629-pericfg", "syscon"
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ Required Properties:
|
|||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-topckgen"
|
||||
- "mediatek,mt2712-topckgen", "syscon"
|
||||
- "mediatek,mt6765-topckgen", "syscon"
|
||||
- "mediatek,mt6779-topckgen", "syscon"
|
||||
- "mediatek,mt6797-topckgen"
|
||||
- "mediatek,mt7622-topckgen"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
Mediatek vcodecsys controller
|
||||
============================
|
||||
|
||||
The Mediatek vcodecsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6765-vcodecsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vcodecsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
The vcodecsys controller also uses the common power domain from
|
||||
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||
The available power doamins are defined in dt-bindings/power/mt*-power.h.
|
||||
|
||||
Example:
|
||||
|
||||
venc_gcon: clock-controller@17000000 {
|
||||
compatible = "mediatek,mt6765-vcodecsys", "syscon";
|
||||
reg = <0 0x17000000 0 0x10000>;
|
||||
power-domains = <&scpsys MT6765_POWER_DOMAIN_VCODEC>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
188
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml
Normal file
188
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml
Normal file
|
|
@ -0,0 +1,188 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Baikal-T1 Clock Control Unit Dividers
|
||||
|
||||
maintainers:
|
||||
- Serge Semin <fancer.lancer@gmail.com>
|
||||
|
||||
description: |
|
||||
Clocks Control Unit is the core of Baikal-T1 SoC System Controller
|
||||
responsible for the chip subsystems clocking and resetting. The CCU is
|
||||
connected with an external fixed rate oscillator, which signal is transformed
|
||||
into clocks of various frequencies and then propagated to either individual
|
||||
IP-blocks or to groups of blocks (clock domains). The transformation is done
|
||||
by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
|
||||
later ones are described in this binding. Each clock domain can be also
|
||||
individually reset by using the domain clocks divider configuration
|
||||
registers. Baikal-T1 CCU is logically divided into the next components:
|
||||
1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
|
||||
in general can provide any frequency supported by the CCU PLLs).
|
||||
2) PLLs clocks generators (PLLs).
|
||||
3) AXI-bus clock dividers (AXI) - described in this binding file.
|
||||
4) System devices reference clock dividers (SYS) - described in this binding
|
||||
file.
|
||||
which are connected with each other as shown on the next figure:
|
||||
|
||||
+---------------+
|
||||
| Baikal-T1 CCU |
|
||||
| +----+------|- MIPS P5600 cores
|
||||
| +-|PLLs|------|- DDR controller
|
||||
| | +----+ |
|
||||
+----+ | | | | |
|
||||
|XTAL|--|-+ | | +---+-|
|
||||
+----+ | | | +-|AXI|-|- AXI-bus
|
||||
| | | +---+-|
|
||||
| | | |
|
||||
| | +----+---+-|- APB-bus
|
||||
| +-------|SYS|-|- Low-speed Devices
|
||||
| +---+-|- High-speed Devices
|
||||
+---------------+
|
||||
|
||||
Each sub-block is represented as a separate DT node and has an individual
|
||||
driver to be bound with.
|
||||
|
||||
In order to create signals of wide range frequencies the external oscillator
|
||||
output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
|
||||
then passed over CCU dividers to create signals required for the target clock
|
||||
domain (like AXI-bus or System Device consumers). The dividers have the
|
||||
following structure:
|
||||
|
||||
+--------------+
|
||||
CLKIN --|->+----+ 1|\ |
|
||||
SETCLK--|--|/DIV|->| | |
|
||||
CLKDIV--|--| | | |-|->CLKLOUT
|
||||
LOCK----|--+----+ | | |
|
||||
| |/ |
|
||||
| | |
|
||||
EN------|-----------+ |
|
||||
RST-----|--------------|->RSTOUT
|
||||
+--------------+
|
||||
|
||||
where CLKIN is the reference clock coming either from CCU PLLs or from an
|
||||
external clock oscillator, SETCLK - a command to update the output clock in
|
||||
accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
|
||||
the output clock stabilization, EN - enable/disable the divider block,
|
||||
RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core
|
||||
peculiarities the dividers may lack of some functionality depicted on the
|
||||
figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
|
||||
clock provider just doesn't expose either switching functions, or the rate
|
||||
configuration, or both of them.
|
||||
|
||||
The clock dividers, which output clock is then consumed by the SoC individual
|
||||
devices, are united into a single clocks provider called System Devices CCU.
|
||||
Similarly the dividers with output clocks utilized as AXI-bus reference clocks
|
||||
are called AXI-bus CCU. Both of them use the common clock bindings with no
|
||||
custom properties. The list of exported clocks and reset signals can be found
|
||||
in the files: 'include/dt-bindings/clock/bt1-ccu.h' and
|
||||
'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
|
||||
are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
|
||||
to be a children of later one.
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: baikal,bt1-ccu-axi
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: CCU SATA PLL output clock
|
||||
- description: CCU PCIe PLL output clock
|
||||
- description: CCU Ethernet PLL output clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: sata_clk
|
||||
- const: pcie_clk
|
||||
- const: eth_clk
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock
|
||||
- description: CCU SATA PLL output clock
|
||||
- description: CCU PCIe PLL output clock
|
||||
- description: CCU Ethernet PLL output clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref_clk
|
||||
- const: sata_clk
|
||||
- const: pcie_clk
|
||||
- const: eth_clk
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- baikal,bt1-ccu-axi
|
||||
- baikal,bt1-ccu-sys
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
# AXI-bus Clock Control Unit node:
|
||||
- |
|
||||
#include <dt-bindings/clock/bt1-ccu.h>
|
||||
|
||||
clock-controller@1f04d030 {
|
||||
compatible = "baikal,bt1-ccu-axi";
|
||||
reg = <0x1f04d030 0x030>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
clocks = <&ccu_pll CCU_SATA_PLL>,
|
||||
<&ccu_pll CCU_PCIE_PLL>,
|
||||
<&ccu_pll CCU_ETH_PLL>;
|
||||
clock-names = "sata_clk", "pcie_clk", "eth_clk";
|
||||
};
|
||||
# System Devices Clock Control Unit node:
|
||||
- |
|
||||
#include <dt-bindings/clock/bt1-ccu.h>
|
||||
|
||||
clock-controller@1f04d060 {
|
||||
compatible = "baikal,bt1-ccu-sys";
|
||||
reg = <0x1f04d060 0x0a0>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
clocks = <&clk25m>,
|
||||
<&ccu_pll CCU_SATA_PLL>,
|
||||
<&ccu_pll CCU_PCIE_PLL>,
|
||||
<&ccu_pll CCU_ETH_PLL>;
|
||||
clock-names = "ref_clk", "sata_clk", "pcie_clk",
|
||||
"eth_clk";
|
||||
};
|
||||
# Required Clock Control Unit PLL node:
|
||||
- |
|
||||
ccu_pll: clock-controller@1f04d000 {
|
||||
compatible = "baikal,bt1-ccu-pll";
|
||||
reg = <0x1f04d000 0x028>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&clk25m>;
|
||||
clock-names = "ref_clk";
|
||||
};
|
||||
...
|
||||
131
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
Normal file
131
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Baikal-T1 Clock Control Unit PLL
|
||||
|
||||
maintainers:
|
||||
- Serge Semin <fancer.lancer@gmail.com>
|
||||
|
||||
description: |
|
||||
Clocks Control Unit is the core of Baikal-T1 SoC System Controller
|
||||
responsible for the chip subsystems clocking and resetting. The CCU is
|
||||
connected with an external fixed rate oscillator, which signal is transformed
|
||||
into clocks of various frequencies and then propagated to either individual
|
||||
IP-blocks or to groups of blocks (clock domains). The transformation is done
|
||||
by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
|
||||
It's logically divided into the next components:
|
||||
1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
|
||||
in general can provide any frequency supported by the CCU PLLs).
|
||||
2) PLLs clocks generators (PLLs) - described in this binding file.
|
||||
3) AXI-bus clock dividers (AXI).
|
||||
4) System devices reference clock dividers (SYS).
|
||||
which are connected with each other as shown on the next figure:
|
||||
|
||||
+---------------+
|
||||
| Baikal-T1 CCU |
|
||||
| +----+------|- MIPS P5600 cores
|
||||
| +-|PLLs|------|- DDR controller
|
||||
| | +----+ |
|
||||
+----+ | | | | |
|
||||
|XTAL|--|-+ | | +---+-|
|
||||
+----+ | | | +-|AXI|-|- AXI-bus
|
||||
| | | +---+-|
|
||||
| | | |
|
||||
| | +----+---+-|- APB-bus
|
||||
| +-------|SYS|-|- Low-speed Devices
|
||||
| +---+-|- High-speed Devices
|
||||
+---------------+
|
||||
|
||||
Each CCU sub-block is represented as a separate dts-node and has an
|
||||
individual driver to be bound with.
|
||||
|
||||
In order to create signals of wide range frequencies the external oscillator
|
||||
output is primarily connected to a set of CCU PLLs. There are five PLLs
|
||||
to create a clock for the MIPS P5600 cores, the embedded DDR controller,
|
||||
SATA, Ethernet and PCIe domains. The last three domains though named by the
|
||||
biggest system interfaces in fact include nearly all of the rest SoC
|
||||
peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
|
||||
with an interface wrapper (so called safe PLL' clocks switcher) to simplify
|
||||
the PLL configuration procedure. The PLLs work as depicted on the next
|
||||
diagram:
|
||||
|
||||
+--------------------------+
|
||||
| |
|
||||
+-->+---+ +---+ +---+ | +---+ 0|\
|
||||
CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
|
||||
+---+ +->+---+ +---+ /->+---+ | |--->CLKOUT
|
||||
CLKOD---------C----------------+ 1| |
|
||||
+--------C--------------------------->|/
|
||||
| | ^
|
||||
Rclk-+->+---+ | |
|
||||
CLKR--->|/NR|-+ |
|
||||
+---+ |
|
||||
BYPASS--------------------------------------+
|
||||
BWADJ--->
|
||||
|
||||
where Rclk is the reference clock coming from XTAL, NR - reference clock
|
||||
divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
|
||||
output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
|
||||
the binding supports the PLL dividers configuration in accordance with a
|
||||
requested rate, while bypassing and bandwidth adjustment settings can be
|
||||
added in future if it gets to be necessary.
|
||||
|
||||
The PLLs CLKOUT is then either directly connected with the corresponding
|
||||
clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
|
||||
divider to create a signal required for the clock domain.
|
||||
|
||||
The CCU PLL dts-node uses the common clock bindings with no custom
|
||||
parameters. The list of exported clocks can be found in
|
||||
'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
|
||||
Baikal-T1 SoC System Controller its DT node is supposed to be a child of
|
||||
later one.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: baikal,bt1-ccu-pll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
description: External reference clock
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: ref_clk
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
# Clock Control Unit PLL node:
|
||||
- |
|
||||
clock-controller@1f04d000 {
|
||||
compatible = "baikal,bt1-ccu-pll";
|
||||
reg = <0x1f04d000 0x028>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&clk25m>;
|
||||
clock-names = "ref_clk";
|
||||
};
|
||||
# Required external oscillator:
|
||||
- |
|
||||
clk25m: clock-oscillator-25m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "clk25m";
|
||||
};
|
||||
...
|
||||
|
|
@ -12,6 +12,7 @@ Required properties:
|
|||
"idt,5p49v5933"
|
||||
"idt,5p49v5935"
|
||||
"idt,5p49v6901"
|
||||
"idt,5p49v6965"
|
||||
- reg: i2c device address, shall be 0x68 or 0x6a.
|
||||
- #clock-cells: from common clock binding; shall be set to 1.
|
||||
- clocks: from common clock binding; list of parent clock handles,
|
||||
|
|
|
|||
|
|
@ -362,6 +362,7 @@ config COMMON_CLK_FIXED_MMIO
|
|||
|
||||
source "drivers/clk/actions/Kconfig"
|
||||
source "drivers/clk/analogbits/Kconfig"
|
||||
source "drivers/clk/baikal-t1/Kconfig"
|
||||
source "drivers/clk/bcm/Kconfig"
|
||||
source "drivers/clk/hisilicon/Kconfig"
|
||||
source "drivers/clk/imgtec/Kconfig"
|
||||
|
|
|
|||
|
|
@ -75,6 +75,7 @@ obj-y += analogbits/
|
|||
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
|
||||
obj-$(CONFIG_ARCH_ARTPEC) += axis/
|
||||
obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
|
||||
obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/
|
||||
obj-y += bcm/
|
||||
obj-$(CONFIG_ARCH_BERLIN) += berlin/
|
||||
obj-$(CONFIG_ARCH_DAVINCI) += davinci/
|
||||
|
|
|
|||
42
drivers/clk/baikal-t1/Kconfig
Normal file
42
drivers/clk/baikal-t1/Kconfig
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
config CLK_BAIKAL_T1
|
||||
bool "Baikal-T1 Clocks Control Unit interface"
|
||||
depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST
|
||||
default MIPS_BAIKAL_T1
|
||||
help
|
||||
Clocks Control Unit is the core of Baikal-T1 SoC System Controller
|
||||
responsible for the chip subsystems clocking and resetting. It
|
||||
consists of multiple global clock domains, which can be reset by
|
||||
means of the CCU control registers. These domains and devices placed
|
||||
in them are fed with clocks generated by a hierarchy of PLLs,
|
||||
configurable and fixed clock dividers. Enable this option to be able
|
||||
to select Baikal-T1 CCU PLLs and Dividers drivers.
|
||||
|
||||
if CLK_BAIKAL_T1
|
||||
|
||||
config CLK_BT1_CCU_PLL
|
||||
bool "Baikal-T1 CCU PLLs support"
|
||||
select MFD_SYSCON
|
||||
default MIPS_BAIKAL_T1
|
||||
help
|
||||
Enable this to support the PLLs embedded into the Baikal-T1 SoC
|
||||
System Controller. These are five PLLs placed at the root of the
|
||||
clocks hierarchy, right after an external reference oscillator
|
||||
(normally of 25MHz). They are used to generate high frequency
|
||||
signals, which are either directly wired to the consumers (like
|
||||
CPUs, DDR, etc.) or passed over the clock dividers to be only
|
||||
then used as an individual reference clock of a target device.
|
||||
|
||||
config CLK_BT1_CCU_DIV
|
||||
bool "Baikal-T1 CCU Dividers support"
|
||||
select RESET_CONTROLLER
|
||||
select MFD_SYSCON
|
||||
default MIPS_BAIKAL_T1
|
||||
help
|
||||
Enable this to support the CCU dividers used to distribute clocks
|
||||
between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
|
||||
SoC. CCU dividers can be either configurable or with fixed divider,
|
||||
either gateable or ungateable. Some of the CCU dividers can be as well
|
||||
used to reset the domains they're supplying clock to.
|
||||
|
||||
endif
|
||||
3
drivers/clk/baikal-t1/Makefile
Normal file
3
drivers/clk/baikal-t1/Makefile
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-$(CONFIG_CLK_BT1_CCU_PLL) += ccu-pll.o clk-ccu-pll.o
|
||||
obj-$(CONFIG_CLK_BT1_CCU_DIV) += ccu-div.o clk-ccu-div.o
|
||||
602
drivers/clk/baikal-t1/ccu-div.c
Normal file
602
drivers/clk/baikal-t1/ccu-div.c
Normal file
|
|
@ -0,0 +1,602 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
*
|
||||
* Authors:
|
||||
* Serge Semin <Sergey.Semin@baikalelectronics.ru>
|
||||
* Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
|
||||
*
|
||||
* Baikal-T1 CCU Dividers interface driver
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "bt1-ccu-div: " fmt
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/bits.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/time64.h>
|
||||
#include <linux/debugfs.h>
|
||||
|
||||
#include "ccu-div.h"
|
||||
|
||||
#define CCU_DIV_CTL 0x00
|
||||
#define CCU_DIV_CTL_EN BIT(0)
|
||||
#define CCU_DIV_CTL_RST BIT(1)
|
||||
#define CCU_DIV_CTL_SET_CLKDIV BIT(2)
|
||||
#define CCU_DIV_CTL_CLKDIV_FLD 4
|
||||
#define CCU_DIV_CTL_CLKDIV_MASK(_width) \
|
||||
GENMASK((_width) + CCU_DIV_CTL_CLKDIV_FLD - 1, CCU_DIV_CTL_CLKDIV_FLD)
|
||||
#define CCU_DIV_CTL_LOCK_SHIFTED BIT(27)
|
||||
#define CCU_DIV_CTL_LOCK_NORMAL BIT(31)
|
||||
|
||||
#define CCU_DIV_RST_DELAY_US 1
|
||||
#define CCU_DIV_LOCK_CHECK_RETRIES 50
|
||||
|
||||
#define CCU_DIV_CLKDIV_MIN 0
|
||||
#define CCU_DIV_CLKDIV_MAX(_mask) \
|
||||
((_mask) >> CCU_DIV_CTL_CLKDIV_FLD)
|
||||
|
||||
/*
|
||||
* Use the next two methods until there are generic field setter and
|
||||
* getter available with non-constant mask support.
|
||||
*/
|
||||
static inline u32 ccu_div_get(u32 mask, u32 val)
|
||||
{
|
||||
return (val & mask) >> CCU_DIV_CTL_CLKDIV_FLD;
|
||||
}
|
||||
|
||||
static inline u32 ccu_div_prep(u32 mask, u32 val)
|
||||
{
|
||||
return (val << CCU_DIV_CTL_CLKDIV_FLD) & mask;
|
||||
}
|
||||
|
||||
static inline unsigned long ccu_div_lock_delay_ns(unsigned long ref_clk,
|
||||
unsigned long div)
|
||||
{
|
||||
u64 ns = 4ULL * (div ?: 1) * NSEC_PER_SEC;
|
||||
|
||||
do_div(ns, ref_clk);
|
||||
|
||||
return ns;
|
||||
}
|
||||
|
||||
static inline unsigned long ccu_div_calc_freq(unsigned long ref_clk,
|
||||
unsigned long div)
|
||||
{
|
||||
return ref_clk / (div ?: 1);
|
||||
}
|
||||
|
||||
static int ccu_div_var_update_clkdiv(struct ccu_div *div,
|
||||
unsigned long parent_rate,
|
||||
unsigned long divider)
|
||||
{
|
||||
unsigned long nd;
|
||||
u32 val = 0;
|
||||
u32 lock;
|
||||
int count;
|
||||
|
||||
nd = ccu_div_lock_delay_ns(parent_rate, divider);
|
||||
|
||||
if (div->features & CCU_DIV_LOCK_SHIFTED)
|
||||
lock = CCU_DIV_CTL_LOCK_SHIFTED;
|
||||
else
|
||||
lock = CCU_DIV_CTL_LOCK_NORMAL;
|
||||
|
||||
regmap_update_bits(div->sys_regs, div->reg_ctl,
|
||||
CCU_DIV_CTL_SET_CLKDIV, CCU_DIV_CTL_SET_CLKDIV);
|
||||
|
||||
/*
|
||||
* Until there is nsec-version of readl_poll_timeout() is available
|
||||
* we have to implement the next polling loop.
|
||||
*/
|
||||
count = CCU_DIV_LOCK_CHECK_RETRIES;
|
||||
do {
|
||||
ndelay(nd);
|
||||
regmap_read(div->sys_regs, div->reg_ctl, &val);
|
||||
if (val & lock)
|
||||
return 0;
|
||||
} while (--count);
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static int ccu_div_var_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_hw *parent_hw = clk_hw_get_parent(hw);
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
unsigned long flags;
|
||||
u32 val = 0;
|
||||
int ret;
|
||||
|
||||
if (!parent_hw) {
|
||||
pr_err("Can't enable '%s' with no parent", clk_hw_get_name(hw));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_read(div->sys_regs, div->reg_ctl, &val);
|
||||
if (val & CCU_DIV_CTL_EN)
|
||||
return 0;
|
||||
|
||||
spin_lock_irqsave(&div->lock, flags);
|
||||
ret = ccu_div_var_update_clkdiv(div, clk_hw_get_rate(parent_hw),
|
||||
ccu_div_get(div->mask, val));
|
||||
if (!ret)
|
||||
regmap_update_bits(div->sys_regs, div->reg_ctl,
|
||||
CCU_DIV_CTL_EN, CCU_DIV_CTL_EN);
|
||||
spin_unlock_irqrestore(&div->lock, flags);
|
||||
if (ret)
|
||||
pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ccu_div_gate_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&div->lock, flags);
|
||||
regmap_update_bits(div->sys_regs, div->reg_ctl,
|
||||
CCU_DIV_CTL_EN, CCU_DIV_CTL_EN);
|
||||
spin_unlock_irqrestore(&div->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ccu_div_gate_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&div->lock, flags);
|
||||
regmap_update_bits(div->sys_regs, div->reg_ctl, CCU_DIV_CTL_EN, 0);
|
||||
spin_unlock_irqrestore(&div->lock, flags);
|
||||
}
|
||||
|
||||
static int ccu_div_gate_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
u32 val = 0;
|
||||
|
||||
regmap_read(div->sys_regs, div->reg_ctl, &val);
|
||||
|
||||
return !!(val & CCU_DIV_CTL_EN);
|
||||
}
|
||||
|
||||
static unsigned long ccu_div_var_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
unsigned long divider;
|
||||
u32 val = 0;
|
||||
|
||||
regmap_read(div->sys_regs, div->reg_ctl, &val);
|
||||
divider = ccu_div_get(div->mask, val);
|
||||
|
||||
return ccu_div_calc_freq(parent_rate, divider);
|
||||
}
|
||||
|
||||
static inline unsigned long ccu_div_var_calc_divider(unsigned long rate,
|
||||
unsigned long parent_rate,
|
||||
unsigned int mask)
|
||||
{
|
||||
unsigned long divider;
|
||||
|
||||
divider = parent_rate / rate;
|
||||
return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN,
|
||||
CCU_DIV_CLKDIV_MAX(mask));
|
||||
}
|
||||
|
||||
static long ccu_div_var_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
unsigned long divider;
|
||||
|
||||
divider = ccu_div_var_calc_divider(rate, *parent_rate, div->mask);
|
||||
|
||||
return ccu_div_calc_freq(*parent_rate, divider);
|
||||
}
|
||||
|
||||
/*
|
||||
* This method is used for the clock divider blocks, which support the
|
||||
* on-the-fly rate change. So due to lacking the EN bit functionality
|
||||
* they can't be gated before the rate adjustment.
|
||||
*/
|
||||
static int ccu_div_var_set_rate_slow(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
unsigned long flags, divider;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
|
||||
if (divider == 1 && div->features & CCU_DIV_SKIP_ONE) {
|
||||
divider = 0;
|
||||
} else if (div->features & CCU_DIV_SKIP_ONE_TO_THREE) {
|
||||
if (divider == 1 || divider == 2)
|
||||
divider = 0;
|
||||
else if (divider == 3)
|
||||
divider = 4;
|
||||
}
|
||||
|
||||
val = ccu_div_prep(div->mask, divider);
|
||||
|
||||
spin_lock_irqsave(&div->lock, flags);
|
||||
regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, val);
|
||||
ret = ccu_div_var_update_clkdiv(div, parent_rate, divider);
|
||||
spin_unlock_irqrestore(&div->lock, flags);
|
||||
if (ret)
|
||||
pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* This method is used for the clock divider blocks, which don't support
|
||||
* the on-the-fly rate change.
|
||||
*/
|
||||
static int ccu_div_var_set_rate_fast(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
unsigned long flags, divider = 1;
|
||||
u32 val;
|
||||
|
||||
divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
|
||||
val = ccu_div_prep(div->mask, divider);
|
||||
|
||||
/*
|
||||
* Also disable the clock divider block if it was enabled by default
|
||||
* or by the bootloader.
|
||||
*/
|
||||
spin_lock_irqsave(&div->lock, flags);
|
||||
regmap_update_bits(div->sys_regs, div->reg_ctl,
|
||||
div->mask | CCU_DIV_CTL_EN, val);
|
||||
spin_unlock_irqrestore(&div->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long ccu_div_fixed_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
|
||||
return ccu_div_calc_freq(parent_rate, div->divider);
|
||||
}
|
||||
|
||||
static long ccu_div_fixed_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
|
||||
return ccu_div_calc_freq(*parent_rate, div->divider);
|
||||
}
|
||||
|
||||
static int ccu_div_fixed_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ccu_div_reset_domain(struct ccu_div *div)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (!div || !(div->features & CCU_DIV_RESET_DOMAIN))
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&div->lock, flags);
|
||||
regmap_update_bits(div->sys_regs, div->reg_ctl,
|
||||
CCU_DIV_CTL_RST, CCU_DIV_CTL_RST);
|
||||
spin_unlock_irqrestore(&div->lock, flags);
|
||||
|
||||
/* The next delay must be enough to cover all the resets. */
|
||||
udelay(CCU_DIV_RST_DELAY_US);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
struct ccu_div_dbgfs_bit {
|
||||
struct ccu_div *div;
|
||||
const char *name;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
#define CCU_DIV_DBGFS_BIT_ATTR(_name, _mask) { \
|
||||
.name = _name, \
|
||||
.mask = _mask \
|
||||
}
|
||||
|
||||
static const struct ccu_div_dbgfs_bit ccu_div_bits[] = {
|
||||
CCU_DIV_DBGFS_BIT_ATTR("div_en", CCU_DIV_CTL_EN),
|
||||
CCU_DIV_DBGFS_BIT_ATTR("div_rst", CCU_DIV_CTL_RST),
|
||||
CCU_DIV_DBGFS_BIT_ATTR("div_bypass", CCU_DIV_CTL_SET_CLKDIV),
|
||||
CCU_DIV_DBGFS_BIT_ATTR("div_lock", CCU_DIV_CTL_LOCK_NORMAL)
|
||||
};
|
||||
|
||||
#define CCU_DIV_DBGFS_BIT_NUM ARRAY_SIZE(ccu_div_bits)
|
||||
|
||||
/*
|
||||
* It can be dangerous to change the Divider settings behind clock framework
|
||||
* back, therefore we don't provide any kernel config based compile time option
|
||||
* for this feature to enable.
|
||||
*/
|
||||
#undef CCU_DIV_ALLOW_WRITE_DEBUGFS
|
||||
#ifdef CCU_DIV_ALLOW_WRITE_DEBUGFS
|
||||
|
||||
static int ccu_div_dbgfs_bit_set(void *priv, u64 val)
|
||||
{
|
||||
const struct ccu_div_dbgfs_bit *bit = priv;
|
||||
struct ccu_div *div = bit->div;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&div->lock, flags);
|
||||
regmap_update_bits(div->sys_regs, div->reg_ctl,
|
||||
bit->mask, val ? bit->mask : 0);
|
||||
spin_unlock_irqrestore(&div->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ccu_div_dbgfs_var_clkdiv_set(void *priv, u64 val)
|
||||
{
|
||||
struct ccu_div *div = priv;
|
||||
unsigned long flags;
|
||||
u32 data;
|
||||
|
||||
val = clamp_t(u64, val, CCU_DIV_CLKDIV_MIN,
|
||||
CCU_DIV_CLKDIV_MAX(div->mask));
|
||||
data = ccu_div_prep(div->mask, val);
|
||||
|
||||
spin_lock_irqsave(&div->lock, flags);
|
||||
regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, data);
|
||||
spin_unlock_irqrestore(&div->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define ccu_div_dbgfs_mode 0644
|
||||
|
||||
#else /* !CCU_DIV_ALLOW_WRITE_DEBUGFS */
|
||||
|
||||
#define ccu_div_dbgfs_bit_set NULL
|
||||
#define ccu_div_dbgfs_var_clkdiv_set NULL
|
||||
#define ccu_div_dbgfs_mode 0444
|
||||
|
||||
#endif /* !CCU_DIV_ALLOW_WRITE_DEBUGFS */
|
||||
|
||||
static int ccu_div_dbgfs_bit_get(void *priv, u64 *val)
|
||||
{
|
||||
const struct ccu_div_dbgfs_bit *bit = priv;
|
||||
struct ccu_div *div = bit->div;
|
||||
u32 data = 0;
|
||||
|
||||
regmap_read(div->sys_regs, div->reg_ctl, &data);
|
||||
*val = !!(data & bit->mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_bit_fops,
|
||||
ccu_div_dbgfs_bit_get, ccu_div_dbgfs_bit_set, "%llu\n");
|
||||
|
||||
static int ccu_div_dbgfs_var_clkdiv_get(void *priv, u64 *val)
|
||||
{
|
||||
struct ccu_div *div = priv;
|
||||
u32 data = 0;
|
||||
|
||||
regmap_read(div->sys_regs, div->reg_ctl, &data);
|
||||
*val = ccu_div_get(div->mask, data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_var_clkdiv_fops,
|
||||
ccu_div_dbgfs_var_clkdiv_get, ccu_div_dbgfs_var_clkdiv_set, "%llu\n");
|
||||
|
||||
static int ccu_div_dbgfs_fixed_clkdiv_get(void *priv, u64 *val)
|
||||
{
|
||||
struct ccu_div *div = priv;
|
||||
|
||||
*val = div->divider;
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_fixed_clkdiv_fops,
|
||||
ccu_div_dbgfs_fixed_clkdiv_get, NULL, "%llu\n");
|
||||
|
||||
static void ccu_div_var_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
struct ccu_div_dbgfs_bit *bits;
|
||||
int didx, bidx, num = 2;
|
||||
const char *name;
|
||||
|
||||
num += !!(div->flags & CLK_SET_RATE_GATE) +
|
||||
!!(div->features & CCU_DIV_RESET_DOMAIN);
|
||||
|
||||
bits = kcalloc(num, sizeof(*bits), GFP_KERNEL);
|
||||
if (!bits)
|
||||
return;
|
||||
|
||||
for (didx = 0, bidx = 0; bidx < CCU_DIV_DBGFS_BIT_NUM; ++bidx) {
|
||||
name = ccu_div_bits[bidx].name;
|
||||
if (!(div->flags & CLK_SET_RATE_GATE) &&
|
||||
!strcmp("div_en", name)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!(div->features & CCU_DIV_RESET_DOMAIN) &&
|
||||
!strcmp("div_rst", name)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
bits[didx] = ccu_div_bits[bidx];
|
||||
bits[didx].div = div;
|
||||
|
||||
if (div->features & CCU_DIV_LOCK_SHIFTED &&
|
||||
!strcmp("div_lock", name)) {
|
||||
bits[didx].mask = CCU_DIV_CTL_LOCK_SHIFTED;
|
||||
}
|
||||
|
||||
debugfs_create_file_unsafe(bits[didx].name, ccu_div_dbgfs_mode,
|
||||
dentry, &bits[didx],
|
||||
&ccu_div_dbgfs_bit_fops);
|
||||
++didx;
|
||||
}
|
||||
|
||||
debugfs_create_file_unsafe("div_clkdiv", ccu_div_dbgfs_mode, dentry,
|
||||
div, &ccu_div_dbgfs_var_clkdiv_fops);
|
||||
}
|
||||
|
||||
static void ccu_div_gate_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
struct ccu_div_dbgfs_bit *bit;
|
||||
|
||||
bit = kmalloc(sizeof(*bit), GFP_KERNEL);
|
||||
if (!bit)
|
||||
return;
|
||||
|
||||
*bit = ccu_div_bits[0];
|
||||
bit->div = div;
|
||||
debugfs_create_file_unsafe(bit->name, ccu_div_dbgfs_mode, dentry, bit,
|
||||
&ccu_div_dbgfs_bit_fops);
|
||||
|
||||
debugfs_create_file_unsafe("div_clkdiv", 0400, dentry, div,
|
||||
&ccu_div_dbgfs_fixed_clkdiv_fops);
|
||||
}
|
||||
|
||||
static void ccu_div_fixed_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
|
||||
debugfs_create_file_unsafe("div_clkdiv", 0400, dentry, div,
|
||||
&ccu_div_dbgfs_fixed_clkdiv_fops);
|
||||
}
|
||||
|
||||
#else /* !CONFIG_DEBUG_FS */
|
||||
|
||||
#define ccu_div_var_debug_init NULL
|
||||
#define ccu_div_gate_debug_init NULL
|
||||
#define ccu_div_fixed_debug_init NULL
|
||||
|
||||
#endif /* !CONFIG_DEBUG_FS */
|
||||
|
||||
static const struct clk_ops ccu_div_var_gate_to_set_ops = {
|
||||
.enable = ccu_div_var_enable,
|
||||
.disable = ccu_div_gate_disable,
|
||||
.is_enabled = ccu_div_gate_is_enabled,
|
||||
.recalc_rate = ccu_div_var_recalc_rate,
|
||||
.round_rate = ccu_div_var_round_rate,
|
||||
.set_rate = ccu_div_var_set_rate_fast,
|
||||
.debug_init = ccu_div_var_debug_init
|
||||
};
|
||||
|
||||
static const struct clk_ops ccu_div_var_nogate_ops = {
|
||||
.recalc_rate = ccu_div_var_recalc_rate,
|
||||
.round_rate = ccu_div_var_round_rate,
|
||||
.set_rate = ccu_div_var_set_rate_slow,
|
||||
.debug_init = ccu_div_var_debug_init
|
||||
};
|
||||
|
||||
static const struct clk_ops ccu_div_gate_ops = {
|
||||
.enable = ccu_div_gate_enable,
|
||||
.disable = ccu_div_gate_disable,
|
||||
.is_enabled = ccu_div_gate_is_enabled,
|
||||
.recalc_rate = ccu_div_fixed_recalc_rate,
|
||||
.round_rate = ccu_div_fixed_round_rate,
|
||||
.set_rate = ccu_div_fixed_set_rate,
|
||||
.debug_init = ccu_div_gate_debug_init
|
||||
};
|
||||
|
||||
static const struct clk_ops ccu_div_fixed_ops = {
|
||||
.recalc_rate = ccu_div_fixed_recalc_rate,
|
||||
.round_rate = ccu_div_fixed_round_rate,
|
||||
.set_rate = ccu_div_fixed_set_rate,
|
||||
.debug_init = ccu_div_fixed_debug_init
|
||||
};
|
||||
|
||||
struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init)
|
||||
{
|
||||
struct clk_parent_data parent_data = { };
|
||||
struct clk_init_data hw_init = { };
|
||||
struct ccu_div *div;
|
||||
int ret;
|
||||
|
||||
if (!div_init)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
||||
if (!div)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
/*
|
||||
* Note since Baikal-T1 System Controller registers are MMIO-backed
|
||||
* we won't check the regmap IO operations return status, because it
|
||||
* must be zero anyway.
|
||||
*/
|
||||
div->hw.init = &hw_init;
|
||||
div->id = div_init->id;
|
||||
div->reg_ctl = div_init->base + CCU_DIV_CTL;
|
||||
div->sys_regs = div_init->sys_regs;
|
||||
div->flags = div_init->flags;
|
||||
div->features = div_init->features;
|
||||
spin_lock_init(&div->lock);
|
||||
|
||||
hw_init.name = div_init->name;
|
||||
hw_init.flags = div_init->flags;
|
||||
|
||||
if (div_init->type == CCU_DIV_VAR) {
|
||||
if (hw_init.flags & CLK_SET_RATE_GATE)
|
||||
hw_init.ops = &ccu_div_var_gate_to_set_ops;
|
||||
else
|
||||
hw_init.ops = &ccu_div_var_nogate_ops;
|
||||
div->mask = CCU_DIV_CTL_CLKDIV_MASK(div_init->width);
|
||||
} else if (div_init->type == CCU_DIV_GATE) {
|
||||
hw_init.ops = &ccu_div_gate_ops;
|
||||
div->divider = div_init->divider;
|
||||
} else if (div_init->type == CCU_DIV_FIXED) {
|
||||
hw_init.ops = &ccu_div_fixed_ops;
|
||||
div->divider = div_init->divider;
|
||||
} else {
|
||||
ret = -EINVAL;
|
||||
goto err_free_div;
|
||||
}
|
||||
|
||||
if (!div_init->parent_name) {
|
||||
ret = -EINVAL;
|
||||
goto err_free_div;
|
||||
}
|
||||
parent_data.fw_name = div_init->parent_name;
|
||||
hw_init.parent_data = &parent_data;
|
||||
hw_init.num_parents = 1;
|
||||
|
||||
ret = of_clk_hw_register(div_init->np, &div->hw);
|
||||
if (ret)
|
||||
goto err_free_div;
|
||||
|
||||
return div;
|
||||
|
||||
err_free_div:
|
||||
kfree(div);
|
||||
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
void ccu_div_hw_unregister(struct ccu_div *div)
|
||||
{
|
||||
clk_hw_unregister(&div->hw);
|
||||
|
||||
kfree(div);
|
||||
}
|
||||
110
drivers/clk/baikal-t1/ccu-div.h
Normal file
110
drivers/clk/baikal-t1/ccu-div.h
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
*
|
||||
* Baikal-T1 CCU Dividers interface driver
|
||||
*/
|
||||
#ifndef __CLK_BT1_CCU_DIV_H__
|
||||
#define __CLK_BT1_CCU_DIV_H__
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/bits.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
/*
|
||||
* CCU Divider private flags
|
||||
* @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
|
||||
* It can be 0 though, which is functionally the same.
|
||||
* @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
|
||||
* It can be either 0 or greater than 3.
|
||||
* @CCU_DIV_LOCK_SHIFTED: Find lock-bit at non-standard position.
|
||||
* @CCU_DIV_RESET_DOMAIN: Provide reset clock domain method.
|
||||
*/
|
||||
#define CCU_DIV_SKIP_ONE BIT(1)
|
||||
#define CCU_DIV_SKIP_ONE_TO_THREE BIT(2)
|
||||
#define CCU_DIV_LOCK_SHIFTED BIT(3)
|
||||
#define CCU_DIV_RESET_DOMAIN BIT(4)
|
||||
|
||||
/*
|
||||
* enum ccu_div_type - CCU Divider types
|
||||
* @CCU_DIV_VAR: Clocks gate with variable divider.
|
||||
* @CCU_DIV_GATE: Clocks gate with fixed divider.
|
||||
* @CCU_DIV_FIXED: Ungateable clock with fixed divider.
|
||||
*/
|
||||
enum ccu_div_type {
|
||||
CCU_DIV_VAR,
|
||||
CCU_DIV_GATE,
|
||||
CCU_DIV_FIXED
|
||||
};
|
||||
|
||||
/*
|
||||
* struct ccu_div_init_data - CCU Divider initialization data
|
||||
* @id: Clocks private identifier.
|
||||
* @name: Clocks name.
|
||||
* @parent_name: Parent clocks name in a fw node.
|
||||
* @base: Divider register base address with respect to the sys_regs base.
|
||||
* @sys_regs: Baikal-T1 System Controller registers map.
|
||||
* @np: Pointer to the node describing the CCU Dividers.
|
||||
* @type: CCU divider type (variable, fixed with and without gate).
|
||||
* @width: Divider width if it's variable.
|
||||
* @divider: Divider fixed value.
|
||||
* @flags: CCU Divider clock flags.
|
||||
* @features: CCU Divider private features.
|
||||
*/
|
||||
struct ccu_div_init_data {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned int base;
|
||||
struct regmap *sys_regs;
|
||||
struct device_node *np;
|
||||
enum ccu_div_type type;
|
||||
union {
|
||||
unsigned int width;
|
||||
unsigned int divider;
|
||||
};
|
||||
unsigned long flags;
|
||||
unsigned long features;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct ccu_div - CCU Divider descriptor
|
||||
* @hw: clk_hw of the divider.
|
||||
* @id: Clock private identifier.
|
||||
* @reg_ctl: Divider control register base address.
|
||||
* @sys_regs: Baikal-T1 System Controller registers map.
|
||||
* @lock: Divider state change spin-lock.
|
||||
* @mask: Divider field mask.
|
||||
* @divider: Divider fixed value.
|
||||
* @flags: Divider clock flags.
|
||||
* @features: CCU Divider private features.
|
||||
*/
|
||||
struct ccu_div {
|
||||
struct clk_hw hw;
|
||||
unsigned int id;
|
||||
unsigned int reg_ctl;
|
||||
struct regmap *sys_regs;
|
||||
spinlock_t lock;
|
||||
union {
|
||||
u32 mask;
|
||||
unsigned int divider;
|
||||
};
|
||||
unsigned long flags;
|
||||
unsigned long features;
|
||||
};
|
||||
#define to_ccu_div(_hw) container_of(_hw, struct ccu_div, hw)
|
||||
|
||||
static inline struct clk_hw *ccu_div_get_clk_hw(struct ccu_div *div)
|
||||
{
|
||||
return div ? &div->hw : NULL;
|
||||
}
|
||||
|
||||
struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *init);
|
||||
|
||||
void ccu_div_hw_unregister(struct ccu_div *div);
|
||||
|
||||
int ccu_div_reset_domain(struct ccu_div *div);
|
||||
|
||||
#endif /* __CLK_BT1_CCU_DIV_H__ */
|
||||
558
drivers/clk/baikal-t1/ccu-pll.c
Normal file
558
drivers/clk/baikal-t1/ccu-pll.c
Normal file
|
|
@ -0,0 +1,558 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
*
|
||||
* Authors:
|
||||
* Serge Semin <Sergey.Semin@baikalelectronics.ru>
|
||||
* Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
|
||||
*
|
||||
* Baikal-T1 CCU PLL interface driver
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "bt1-ccu-pll: " fmt
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/limits.h>
|
||||
#include <linux/bits.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/time64.h>
|
||||
#include <linux/rational.h>
|
||||
#include <linux/debugfs.h>
|
||||
|
||||
#include "ccu-pll.h"
|
||||
|
||||
#define CCU_PLL_CTL 0x000
|
||||
#define CCU_PLL_CTL_EN BIT(0)
|
||||
#define CCU_PLL_CTL_RST BIT(1)
|
||||
#define CCU_PLL_CTL_CLKR_FLD 2
|
||||
#define CCU_PLL_CTL_CLKR_MASK GENMASK(7, CCU_PLL_CTL_CLKR_FLD)
|
||||
#define CCU_PLL_CTL_CLKF_FLD 8
|
||||
#define CCU_PLL_CTL_CLKF_MASK GENMASK(20, CCU_PLL_CTL_CLKF_FLD)
|
||||
#define CCU_PLL_CTL_CLKOD_FLD 21
|
||||
#define CCU_PLL_CTL_CLKOD_MASK GENMASK(24, CCU_PLL_CTL_CLKOD_FLD)
|
||||
#define CCU_PLL_CTL_BYPASS BIT(30)
|
||||
#define CCU_PLL_CTL_LOCK BIT(31)
|
||||
#define CCU_PLL_CTL1 0x004
|
||||
#define CCU_PLL_CTL1_BWADJ_FLD 3
|
||||
#define CCU_PLL_CTL1_BWADJ_MASK GENMASK(14, CCU_PLL_CTL1_BWADJ_FLD)
|
||||
|
||||
#define CCU_PLL_LOCK_CHECK_RETRIES 50
|
||||
|
||||
#define CCU_PLL_NR_MAX \
|
||||
((CCU_PLL_CTL_CLKR_MASK >> CCU_PLL_CTL_CLKR_FLD) + 1)
|
||||
#define CCU_PLL_NF_MAX \
|
||||
((CCU_PLL_CTL_CLKF_MASK >> (CCU_PLL_CTL_CLKF_FLD + 1)) + 1)
|
||||
#define CCU_PLL_OD_MAX \
|
||||
((CCU_PLL_CTL_CLKOD_MASK >> CCU_PLL_CTL_CLKOD_FLD) + 1)
|
||||
#define CCU_PLL_NB_MAX \
|
||||
((CCU_PLL_CTL1_BWADJ_MASK >> CCU_PLL_CTL1_BWADJ_FLD) + 1)
|
||||
#define CCU_PLL_FDIV_MIN 427000UL
|
||||
#define CCU_PLL_FDIV_MAX 3500000000UL
|
||||
#define CCU_PLL_FOUT_MIN 200000000UL
|
||||
#define CCU_PLL_FOUT_MAX 2500000000UL
|
||||
#define CCU_PLL_FVCO_MIN 700000000UL
|
||||
#define CCU_PLL_FVCO_MAX 3500000000UL
|
||||
#define CCU_PLL_CLKOD_FACTOR 2
|
||||
|
||||
static inline unsigned long ccu_pll_lock_delay_us(unsigned long ref_clk,
|
||||
unsigned long nr)
|
||||
{
|
||||
u64 us = 500ULL * nr * USEC_PER_SEC;
|
||||
|
||||
do_div(us, ref_clk);
|
||||
|
||||
return us;
|
||||
}
|
||||
|
||||
static inline unsigned long ccu_pll_calc_freq(unsigned long ref_clk,
|
||||
unsigned long nr,
|
||||
unsigned long nf,
|
||||
unsigned long od)
|
||||
{
|
||||
u64 tmp = ref_clk;
|
||||
|
||||
do_div(tmp, nr);
|
||||
tmp *= nf;
|
||||
do_div(tmp, od);
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk,
|
||||
unsigned long nr)
|
||||
{
|
||||
unsigned long ud, ut;
|
||||
u32 val;
|
||||
|
||||
ud = ccu_pll_lock_delay_us(ref_clk, nr);
|
||||
ut = ud * CCU_PLL_LOCK_CHECK_RETRIES;
|
||||
|
||||
regmap_update_bits(pll->sys_regs, pll->reg_ctl,
|
||||
CCU_PLL_CTL_RST, CCU_PLL_CTL_RST);
|
||||
|
||||
return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val,
|
||||
val & CCU_PLL_CTL_LOCK, ud, ut);
|
||||
}
|
||||
|
||||
static int ccu_pll_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_hw *parent_hw = clk_hw_get_parent(hw);
|
||||
struct ccu_pll *pll = to_ccu_pll(hw);
|
||||
unsigned long flags;
|
||||
u32 val = 0;
|
||||
int ret;
|
||||
|
||||
if (!parent_hw) {
|
||||
pr_err("Can't enable '%s' with no parent", clk_hw_get_name(hw));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_read(pll->sys_regs, pll->reg_ctl, &val);
|
||||
if (val & CCU_PLL_CTL_EN)
|
||||
return 0;
|
||||
|
||||
spin_lock_irqsave(&pll->lock, flags);
|
||||
regmap_write(pll->sys_regs, pll->reg_ctl, val | CCU_PLL_CTL_EN);
|
||||
ret = ccu_pll_reset(pll, clk_hw_get_rate(parent_hw),
|
||||
FIELD_GET(CCU_PLL_CTL_CLKR_MASK, val) + 1);
|
||||
spin_unlock_irqrestore(&pll->lock, flags);
|
||||
if (ret)
|
||||
pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ccu_pll_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct ccu_pll *pll = to_ccu_pll(hw);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&pll->lock, flags);
|
||||
regmap_update_bits(pll->sys_regs, pll->reg_ctl, CCU_PLL_CTL_EN, 0);
|
||||
spin_unlock_irqrestore(&pll->lock, flags);
|
||||
}
|
||||
|
||||
static int ccu_pll_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct ccu_pll *pll = to_ccu_pll(hw);
|
||||
u32 val = 0;
|
||||
|
||||
regmap_read(pll->sys_regs, pll->reg_ctl, &val);
|
||||
|
||||
return !!(val & CCU_PLL_CTL_EN);
|
||||
}
|
||||
|
||||
static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct ccu_pll *pll = to_ccu_pll(hw);
|
||||
unsigned long nr, nf, od;
|
||||
u32 val = 0;
|
||||
|
||||
regmap_read(pll->sys_regs, pll->reg_ctl, &val);
|
||||
nr = FIELD_GET(CCU_PLL_CTL_CLKR_MASK, val) + 1;
|
||||
nf = FIELD_GET(CCU_PLL_CTL_CLKF_MASK, val) + 1;
|
||||
od = FIELD_GET(CCU_PLL_CTL_CLKOD_MASK, val) + 1;
|
||||
|
||||
return ccu_pll_calc_freq(parent_rate, nr, nf, od);
|
||||
}
|
||||
|
||||
static void ccu_pll_calc_factors(unsigned long rate, unsigned long parent_rate,
|
||||
unsigned long *nr, unsigned long *nf,
|
||||
unsigned long *od)
|
||||
{
|
||||
unsigned long err, freq, min_err = ULONG_MAX;
|
||||
unsigned long num, denom, n1, d1, nri;
|
||||
unsigned long nr_max, nf_max, od_max;
|
||||
|
||||
/*
|
||||
* Make sure PLL is working with valid input signal (Fdiv). If
|
||||
* you want to speed the function up just reduce CCU_PLL_NR_MAX.
|
||||
* This will cause a worse approximation though.
|
||||
*/
|
||||
nri = (parent_rate / CCU_PLL_FDIV_MAX) + 1;
|
||||
nr_max = min(parent_rate / CCU_PLL_FDIV_MIN, CCU_PLL_NR_MAX);
|
||||
|
||||
/*
|
||||
* Find a closest [nr;nf;od] vector taking into account the
|
||||
* limitations like: 1) 700MHz <= Fvco <= 3.5GHz, 2) PLL Od is
|
||||
* either 1 or even number within the acceptable range (alas 1s
|
||||
* is also excluded by the next loop).
|
||||
*/
|
||||
for (; nri <= nr_max; ++nri) {
|
||||
/* Use Od factor to fulfill the limitation 2). */
|
||||
num = CCU_PLL_CLKOD_FACTOR * rate;
|
||||
denom = parent_rate / nri;
|
||||
|
||||
/*
|
||||
* Make sure Fvco is within the acceptable range to fulfill
|
||||
* the condition 1). Note due to the CCU_PLL_CLKOD_FACTOR value
|
||||
* the actual upper limit is also divided by that factor.
|
||||
* It's not big problem for us since practically there is no
|
||||
* need in clocks with that high frequency.
|
||||
*/
|
||||
nf_max = min(CCU_PLL_FVCO_MAX / denom, CCU_PLL_NF_MAX);
|
||||
od_max = CCU_PLL_OD_MAX / CCU_PLL_CLKOD_FACTOR;
|
||||
|
||||
/*
|
||||
* Bypass the out-of-bound values, which can't be properly
|
||||
* handled by the rational fraction approximation algorithm.
|
||||
*/
|
||||
if (num / denom >= nf_max) {
|
||||
n1 = nf_max;
|
||||
d1 = 1;
|
||||
} else if (denom / num >= od_max) {
|
||||
n1 = 1;
|
||||
d1 = od_max;
|
||||
} else {
|
||||
rational_best_approximation(num, denom, nf_max, od_max,
|
||||
&n1, &d1);
|
||||
}
|
||||
|
||||
/* Select the best approximation of the target rate. */
|
||||
freq = ccu_pll_calc_freq(parent_rate, nri, n1, d1);
|
||||
err = abs((int64_t)freq - num);
|
||||
if (err < min_err) {
|
||||
min_err = err;
|
||||
*nr = nri;
|
||||
*nf = n1;
|
||||
*od = CCU_PLL_CLKOD_FACTOR * d1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
unsigned long nr = 1, nf = 1, od = 1;
|
||||
|
||||
ccu_pll_calc_factors(rate, *parent_rate, &nr, &nf, &od);
|
||||
|
||||
return ccu_pll_calc_freq(*parent_rate, nr, nf, od);
|
||||
}
|
||||
|
||||
/*
|
||||
* This method is used for PLLs, which support the on-the-fly dividers
|
||||
* adjustment. So there is no need in gating such clocks.
|
||||
*/
|
||||
static int ccu_pll_set_rate_reset(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct ccu_pll *pll = to_ccu_pll(hw);
|
||||
unsigned long nr, nf, od;
|
||||
unsigned long flags;
|
||||
u32 mask, val;
|
||||
int ret;
|
||||
|
||||
ccu_pll_calc_factors(rate, parent_rate, &nr, &nf, &od);
|
||||
|
||||
mask = CCU_PLL_CTL_CLKR_MASK | CCU_PLL_CTL_CLKF_MASK |
|
||||
CCU_PLL_CTL_CLKOD_MASK;
|
||||
val = FIELD_PREP(CCU_PLL_CTL_CLKR_MASK, nr - 1) |
|
||||
FIELD_PREP(CCU_PLL_CTL_CLKF_MASK, nf - 1) |
|
||||
FIELD_PREP(CCU_PLL_CTL_CLKOD_MASK, od - 1);
|
||||
|
||||
spin_lock_irqsave(&pll->lock, flags);
|
||||
regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val);
|
||||
ret = ccu_pll_reset(pll, parent_rate, nr);
|
||||
spin_unlock_irqrestore(&pll->lock, flags);
|
||||
if (ret)
|
||||
pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* This method is used for PLLs, which don't support the on-the-fly dividers
|
||||
* adjustment. So the corresponding clocks are supposed to be gated first.
|
||||
*/
|
||||
static int ccu_pll_set_rate_norst(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct ccu_pll *pll = to_ccu_pll(hw);
|
||||
unsigned long nr, nf, od;
|
||||
unsigned long flags;
|
||||
u32 mask, val;
|
||||
|
||||
ccu_pll_calc_factors(rate, parent_rate, &nr, &nf, &od);
|
||||
|
||||
/*
|
||||
* Disable PLL if it was enabled by default or left enabled by the
|
||||
* system bootloader.
|
||||
*/
|
||||
mask = CCU_PLL_CTL_CLKR_MASK | CCU_PLL_CTL_CLKF_MASK |
|
||||
CCU_PLL_CTL_CLKOD_MASK | CCU_PLL_CTL_EN;
|
||||
val = FIELD_PREP(CCU_PLL_CTL_CLKR_MASK, nr - 1) |
|
||||
FIELD_PREP(CCU_PLL_CTL_CLKF_MASK, nf - 1) |
|
||||
FIELD_PREP(CCU_PLL_CTL_CLKOD_MASK, od - 1);
|
||||
|
||||
spin_lock_irqsave(&pll->lock, flags);
|
||||
regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val);
|
||||
spin_unlock_irqrestore(&pll->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
struct ccu_pll_dbgfs_bit {
|
||||
struct ccu_pll *pll;
|
||||
const char *name;
|
||||
unsigned int reg;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
struct ccu_pll_dbgfs_fld {
|
||||
struct ccu_pll *pll;
|
||||
const char *name;
|
||||
unsigned int reg;
|
||||
unsigned int lsb;
|
||||
u32 mask;
|
||||
u32 min;
|
||||
u32 max;
|
||||
};
|
||||
|
||||
#define CCU_PLL_DBGFS_BIT_ATTR(_name, _reg, _mask) \
|
||||
{ \
|
||||
.name = _name, \
|
||||
.reg = _reg, \
|
||||
.mask = _mask \
|
||||
}
|
||||
|
||||
#define CCU_PLL_DBGFS_FLD_ATTR(_name, _reg, _lsb, _mask, _min, _max) \
|
||||
{ \
|
||||
.name = _name, \
|
||||
.reg = _reg, \
|
||||
.lsb = _lsb, \
|
||||
.mask = _mask, \
|
||||
.min = _min, \
|
||||
.max = _max \
|
||||
}
|
||||
|
||||
static const struct ccu_pll_dbgfs_bit ccu_pll_bits[] = {
|
||||
CCU_PLL_DBGFS_BIT_ATTR("pll_en", CCU_PLL_CTL, CCU_PLL_CTL_EN),
|
||||
CCU_PLL_DBGFS_BIT_ATTR("pll_rst", CCU_PLL_CTL, CCU_PLL_CTL_RST),
|
||||
CCU_PLL_DBGFS_BIT_ATTR("pll_bypass", CCU_PLL_CTL, CCU_PLL_CTL_BYPASS),
|
||||
CCU_PLL_DBGFS_BIT_ATTR("pll_lock", CCU_PLL_CTL, CCU_PLL_CTL_LOCK)
|
||||
};
|
||||
|
||||
#define CCU_PLL_DBGFS_BIT_NUM ARRAY_SIZE(ccu_pll_bits)
|
||||
|
||||
static const struct ccu_pll_dbgfs_fld ccu_pll_flds[] = {
|
||||
CCU_PLL_DBGFS_FLD_ATTR("pll_nr", CCU_PLL_CTL, CCU_PLL_CTL_CLKR_FLD,
|
||||
CCU_PLL_CTL_CLKR_MASK, 1, CCU_PLL_NR_MAX),
|
||||
CCU_PLL_DBGFS_FLD_ATTR("pll_nf", CCU_PLL_CTL, CCU_PLL_CTL_CLKF_FLD,
|
||||
CCU_PLL_CTL_CLKF_MASK, 1, CCU_PLL_NF_MAX),
|
||||
CCU_PLL_DBGFS_FLD_ATTR("pll_od", CCU_PLL_CTL, CCU_PLL_CTL_CLKOD_FLD,
|
||||
CCU_PLL_CTL_CLKOD_MASK, 1, CCU_PLL_OD_MAX),
|
||||
CCU_PLL_DBGFS_FLD_ATTR("pll_nb", CCU_PLL_CTL1, CCU_PLL_CTL1_BWADJ_FLD,
|
||||
CCU_PLL_CTL1_BWADJ_MASK, 1, CCU_PLL_NB_MAX)
|
||||
};
|
||||
|
||||
#define CCU_PLL_DBGFS_FLD_NUM ARRAY_SIZE(ccu_pll_flds)
|
||||
|
||||
/*
|
||||
* It can be dangerous to change the PLL settings behind clock framework back,
|
||||
* therefore we don't provide any kernel config based compile time option for
|
||||
* this feature to enable.
|
||||
*/
|
||||
#undef CCU_PLL_ALLOW_WRITE_DEBUGFS
|
||||
#ifdef CCU_PLL_ALLOW_WRITE_DEBUGFS
|
||||
|
||||
static int ccu_pll_dbgfs_bit_set(void *priv, u64 val)
|
||||
{
|
||||
const struct ccu_pll_dbgfs_bit *bit = priv;
|
||||
struct ccu_pll *pll = bit->pll;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&pll->lock, flags);
|
||||
regmap_update_bits(pll->sys_regs, pll->reg_ctl + bit->reg,
|
||||
bit->mask, val ? bit->mask : 0);
|
||||
spin_unlock_irqrestore(&pll->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ccu_pll_dbgfs_fld_set(void *priv, u64 val)
|
||||
{
|
||||
struct ccu_pll_dbgfs_fld *fld = priv;
|
||||
struct ccu_pll *pll = fld->pll;
|
||||
unsigned long flags;
|
||||
u32 data;
|
||||
|
||||
val = clamp_t(u64, val, fld->min, fld->max);
|
||||
data = ((val - 1) << fld->lsb) & fld->mask;
|
||||
|
||||
spin_lock_irqsave(&pll->lock, flags);
|
||||
regmap_update_bits(pll->sys_regs, pll->reg_ctl + fld->reg, fld->mask,
|
||||
data);
|
||||
spin_unlock_irqrestore(&pll->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define ccu_pll_dbgfs_mode 0644
|
||||
|
||||
#else /* !CCU_PLL_ALLOW_WRITE_DEBUGFS */
|
||||
|
||||
#define ccu_pll_dbgfs_bit_set NULL
|
||||
#define ccu_pll_dbgfs_fld_set NULL
|
||||
#define ccu_pll_dbgfs_mode 0444
|
||||
|
||||
#endif /* !CCU_PLL_ALLOW_WRITE_DEBUGFS */
|
||||
|
||||
static int ccu_pll_dbgfs_bit_get(void *priv, u64 *val)
|
||||
{
|
||||
struct ccu_pll_dbgfs_bit *bit = priv;
|
||||
struct ccu_pll *pll = bit->pll;
|
||||
u32 data = 0;
|
||||
|
||||
regmap_read(pll->sys_regs, pll->reg_ctl + bit->reg, &data);
|
||||
*val = !!(data & bit->mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_DEBUGFS_ATTRIBUTE(ccu_pll_dbgfs_bit_fops,
|
||||
ccu_pll_dbgfs_bit_get, ccu_pll_dbgfs_bit_set, "%llu\n");
|
||||
|
||||
static int ccu_pll_dbgfs_fld_get(void *priv, u64 *val)
|
||||
{
|
||||
struct ccu_pll_dbgfs_fld *fld = priv;
|
||||
struct ccu_pll *pll = fld->pll;
|
||||
u32 data = 0;
|
||||
|
||||
regmap_read(pll->sys_regs, pll->reg_ctl + fld->reg, &data);
|
||||
*val = ((data & fld->mask) >> fld->lsb) + 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_DEBUGFS_ATTRIBUTE(ccu_pll_dbgfs_fld_fops,
|
||||
ccu_pll_dbgfs_fld_get, ccu_pll_dbgfs_fld_set, "%llu\n");
|
||||
|
||||
static void ccu_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
||||
{
|
||||
struct ccu_pll *pll = to_ccu_pll(hw);
|
||||
struct ccu_pll_dbgfs_bit *bits;
|
||||
struct ccu_pll_dbgfs_fld *flds;
|
||||
int idx;
|
||||
|
||||
bits = kcalloc(CCU_PLL_DBGFS_BIT_NUM, sizeof(*bits), GFP_KERNEL);
|
||||
if (!bits)
|
||||
return;
|
||||
|
||||
for (idx = 0; idx < CCU_PLL_DBGFS_BIT_NUM; ++idx) {
|
||||
bits[idx] = ccu_pll_bits[idx];
|
||||
bits[idx].pll = pll;
|
||||
|
||||
debugfs_create_file_unsafe(bits[idx].name, ccu_pll_dbgfs_mode,
|
||||
dentry, &bits[idx],
|
||||
&ccu_pll_dbgfs_bit_fops);
|
||||
}
|
||||
|
||||
flds = kcalloc(CCU_PLL_DBGFS_FLD_NUM, sizeof(*flds), GFP_KERNEL);
|
||||
if (!flds)
|
||||
return;
|
||||
|
||||
for (idx = 0; idx < CCU_PLL_DBGFS_FLD_NUM; ++idx) {
|
||||
flds[idx] = ccu_pll_flds[idx];
|
||||
flds[idx].pll = pll;
|
||||
|
||||
debugfs_create_file_unsafe(flds[idx].name, ccu_pll_dbgfs_mode,
|
||||
dentry, &flds[idx],
|
||||
&ccu_pll_dbgfs_fld_fops);
|
||||
}
|
||||
}
|
||||
|
||||
#else /* !CONFIG_DEBUG_FS */
|
||||
|
||||
#define ccu_pll_debug_init NULL
|
||||
|
||||
#endif /* !CONFIG_DEBUG_FS */
|
||||
|
||||
static const struct clk_ops ccu_pll_gate_to_set_ops = {
|
||||
.enable = ccu_pll_enable,
|
||||
.disable = ccu_pll_disable,
|
||||
.is_enabled = ccu_pll_is_enabled,
|
||||
.recalc_rate = ccu_pll_recalc_rate,
|
||||
.round_rate = ccu_pll_round_rate,
|
||||
.set_rate = ccu_pll_set_rate_norst,
|
||||
.debug_init = ccu_pll_debug_init
|
||||
};
|
||||
|
||||
static const struct clk_ops ccu_pll_straight_set_ops = {
|
||||
.enable = ccu_pll_enable,
|
||||
.disable = ccu_pll_disable,
|
||||
.is_enabled = ccu_pll_is_enabled,
|
||||
.recalc_rate = ccu_pll_recalc_rate,
|
||||
.round_rate = ccu_pll_round_rate,
|
||||
.set_rate = ccu_pll_set_rate_reset,
|
||||
.debug_init = ccu_pll_debug_init
|
||||
};
|
||||
|
||||
struct ccu_pll *ccu_pll_hw_register(const struct ccu_pll_init_data *pll_init)
|
||||
{
|
||||
struct clk_parent_data parent_data = { };
|
||||
struct clk_init_data hw_init = { };
|
||||
struct ccu_pll *pll;
|
||||
int ret;
|
||||
|
||||
if (!pll_init)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
/*
|
||||
* Note since Baikal-T1 System Controller registers are MMIO-backed
|
||||
* we won't check the regmap IO operations return status, because it
|
||||
* must be zero anyway.
|
||||
*/
|
||||
pll->hw.init = &hw_init;
|
||||
pll->reg_ctl = pll_init->base + CCU_PLL_CTL;
|
||||
pll->reg_ctl1 = pll_init->base + CCU_PLL_CTL1;
|
||||
pll->sys_regs = pll_init->sys_regs;
|
||||
pll->id = pll_init->id;
|
||||
spin_lock_init(&pll->lock);
|
||||
|
||||
hw_init.name = pll_init->name;
|
||||
hw_init.flags = pll_init->flags;
|
||||
|
||||
if (hw_init.flags & CLK_SET_RATE_GATE)
|
||||
hw_init.ops = &ccu_pll_gate_to_set_ops;
|
||||
else
|
||||
hw_init.ops = &ccu_pll_straight_set_ops;
|
||||
|
||||
if (!pll_init->parent_name) {
|
||||
ret = -EINVAL;
|
||||
goto err_free_pll;
|
||||
}
|
||||
parent_data.fw_name = pll_init->parent_name;
|
||||
hw_init.parent_data = &parent_data;
|
||||
hw_init.num_parents = 1;
|
||||
|
||||
ret = of_clk_hw_register(pll_init->np, &pll->hw);
|
||||
if (ret)
|
||||
goto err_free_pll;
|
||||
|
||||
return pll;
|
||||
|
||||
err_free_pll:
|
||||
kfree(pll);
|
||||
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
void ccu_pll_hw_unregister(struct ccu_pll *pll)
|
||||
{
|
||||
clk_hw_unregister(&pll->hw);
|
||||
|
||||
kfree(pll);
|
||||
}
|
||||
64
drivers/clk/baikal-t1/ccu-pll.h
Normal file
64
drivers/clk/baikal-t1/ccu-pll.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
*
|
||||
* Baikal-T1 CCU PLL interface driver
|
||||
*/
|
||||
#ifndef __CLK_BT1_CCU_PLL_H__
|
||||
#define __CLK_BT1_CCU_PLL_H__
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/bits.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
/*
|
||||
* struct ccu_pll_init_data - CCU PLL initialization data
|
||||
* @id: Clock private identifier.
|
||||
* @name: Clocks name.
|
||||
* @parent_name: Clocks parent name in a fw node.
|
||||
* @base: PLL registers base address with respect to the sys_regs base.
|
||||
* @sys_regs: Baikal-T1 System Controller registers map.
|
||||
* @np: Pointer to the node describing the CCU PLLs.
|
||||
* @flags: PLL clock flags.
|
||||
*/
|
||||
struct ccu_pll_init_data {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned int base;
|
||||
struct regmap *sys_regs;
|
||||
struct device_node *np;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct ccu_pll - CCU PLL descriptor
|
||||
* @hw: clk_hw of the PLL.
|
||||
* @id: Clock private identifier.
|
||||
* @reg_ctl: PLL control register base.
|
||||
* @reg_ctl1: PLL control1 register base.
|
||||
* @sys_regs: Baikal-T1 System Controller registers map.
|
||||
* @lock: PLL state change spin-lock.
|
||||
*/
|
||||
struct ccu_pll {
|
||||
struct clk_hw hw;
|
||||
unsigned int id;
|
||||
unsigned int reg_ctl;
|
||||
unsigned int reg_ctl1;
|
||||
struct regmap *sys_regs;
|
||||
spinlock_t lock;
|
||||
};
|
||||
#define to_ccu_pll(_hw) container_of(_hw, struct ccu_pll, hw)
|
||||
|
||||
static inline struct clk_hw *ccu_pll_get_clk_hw(struct ccu_pll *pll)
|
||||
{
|
||||
return pll ? &pll->hw : NULL;
|
||||
}
|
||||
|
||||
struct ccu_pll *ccu_pll_hw_register(const struct ccu_pll_init_data *init);
|
||||
|
||||
void ccu_pll_hw_unregister(struct ccu_pll *pll);
|
||||
|
||||
#endif /* __CLK_BT1_CCU_PLL_H__ */
|
||||
485
drivers/clk/baikal-t1/clk-ccu-div.c
Normal file
485
drivers/clk/baikal-t1/clk-ccu-div.c
Normal file
|
|
@ -0,0 +1,485 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
*
|
||||
* Authors:
|
||||
* Serge Semin <Sergey.Semin@baikalelectronics.ru>
|
||||
* Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
|
||||
*
|
||||
* Baikal-T1 CCU Dividers clock driver
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "bt1-ccu-div: " fmt
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/bt1-ccu.h>
|
||||
#include <dt-bindings/reset/bt1-ccu.h>
|
||||
|
||||
#include "ccu-div.h"
|
||||
|
||||
#define CCU_AXI_MAIN_BASE 0x030
|
||||
#define CCU_AXI_DDR_BASE 0x034
|
||||
#define CCU_AXI_SATA_BASE 0x038
|
||||
#define CCU_AXI_GMAC0_BASE 0x03C
|
||||
#define CCU_AXI_GMAC1_BASE 0x040
|
||||
#define CCU_AXI_XGMAC_BASE 0x044
|
||||
#define CCU_AXI_PCIE_M_BASE 0x048
|
||||
#define CCU_AXI_PCIE_S_BASE 0x04C
|
||||
#define CCU_AXI_USB_BASE 0x050
|
||||
#define CCU_AXI_HWA_BASE 0x054
|
||||
#define CCU_AXI_SRAM_BASE 0x058
|
||||
|
||||
#define CCU_SYS_SATA_REF_BASE 0x060
|
||||
#define CCU_SYS_APB_BASE 0x064
|
||||
#define CCU_SYS_GMAC0_BASE 0x068
|
||||
#define CCU_SYS_GMAC1_BASE 0x06C
|
||||
#define CCU_SYS_XGMAC_BASE 0x070
|
||||
#define CCU_SYS_USB_BASE 0x074
|
||||
#define CCU_SYS_PVT_BASE 0x078
|
||||
#define CCU_SYS_HWA_BASE 0x07C
|
||||
#define CCU_SYS_UART_BASE 0x084
|
||||
#define CCU_SYS_TIMER0_BASE 0x088
|
||||
#define CCU_SYS_TIMER1_BASE 0x08C
|
||||
#define CCU_SYS_TIMER2_BASE 0x090
|
||||
#define CCU_SYS_WDT_BASE 0x150
|
||||
|
||||
#define CCU_DIV_VAR_INFO(_id, _name, _pname, _base, _width, _flags, _features) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _pname, \
|
||||
.base = _base, \
|
||||
.type = CCU_DIV_VAR, \
|
||||
.width = _width, \
|
||||
.flags = _flags, \
|
||||
.features = _features \
|
||||
}
|
||||
|
||||
#define CCU_DIV_GATE_INFO(_id, _name, _pname, _base, _divider) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _pname, \
|
||||
.base = _base, \
|
||||
.type = CCU_DIV_GATE, \
|
||||
.divider = _divider \
|
||||
}
|
||||
|
||||
#define CCU_DIV_FIXED_INFO(_id, _name, _pname, _divider) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _pname, \
|
||||
.type = CCU_DIV_FIXED, \
|
||||
.divider = _divider \
|
||||
}
|
||||
|
||||
#define CCU_DIV_RST_MAP(_rst_id, _clk_id) \
|
||||
{ \
|
||||
.rst_id = _rst_id, \
|
||||
.clk_id = _clk_id \
|
||||
}
|
||||
|
||||
struct ccu_div_info {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned int base;
|
||||
enum ccu_div_type type;
|
||||
union {
|
||||
unsigned int width;
|
||||
unsigned int divider;
|
||||
};
|
||||
unsigned long flags;
|
||||
unsigned long features;
|
||||
};
|
||||
|
||||
struct ccu_div_rst_map {
|
||||
unsigned int rst_id;
|
||||
unsigned int clk_id;
|
||||
};
|
||||
|
||||
struct ccu_div_data {
|
||||
struct device_node *np;
|
||||
struct regmap *sys_regs;
|
||||
|
||||
unsigned int divs_num;
|
||||
const struct ccu_div_info *divs_info;
|
||||
struct ccu_div **divs;
|
||||
|
||||
unsigned int rst_num;
|
||||
const struct ccu_div_rst_map *rst_map;
|
||||
struct reset_controller_dev rcdev;
|
||||
};
|
||||
#define to_ccu_div_data(_rcdev) container_of(_rcdev, struct ccu_div_data, rcdev)
|
||||
|
||||
/*
|
||||
* AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
|
||||
* must be left enabled in any case, since former one is responsible for
|
||||
* clocking a bus between CPU cores and the rest of the SoC components, while
|
||||
* the later is clocking the AXI-bus between DDR controller and the Main
|
||||
* Interconnect. So should any of these clocks get to be disabled, the system
|
||||
* will literally stop working. That's why we marked them as critical.
|
||||
*/
|
||||
static const struct ccu_div_info axi_info[] = {
|
||||
CCU_DIV_VAR_INFO(CCU_AXI_MAIN_CLK, "axi_main_clk", "pcie_clk",
|
||||
CCU_AXI_MAIN_BASE, 4,
|
||||
CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_VAR_INFO(CCU_AXI_DDR_CLK, "axi_ddr_clk", "sata_clk",
|
||||
CCU_AXI_DDR_BASE, 4,
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
|
||||
CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_VAR_INFO(CCU_AXI_SATA_CLK, "axi_sata_clk", "sata_clk",
|
||||
CCU_AXI_SATA_BASE, 4,
|
||||
CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_VAR_INFO(CCU_AXI_GMAC0_CLK, "axi_gmac0_clk", "eth_clk",
|
||||
CCU_AXI_GMAC0_BASE, 4,
|
||||
CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_VAR_INFO(CCU_AXI_GMAC1_CLK, "axi_gmac1_clk", "eth_clk",
|
||||
CCU_AXI_GMAC1_BASE, 4,
|
||||
CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_VAR_INFO(CCU_AXI_XGMAC_CLK, "axi_xgmac_clk", "eth_clk",
|
||||
CCU_AXI_XGMAC_BASE, 4,
|
||||
CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_VAR_INFO(CCU_AXI_PCIE_M_CLK, "axi_pcie_m_clk", "pcie_clk",
|
||||
CCU_AXI_PCIE_M_BASE, 4,
|
||||
CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_VAR_INFO(CCU_AXI_PCIE_S_CLK, "axi_pcie_s_clk", "pcie_clk",
|
||||
CCU_AXI_PCIE_S_BASE, 4,
|
||||
CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_VAR_INFO(CCU_AXI_USB_CLK, "axi_usb_clk", "sata_clk",
|
||||
CCU_AXI_USB_BASE, 4,
|
||||
CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_VAR_INFO(CCU_AXI_HWA_CLK, "axi_hwa_clk", "sata_clk",
|
||||
CCU_AXI_HWA_BASE, 4,
|
||||
CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_VAR_INFO(CCU_AXI_SRAM_CLK, "axi_sram_clk", "eth_clk",
|
||||
CCU_AXI_SRAM_BASE, 4,
|
||||
CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN)
|
||||
};
|
||||
|
||||
static const struct ccu_div_rst_map axi_rst_map[] = {
|
||||
CCU_DIV_RST_MAP(CCU_AXI_MAIN_RST, CCU_AXI_MAIN_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_DDR_RST, CCU_AXI_DDR_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_SATA_RST, CCU_AXI_SATA_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_GMAC0_RST, CCU_AXI_GMAC0_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_GMAC1_RST, CCU_AXI_GMAC1_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_XGMAC_RST, CCU_AXI_XGMAC_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_PCIE_M_RST, CCU_AXI_PCIE_M_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_PCIE_S_RST, CCU_AXI_PCIE_S_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_USB_RST, CCU_AXI_USB_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_HWA_RST, CCU_AXI_HWA_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_SRAM_RST, CCU_AXI_SRAM_CLK)
|
||||
};
|
||||
|
||||
/*
|
||||
* APB-bus clock is marked as critical since it's a main communication bus
|
||||
* for the SoC devices registers IO-operations.
|
||||
*/
|
||||
static const struct ccu_div_info sys_info[] = {
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk",
|
||||
"sata_clk", CCU_SYS_SATA_REF_BASE, 4,
|
||||
CLK_SET_RATE_GATE,
|
||||
CCU_DIV_SKIP_ONE | CCU_DIV_LOCK_SHIFTED |
|
||||
CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_APB_CLK, "sys_apb_clk",
|
||||
"pcie_clk", CCU_SYS_APB_BASE, 5,
|
||||
CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_GATE_INFO(CCU_SYS_GMAC0_TX_CLK, "sys_gmac0_tx_clk",
|
||||
"eth_clk", CCU_SYS_GMAC0_BASE, 5),
|
||||
CCU_DIV_FIXED_INFO(CCU_SYS_GMAC0_PTP_CLK, "sys_gmac0_ptp_clk",
|
||||
"eth_clk", 10),
|
||||
CCU_DIV_GATE_INFO(CCU_SYS_GMAC1_TX_CLK, "sys_gmac1_tx_clk",
|
||||
"eth_clk", CCU_SYS_GMAC1_BASE, 5),
|
||||
CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
|
||||
"eth_clk", 10),
|
||||
CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
|
||||
"eth_clk", CCU_SYS_XGMAC_BASE, 8),
|
||||
CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
|
||||
"eth_clk", 10),
|
||||
CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
|
||||
"eth_clk", CCU_SYS_USB_BASE, 10),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
|
||||
"ref_clk", CCU_SYS_PVT_BASE, 5,
|
||||
CLK_SET_RATE_GATE, 0),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_HWA_CLK, "sys_hwa_clk",
|
||||
"sata_clk", CCU_SYS_HWA_BASE, 4,
|
||||
CLK_SET_RATE_GATE, 0),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_UART_CLK, "sys_uart_clk",
|
||||
"eth_clk", CCU_SYS_UART_BASE, 17,
|
||||
CLK_SET_RATE_GATE, 0),
|
||||
CCU_DIV_FIXED_INFO(CCU_SYS_I2C1_CLK, "sys_i2c1_clk",
|
||||
"eth_clk", 10),
|
||||
CCU_DIV_FIXED_INFO(CCU_SYS_I2C2_CLK, "sys_i2c2_clk",
|
||||
"eth_clk", 10),
|
||||
CCU_DIV_FIXED_INFO(CCU_SYS_GPIO_CLK, "sys_gpio_clk",
|
||||
"ref_clk", 25),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_TIMER0_CLK, "sys_timer0_clk",
|
||||
"ref_clk", CCU_SYS_TIMER0_BASE, 17,
|
||||
CLK_SET_RATE_GATE, 0),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_TIMER1_CLK, "sys_timer1_clk",
|
||||
"ref_clk", CCU_SYS_TIMER1_BASE, 17,
|
||||
CLK_SET_RATE_GATE, 0),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_TIMER2_CLK, "sys_timer2_clk",
|
||||
"ref_clk", CCU_SYS_TIMER2_BASE, 17,
|
||||
CLK_SET_RATE_GATE, 0),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_WDT_CLK, "sys_wdt_clk",
|
||||
"eth_clk", CCU_SYS_WDT_BASE, 17,
|
||||
CLK_SET_RATE_GATE, CCU_DIV_SKIP_ONE_TO_THREE)
|
||||
};
|
||||
|
||||
static const struct ccu_div_rst_map sys_rst_map[] = {
|
||||
CCU_DIV_RST_MAP(CCU_SYS_SATA_REF_RST, CCU_SYS_SATA_REF_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_SYS_APB_RST, CCU_SYS_APB_CLK),
|
||||
};
|
||||
|
||||
static struct ccu_div *ccu_div_find_desc(struct ccu_div_data *data,
|
||||
unsigned int clk_id)
|
||||
{
|
||||
struct ccu_div *div;
|
||||
int idx;
|
||||
|
||||
for (idx = 0; idx < data->divs_num; ++idx) {
|
||||
div = data->divs[idx];
|
||||
if (div && div->id == clk_id)
|
||||
return div;
|
||||
}
|
||||
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static int ccu_div_reset(struct reset_controller_dev *rcdev,
|
||||
unsigned long rst_id)
|
||||
{
|
||||
struct ccu_div_data *data = to_ccu_div_data(rcdev);
|
||||
const struct ccu_div_rst_map *map;
|
||||
struct ccu_div *div;
|
||||
int idx, ret;
|
||||
|
||||
for (idx = 0, map = data->rst_map; idx < data->rst_num; ++idx, ++map) {
|
||||
if (map->rst_id == rst_id)
|
||||
break;
|
||||
}
|
||||
if (idx == data->rst_num) {
|
||||
pr_err("Invalid reset ID %lu specified\n", rst_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
div = ccu_div_find_desc(data, map->clk_id);
|
||||
if (IS_ERR(div)) {
|
||||
pr_err("Invalid clock ID %d in mapping\n", map->clk_id);
|
||||
return PTR_ERR(div);
|
||||
}
|
||||
|
||||
ret = ccu_div_reset_domain(div);
|
||||
if (ret) {
|
||||
pr_err("Reset isn't supported by divider %s\n",
|
||||
clk_hw_get_name(ccu_div_get_clk_hw(div)));
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct reset_control_ops ccu_div_rst_ops = {
|
||||
.reset = ccu_div_reset,
|
||||
};
|
||||
|
||||
static struct ccu_div_data *ccu_div_create_data(struct device_node *np)
|
||||
{
|
||||
struct ccu_div_data *data;
|
||||
int ret;
|
||||
|
||||
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
data->np = np;
|
||||
if (of_device_is_compatible(np, "baikal,bt1-ccu-axi")) {
|
||||
data->divs_num = ARRAY_SIZE(axi_info);
|
||||
data->divs_info = axi_info;
|
||||
data->rst_num = ARRAY_SIZE(axi_rst_map);
|
||||
data->rst_map = axi_rst_map;
|
||||
} else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys")) {
|
||||
data->divs_num = ARRAY_SIZE(sys_info);
|
||||
data->divs_info = sys_info;
|
||||
data->rst_num = ARRAY_SIZE(sys_rst_map);
|
||||
data->rst_map = sys_rst_map;
|
||||
} else {
|
||||
pr_err("Uncompatible DT node '%s' specified\n",
|
||||
of_node_full_name(np));
|
||||
ret = -EINVAL;
|
||||
goto err_kfree_data;
|
||||
}
|
||||
|
||||
data->divs = kcalloc(data->divs_num, sizeof(*data->divs), GFP_KERNEL);
|
||||
if (!data->divs) {
|
||||
ret = -ENOMEM;
|
||||
goto err_kfree_data;
|
||||
}
|
||||
|
||||
return data;
|
||||
|
||||
err_kfree_data:
|
||||
kfree(data);
|
||||
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
static void ccu_div_free_data(struct ccu_div_data *data)
|
||||
{
|
||||
kfree(data->divs);
|
||||
|
||||
kfree(data);
|
||||
}
|
||||
|
||||
static int ccu_div_find_sys_regs(struct ccu_div_data *data)
|
||||
{
|
||||
data->sys_regs = syscon_node_to_regmap(data->np->parent);
|
||||
if (IS_ERR(data->sys_regs)) {
|
||||
pr_err("Failed to find syscon regs for '%s'\n",
|
||||
of_node_full_name(data->np));
|
||||
return PTR_ERR(data->sys_regs);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_hw *ccu_div_of_clk_hw_get(struct of_phandle_args *clkspec,
|
||||
void *priv)
|
||||
{
|
||||
struct ccu_div_data *data = priv;
|
||||
struct ccu_div *div;
|
||||
unsigned int clk_id;
|
||||
|
||||
clk_id = clkspec->args[0];
|
||||
div = ccu_div_find_desc(data, clk_id);
|
||||
if (IS_ERR(div)) {
|
||||
pr_info("Invalid clock ID %d specified\n", clk_id);
|
||||
return ERR_CAST(div);
|
||||
}
|
||||
|
||||
return ccu_div_get_clk_hw(div);
|
||||
}
|
||||
|
||||
static int ccu_div_clk_register(struct ccu_div_data *data)
|
||||
{
|
||||
int idx, ret;
|
||||
|
||||
for (idx = 0; idx < data->divs_num; ++idx) {
|
||||
const struct ccu_div_info *info = &data->divs_info[idx];
|
||||
struct ccu_div_init_data init = {0};
|
||||
|
||||
init.id = info->id;
|
||||
init.name = info->name;
|
||||
init.parent_name = info->parent_name;
|
||||
init.np = data->np;
|
||||
init.type = info->type;
|
||||
init.flags = info->flags;
|
||||
init.features = info->features;
|
||||
|
||||
if (init.type == CCU_DIV_VAR) {
|
||||
init.base = info->base;
|
||||
init.sys_regs = data->sys_regs;
|
||||
init.width = info->width;
|
||||
} else if (init.type == CCU_DIV_GATE) {
|
||||
init.base = info->base;
|
||||
init.sys_regs = data->sys_regs;
|
||||
init.divider = info->divider;
|
||||
} else {
|
||||
init.divider = info->divider;
|
||||
}
|
||||
|
||||
data->divs[idx] = ccu_div_hw_register(&init);
|
||||
if (IS_ERR(data->divs[idx])) {
|
||||
ret = PTR_ERR(data->divs[idx]);
|
||||
pr_err("Couldn't register divider '%s' hw\n",
|
||||
init.name);
|
||||
goto err_hw_unregister;
|
||||
}
|
||||
}
|
||||
|
||||
ret = of_clk_add_hw_provider(data->np, ccu_div_of_clk_hw_get, data);
|
||||
if (ret) {
|
||||
pr_err("Couldn't register dividers '%s' clock provider\n",
|
||||
of_node_full_name(data->np));
|
||||
goto err_hw_unregister;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_hw_unregister:
|
||||
for (--idx; idx >= 0; --idx)
|
||||
ccu_div_hw_unregister(data->divs[idx]);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ccu_div_clk_unregister(struct ccu_div_data *data)
|
||||
{
|
||||
int idx;
|
||||
|
||||
of_clk_del_provider(data->np);
|
||||
|
||||
for (idx = 0; idx < data->divs_num; ++idx)
|
||||
ccu_div_hw_unregister(data->divs[idx]);
|
||||
}
|
||||
|
||||
static int ccu_div_rst_register(struct ccu_div_data *data)
|
||||
{
|
||||
int ret;
|
||||
|
||||
data->rcdev.ops = &ccu_div_rst_ops;
|
||||
data->rcdev.of_node = data->np;
|
||||
data->rcdev.nr_resets = data->rst_num;
|
||||
|
||||
ret = reset_controller_register(&data->rcdev);
|
||||
if (ret)
|
||||
pr_err("Couldn't register divider '%s' reset controller\n",
|
||||
of_node_full_name(data->np));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ccu_div_init(struct device_node *np)
|
||||
{
|
||||
struct ccu_div_data *data;
|
||||
int ret;
|
||||
|
||||
data = ccu_div_create_data(np);
|
||||
if (IS_ERR(data))
|
||||
return;
|
||||
|
||||
ret = ccu_div_find_sys_regs(data);
|
||||
if (ret)
|
||||
goto err_free_data;
|
||||
|
||||
ret = ccu_div_clk_register(data);
|
||||
if (ret)
|
||||
goto err_free_data;
|
||||
|
||||
ret = ccu_div_rst_register(data);
|
||||
if (ret)
|
||||
goto err_clk_unregister;
|
||||
|
||||
return;
|
||||
|
||||
err_clk_unregister:
|
||||
ccu_div_clk_unregister(data);
|
||||
|
||||
err_free_data:
|
||||
ccu_div_free_data(data);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(ccu_axi, "baikal,bt1-ccu-axi", ccu_div_init);
|
||||
CLK_OF_DECLARE(ccu_sys, "baikal,bt1-ccu-sys", ccu_div_init);
|
||||
204
drivers/clk/baikal-t1/clk-ccu-pll.c
Normal file
204
drivers/clk/baikal-t1/clk-ccu-pll.c
Normal file
|
|
@ -0,0 +1,204 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
*
|
||||
* Authors:
|
||||
* Serge Semin <Sergey.Semin@baikalelectronics.ru>
|
||||
* Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
|
||||
*
|
||||
* Baikal-T1 CCU PLL clocks driver
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "bt1-ccu-pll: " fmt
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/bt1-ccu.h>
|
||||
|
||||
#include "ccu-pll.h"
|
||||
|
||||
#define CCU_CPU_PLL_BASE 0x000
|
||||
#define CCU_SATA_PLL_BASE 0x008
|
||||
#define CCU_DDR_PLL_BASE 0x010
|
||||
#define CCU_PCIE_PLL_BASE 0x018
|
||||
#define CCU_ETH_PLL_BASE 0x020
|
||||
|
||||
#define CCU_PLL_INFO(_id, _name, _pname, _base, _flags) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _pname, \
|
||||
.base = _base, \
|
||||
.flags = _flags \
|
||||
}
|
||||
|
||||
#define CCU_PLL_NUM ARRAY_SIZE(pll_info)
|
||||
|
||||
struct ccu_pll_info {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned int base;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
/*
|
||||
* Mark as critical all PLLs except Ethernet one. CPU and DDR PLLs are sources
|
||||
* of CPU cores and DDR controller reference clocks, due to which they
|
||||
* obviously shouldn't be ever gated. SATA and PCIe PLLs are the parents of
|
||||
* APB-bus and DDR controller AXI-bus clocks. If they are gated the system will
|
||||
* be unusable.
|
||||
*/
|
||||
static const struct ccu_pll_info pll_info[] = {
|
||||
CCU_PLL_INFO(CCU_CPU_PLL, "cpu_pll", "ref_clk", CCU_CPU_PLL_BASE,
|
||||
CLK_IS_CRITICAL),
|
||||
CCU_PLL_INFO(CCU_SATA_PLL, "sata_pll", "ref_clk", CCU_SATA_PLL_BASE,
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_GATE),
|
||||
CCU_PLL_INFO(CCU_DDR_PLL, "ddr_pll", "ref_clk", CCU_DDR_PLL_BASE,
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_GATE),
|
||||
CCU_PLL_INFO(CCU_PCIE_PLL, "pcie_pll", "ref_clk", CCU_PCIE_PLL_BASE,
|
||||
CLK_IS_CRITICAL),
|
||||
CCU_PLL_INFO(CCU_ETH_PLL, "eth_pll", "ref_clk", CCU_ETH_PLL_BASE,
|
||||
CLK_SET_RATE_GATE)
|
||||
};
|
||||
|
||||
struct ccu_pll_data {
|
||||
struct device_node *np;
|
||||
struct regmap *sys_regs;
|
||||
struct ccu_pll *plls[CCU_PLL_NUM];
|
||||
};
|
||||
|
||||
static struct ccu_pll *ccu_pll_find_desc(struct ccu_pll_data *data,
|
||||
unsigned int clk_id)
|
||||
{
|
||||
struct ccu_pll *pll;
|
||||
int idx;
|
||||
|
||||
for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
|
||||
pll = data->plls[idx];
|
||||
if (pll && pll->id == clk_id)
|
||||
return pll;
|
||||
}
|
||||
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static struct ccu_pll_data *ccu_pll_create_data(struct device_node *np)
|
||||
{
|
||||
struct ccu_pll_data *data;
|
||||
|
||||
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
data->np = np;
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
static void ccu_pll_free_data(struct ccu_pll_data *data)
|
||||
{
|
||||
kfree(data);
|
||||
}
|
||||
|
||||
static int ccu_pll_find_sys_regs(struct ccu_pll_data *data)
|
||||
{
|
||||
data->sys_regs = syscon_node_to_regmap(data->np->parent);
|
||||
if (IS_ERR(data->sys_regs)) {
|
||||
pr_err("Failed to find syscon regs for '%s'\n",
|
||||
of_node_full_name(data->np));
|
||||
return PTR_ERR(data->sys_regs);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_hw *ccu_pll_of_clk_hw_get(struct of_phandle_args *clkspec,
|
||||
void *priv)
|
||||
{
|
||||
struct ccu_pll_data *data = priv;
|
||||
struct ccu_pll *pll;
|
||||
unsigned int clk_id;
|
||||
|
||||
clk_id = clkspec->args[0];
|
||||
pll = ccu_pll_find_desc(data, clk_id);
|
||||
if (IS_ERR(pll)) {
|
||||
pr_info("Invalid PLL clock ID %d specified\n", clk_id);
|
||||
return ERR_CAST(pll);
|
||||
}
|
||||
|
||||
return ccu_pll_get_clk_hw(pll);
|
||||
}
|
||||
|
||||
static int ccu_pll_clk_register(struct ccu_pll_data *data)
|
||||
{
|
||||
int idx, ret;
|
||||
|
||||
for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
|
||||
const struct ccu_pll_info *info = &pll_info[idx];
|
||||
struct ccu_pll_init_data init = {0};
|
||||
|
||||
init.id = info->id;
|
||||
init.name = info->name;
|
||||
init.parent_name = info->parent_name;
|
||||
init.base = info->base;
|
||||
init.sys_regs = data->sys_regs;
|
||||
init.np = data->np;
|
||||
init.flags = info->flags;
|
||||
|
||||
data->plls[idx] = ccu_pll_hw_register(&init);
|
||||
if (IS_ERR(data->plls[idx])) {
|
||||
ret = PTR_ERR(data->plls[idx]);
|
||||
pr_err("Couldn't register PLL hw '%s'\n",
|
||||
init.name);
|
||||
goto err_hw_unregister;
|
||||
}
|
||||
}
|
||||
|
||||
ret = of_clk_add_hw_provider(data->np, ccu_pll_of_clk_hw_get, data);
|
||||
if (ret) {
|
||||
pr_err("Couldn't register PLL provider of '%s'\n",
|
||||
of_node_full_name(data->np));
|
||||
goto err_hw_unregister;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_hw_unregister:
|
||||
for (--idx; idx >= 0; --idx)
|
||||
ccu_pll_hw_unregister(data->plls[idx]);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static __init void ccu_pll_init(struct device_node *np)
|
||||
{
|
||||
struct ccu_pll_data *data;
|
||||
int ret;
|
||||
|
||||
data = ccu_pll_create_data(np);
|
||||
if (IS_ERR(data))
|
||||
return;
|
||||
|
||||
ret = ccu_pll_find_sys_regs(data);
|
||||
if (ret)
|
||||
goto err_free_data;
|
||||
|
||||
ret = ccu_pll_clk_register(data);
|
||||
if (ret)
|
||||
goto err_free_data;
|
||||
|
||||
return;
|
||||
|
||||
err_free_data:
|
||||
ccu_pll_free_data(data);
|
||||
}
|
||||
CLK_OF_DECLARE(ccu_pll, "baikal,bt1-ccu-pll", ccu_pll_init);
|
||||
|
|
@ -53,35 +53,38 @@ struct hsdk_pll_cfg {
|
|||
u32 fbdiv;
|
||||
u32 odiv;
|
||||
u32 band;
|
||||
u32 bypass;
|
||||
};
|
||||
|
||||
static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
|
||||
{ 100000000, 0, 11, 3, 0 },
|
||||
{ 133000000, 0, 15, 3, 0 },
|
||||
{ 200000000, 1, 47, 3, 0 },
|
||||
{ 233000000, 1, 27, 2, 0 },
|
||||
{ 300000000, 1, 35, 2, 0 },
|
||||
{ 333000000, 1, 39, 2, 0 },
|
||||
{ 400000000, 1, 47, 2, 0 },
|
||||
{ 500000000, 0, 14, 1, 0 },
|
||||
{ 600000000, 0, 17, 1, 0 },
|
||||
{ 700000000, 0, 20, 1, 0 },
|
||||
{ 800000000, 0, 23, 1, 0 },
|
||||
{ 900000000, 1, 26, 0, 0 },
|
||||
{ 1000000000, 1, 29, 0, 0 },
|
||||
{ 1100000000, 1, 32, 0, 0 },
|
||||
{ 1200000000, 1, 35, 0, 0 },
|
||||
{ 1300000000, 1, 38, 0, 0 },
|
||||
{ 1400000000, 1, 41, 0, 0 },
|
||||
{ 1500000000, 1, 44, 0, 0 },
|
||||
{ 1600000000, 1, 47, 0, 0 },
|
||||
{ 100000000, 0, 11, 3, 0, 0 },
|
||||
{ 133000000, 0, 15, 3, 0, 0 },
|
||||
{ 200000000, 1, 47, 3, 0, 0 },
|
||||
{ 233000000, 1, 27, 2, 0, 0 },
|
||||
{ 300000000, 1, 35, 2, 0, 0 },
|
||||
{ 333000000, 1, 39, 2, 0, 0 },
|
||||
{ 400000000, 1, 47, 2, 0, 0 },
|
||||
{ 500000000, 0, 14, 1, 0, 0 },
|
||||
{ 600000000, 0, 17, 1, 0, 0 },
|
||||
{ 700000000, 0, 20, 1, 0, 0 },
|
||||
{ 800000000, 0, 23, 1, 0, 0 },
|
||||
{ 900000000, 1, 26, 0, 0, 0 },
|
||||
{ 1000000000, 1, 29, 0, 0, 0 },
|
||||
{ 1100000000, 1, 32, 0, 0, 0 },
|
||||
{ 1200000000, 1, 35, 0, 0, 0 },
|
||||
{ 1300000000, 1, 38, 0, 0, 0 },
|
||||
{ 1400000000, 1, 41, 0, 0, 0 },
|
||||
{ 1500000000, 1, 44, 0, 0, 0 },
|
||||
{ 1600000000, 1, 47, 0, 0, 0 },
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
|
||||
{ 297000000, 0, 21, 2, 0 },
|
||||
{ 540000000, 0, 19, 1, 0 },
|
||||
{ 594000000, 0, 21, 1, 0 },
|
||||
{ 27000000, 0, 0, 0, 0, 1 },
|
||||
{ 148500000, 0, 21, 3, 0, 0 },
|
||||
{ 297000000, 0, 21, 2, 0, 0 },
|
||||
{ 540000000, 0, 19, 1, 0, 0 },
|
||||
{ 594000000, 0, 21, 1, 0, 0 },
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
@ -134,11 +137,16 @@ static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk,
|
|||
{
|
||||
u32 val = 0;
|
||||
|
||||
/* Powerdown and Bypass bits should be cleared */
|
||||
val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
|
||||
val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
|
||||
val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
|
||||
val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
|
||||
if (cfg->bypass) {
|
||||
val = hsdk_pll_read(clk, CGU_PLL_CTRL);
|
||||
val |= CGU_PLL_CTRL_BYPASS;
|
||||
} else {
|
||||
/* Powerdown and Bypass bits should be cleared */
|
||||
val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
|
||||
val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
|
||||
val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
|
||||
val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
|
||||
}
|
||||
|
||||
dev_dbg(clk->dev, "write configuration: %#x\n", val);
|
||||
|
||||
|
|
@ -172,14 +180,14 @@ static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
|
|||
|
||||
dev_dbg(clk->dev, "current configuration: %#x\n", val);
|
||||
|
||||
/* Check if PLL is disabled */
|
||||
if (val & CGU_PLL_CTRL_PD)
|
||||
return 0;
|
||||
|
||||
/* Check if PLL is bypassed */
|
||||
if (val & CGU_PLL_CTRL_BYPASS)
|
||||
return parent_rate;
|
||||
|
||||
/* Check if PLL is disabled */
|
||||
if (val & CGU_PLL_CTRL_PD)
|
||||
return 0;
|
||||
|
||||
/* input divider = reg.idiv + 1 */
|
||||
idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
|
||||
/* fb divider = 2*(reg.fbdiv + 1) */
|
||||
|
|
|
|||
|
|
@ -124,6 +124,7 @@ enum vc5_model {
|
|||
IDT_VC5_5P49V5933,
|
||||
IDT_VC5_5P49V5935,
|
||||
IDT_VC6_5P49V6901,
|
||||
IDT_VC6_5P49V6965,
|
||||
};
|
||||
|
||||
/* Structure to describe features of a particular VC5 model */
|
||||
|
|
@ -683,6 +684,7 @@ static int vc5_map_index_to_output(const enum vc5_model model,
|
|||
case IDT_VC5_5P49V5925:
|
||||
case IDT_VC5_5P49V5935:
|
||||
case IDT_VC6_5P49V6901:
|
||||
case IDT_VC6_5P49V6965:
|
||||
default:
|
||||
return n;
|
||||
}
|
||||
|
|
@ -956,12 +958,20 @@ static const struct vc5_chip_info idt_5p49v6901_info = {
|
|||
.flags = VC5_HAS_PFD_FREQ_DBL,
|
||||
};
|
||||
|
||||
static const struct vc5_chip_info idt_5p49v6965_info = {
|
||||
.model = IDT_VC6_5P49V6965,
|
||||
.clk_fod_cnt = 4,
|
||||
.clk_out_cnt = 5,
|
||||
.flags = 0,
|
||||
};
|
||||
|
||||
static const struct i2c_device_id vc5_id[] = {
|
||||
{ "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
|
||||
{ "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
|
||||
{ "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
|
||||
{ "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
|
||||
{ "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
|
||||
{ "5p49v6965", .driver_data = IDT_VC6_5P49V6965 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, vc5_id);
|
||||
|
|
@ -972,6 +982,7 @@ static const struct of_device_id clk_vc5_of_match[] = {
|
|||
{ .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
|
||||
{ .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
|
||||
{ .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
|
||||
{ .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
|
||||
|
|
|
|||
|
|
@ -117,6 +117,92 @@ config COMMON_CLK_MT2712_VENCSYS
|
|||
---help---
|
||||
This driver supports MediaTek MT2712 vencsys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765
|
||||
bool "Clock driver for MediaTek MT6765"
|
||||
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
|
||||
select COMMON_CLK_MEDIATEK
|
||||
default ARCH_MEDIATEK && ARM64
|
||||
help
|
||||
This driver supports MediaTek MT6765 basic clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_AUDIOSYS
|
||||
bool "Clock driver for MediaTek MT6765 audiosys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 audiosys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_CAMSYS
|
||||
bool "Clock driver for MediaTek MT6765 camsys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 camsys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_GCESYS
|
||||
bool "Clock driver for MediaTek MT6765 gcesys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 gcesys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_MMSYS
|
||||
bool "Clock driver for MediaTek MT6765 mmsys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 mmsys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_IMGSYS
|
||||
bool "Clock driver for MediaTek MT6765 imgsys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 imgsys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_VCODECSYS
|
||||
bool "Clock driver for MediaTek MT6765 vcodecsys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 vcodecsys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_MFGSYS
|
||||
bool "Clock driver for MediaTek MT6765 mfgsys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 mfgsys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_MIPI0ASYS
|
||||
bool "Clock driver for MediaTek MT6765 mipi0asys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 mipi0asys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_MIPI0BSYS
|
||||
bool "Clock driver for MediaTek MT6765 mipi0bsys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 mipi0bsys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_MIPI1ASYS
|
||||
bool "Clock driver for MediaTek MT6765 mipi1asys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 mipi1asys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_MIPI1BSYS
|
||||
bool "Clock driver for MediaTek MT6765 mipi1bsys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 mipi1bsys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_MIPI2ASYS
|
||||
bool "Clock driver for MediaTek MT6765 mipi2asys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 mipi2asys clocks.
|
||||
|
||||
config COMMON_CLK_MT6765_MIPI2BSYS
|
||||
bool "Clock driver for MediaTek MT6765 mipi2bsys"
|
||||
depends on COMMON_CLK_MT6765
|
||||
help
|
||||
This driver supports MediaTek MT6765 mipi2bsys clocks.
|
||||
|
||||
config COMMON_CLK_MT6779
|
||||
bool "Clock driver for MediaTek MT6779"
|
||||
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
|
||||
|
|
|
|||
|
|
@ -1,6 +1,13 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
|
||||
|
||||
obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT6765_IMGSYS) += clk-mt6765-img.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT6765_MIPI0ASYS) += clk-mt6765-mipi0a.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT6765_MMSYS) += clk-mt6765-mm.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT6765_VCODECSYS) += clk-mt6765-vcodec.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT6779) += clk-mt6779.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT6779_MMSYS) += clk-mt6779-mm.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT6779_IMGSYS) += clk-mt6779-img.o
|
||||
|
|
|
|||
100
drivers/clk/mediatek/clk-mt6765-audio.c
Normal file
100
drivers/clk/mediatek/clk-mt6765-audio.c
Normal file
|
|
@ -0,0 +1,100 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
* Author: Owen Chen <owen.chen@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt6765-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs audio0_cg_regs = {
|
||||
.set_ofs = 0x0,
|
||||
.clr_ofs = 0x0,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs audio1_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x4,
|
||||
.sta_ofs = 0x4,
|
||||
};
|
||||
|
||||
#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &audio0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &audio1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate audio_clks[] = {
|
||||
/* AUDIO0 */
|
||||
GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_ck", 2),
|
||||
GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_engen1_ck", 8),
|
||||
GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner",
|
||||
"aud_engen1_ck", 19),
|
||||
GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_ck", 24),
|
||||
GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_ck", 25),
|
||||
GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis",
|
||||
"audio_ck", 26),
|
||||
GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_ck", 27),
|
||||
/* AUDIO1 */
|
||||
GATE_AUDIO1(CLK_AUDIO_I2S1_BCLK, "aud_i2s1_bclk",
|
||||
"audio_ck", 4),
|
||||
GATE_AUDIO1(CLK_AUDIO_I2S2_BCLK, "aud_i2s2_bclk",
|
||||
"audio_ck", 5),
|
||||
GATE_AUDIO1(CLK_AUDIO_I2S3_BCLK, "aud_i2s3_bclk",
|
||||
"audio_ck", 6),
|
||||
GATE_AUDIO1(CLK_AUDIO_I2S4_BCLK, "aud_i2s4_bclk",
|
||||
"audio_ck", 7),
|
||||
};
|
||||
|
||||
static int clk_mt6765_audio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, audio_clks,
|
||||
ARRAY_SIZE(audio_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6765_audio[] = {
|
||||
{ .compatible = "mediatek,mt6765-audsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt6765_audio_drv = {
|
||||
.probe = clk_mt6765_audio_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt6765-audio",
|
||||
.of_match_table = of_match_clk_mt6765_audio,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt6765_audio_drv);
|
||||
74
drivers/clk/mediatek/clk-mt6765-cam.c
Normal file
74
drivers/clk/mediatek/clk-mt6765-cam.c
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
* Author: Owen Chen <owen.chen@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt6765-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs cam_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_CAM(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &cam_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate cam_clks[] = {
|
||||
GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "mm_ck", 0),
|
||||
GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "mm_ck", 1),
|
||||
GATE_CAM(CLK_CAM, "cam", "mm_ck", 6),
|
||||
GATE_CAM(CLK_CAMTG, "camtg", "mm_ck", 7),
|
||||
GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "mm_ck", 8),
|
||||
GATE_CAM(CLK_CAMSV0, "camsv0", "mm_ck", 9),
|
||||
GATE_CAM(CLK_CAMSV1, "camsv1", "mm_ck", 10),
|
||||
GATE_CAM(CLK_CAMSV2, "camsv2", "mm_ck", 11),
|
||||
GATE_CAM(CLK_CAM_CCU, "cam_ccu", "mm_ck", 12),
|
||||
};
|
||||
|
||||
static int clk_mt6765_cam_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6765_cam[] = {
|
||||
{ .compatible = "mediatek,mt6765-camsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt6765_cam_drv = {
|
||||
.probe = clk_mt6765_cam_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt6765-cam",
|
||||
.of_match_table = of_match_clk_mt6765_cam,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt6765_cam_drv);
|
||||
70
drivers/clk/mediatek/clk-mt6765-img.c
Normal file
70
drivers/clk/mediatek/clk-mt6765-img.c
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
* Author: Owen Chen <owen.chen@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt6765-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs img_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_IMG(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &img_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate img_clks[] = {
|
||||
GATE_IMG(CLK_IMG_LARB2, "img_larb2", "mm_ck", 0),
|
||||
GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_ck", 2),
|
||||
GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_ck", 3),
|
||||
GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_ck", 4),
|
||||
GATE_IMG(CLK_IMG_RSC, "img_rsc", "mm_ck", 5),
|
||||
};
|
||||
|
||||
static int clk_mt6765_img_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6765_img[] = {
|
||||
{ .compatible = "mediatek,mt6765-imgsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt6765_img_drv = {
|
||||
.probe = clk_mt6765_img_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt6765-img",
|
||||
.of_match_table = of_match_clk_mt6765_img,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt6765_img_drv);
|
||||
68
drivers/clk/mediatek/clk-mt6765-mipi0a.c
Normal file
68
drivers/clk/mediatek/clk-mt6765-mipi0a.c
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
* Author: Owen Chen <owen.chen@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt6765-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs mipi0a_cg_regs = {
|
||||
.set_ofs = 0x80,
|
||||
.clr_ofs = 0x80,
|
||||
.sta_ofs = 0x80,
|
||||
};
|
||||
|
||||
#define GATE_MIPI0A(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mipi0a_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate mipi0a_clks[] = {
|
||||
GATE_MIPI0A(CLK_MIPI0A_CSR_CSI_EN_0A,
|
||||
"mipi0a_csr_0a", "f_fseninf_ck", 1),
|
||||
};
|
||||
|
||||
static int clk_mt6765_mipi0a_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MIPI0A_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, mipi0a_clks,
|
||||
ARRAY_SIZE(mipi0a_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6765_mipi0a[] = {
|
||||
{ .compatible = "mediatek,mt6765-mipi0a", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt6765_mipi0a_drv = {
|
||||
.probe = clk_mt6765_mipi0a_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt6765-mipi0a",
|
||||
.of_match_table = of_match_clk_mt6765_mipi0a,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt6765_mipi0a_drv);
|
||||
96
drivers/clk/mediatek/clk-mt6765-mm.c
Normal file
96
drivers/clk/mediatek/clk-mt6765-mm.c
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
* Author: Owen Chen <owen.chen@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt6765-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs mm_cg_regs = {
|
||||
.set_ofs = 0x104,
|
||||
.clr_ofs = 0x108,
|
||||
.sta_ofs = 0x100,
|
||||
};
|
||||
|
||||
#define GATE_MM(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mm_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate mm_clks[] = {
|
||||
/* MM */
|
||||
GATE_MM(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_ck", 0),
|
||||
GATE_MM(CLK_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_ck", 1),
|
||||
GATE_MM(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_ck", 2),
|
||||
GATE_MM(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_ck", 3),
|
||||
GATE_MM(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_ck", 4),
|
||||
GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_ck", 5),
|
||||
GATE_MM(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_ck", 6),
|
||||
GATE_MM(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_ck", 7),
|
||||
GATE_MM(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_ck", 8),
|
||||
GATE_MM(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_ck", 9),
|
||||
GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_ck", 10),
|
||||
GATE_MM(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_ck", 11),
|
||||
GATE_MM(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_ck", 12),
|
||||
GATE_MM(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_ck", 13),
|
||||
GATE_MM(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_ck", 14),
|
||||
GATE_MM(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_ck", 15),
|
||||
GATE_MM(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_ck", 16),
|
||||
GATE_MM(CLK_MM_DSI0, "mm_dsi0", "mm_ck", 17),
|
||||
GATE_MM(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_ck", 18),
|
||||
GATE_MM(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_ck", 19),
|
||||
GATE_MM(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_ck", 20),
|
||||
GATE_MM(CLK_MM_SMI_COMM0, "mm_smi_comm0", "mm_ck", 21),
|
||||
GATE_MM(CLK_MM_SMI_COMM1, "mm_smi_comm1", "mm_ck", 22),
|
||||
GATE_MM(CLK_MM_CAM_MDP, "mm_cam_mdp_ck", "mm_ck", 23),
|
||||
GATE_MM(CLK_MM_SMI_IMG, "mm_smi_img_ck", "mm_ck", 24),
|
||||
GATE_MM(CLK_MM_SMI_CAM, "mm_smi_cam_ck", "mm_ck", 25),
|
||||
GATE_MM(CLK_MM_IMG_DL_RELAY, "mm_img_dl_relay", "mm_ck", 26),
|
||||
GATE_MM(CLK_MM_IMG_DL_ASYNC_TOP, "mm_imgdl_async", "mm_ck", 27),
|
||||
GATE_MM(CLK_MM_DIG_DSI, "mm_dig_dsi_ck", "mm_ck", 28),
|
||||
GATE_MM(CLK_MM_F26M_HRTWT, "mm_hrtwt", "f_f26m_ck", 29),
|
||||
};
|
||||
|
||||
static int clk_mt6765_mm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6765_mm[] = {
|
||||
{ .compatible = "mediatek,mt6765-mmsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt6765_mm_drv = {
|
||||
.probe = clk_mt6765_mm_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt6765-mm",
|
||||
.of_match_table = of_match_clk_mt6765_mm,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt6765_mm_drv);
|
||||
70
drivers/clk/mediatek/clk-mt6765-vcodec.c
Normal file
70
drivers/clk/mediatek/clk-mt6765-vcodec.c
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
* Author: Owen Chen <owen.chen@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt6765-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs venc_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_VENC(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &venc_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate venc_clks[] = {
|
||||
GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "mm_ck", 0),
|
||||
GATE_VENC(CLK_VENC_SET1_VENC, "venc_set1_venc", "mm_ck", 4),
|
||||
GATE_VENC(CLK_VENC_SET2_JPGENC, "jpgenc", "mm_ck", 8),
|
||||
GATE_VENC(CLK_VENC_SET3_VDEC, "venc_set3_vdec", "mm_ck", 12),
|
||||
};
|
||||
|
||||
static int clk_mt6765_vcodec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, venc_clks,
|
||||
ARRAY_SIZE(venc_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6765_vcodec[] = {
|
||||
{ .compatible = "mediatek,mt6765-vcodecsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt6765_vcodec_drv = {
|
||||
.probe = clk_mt6765_vcodec_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt6765-vcodec",
|
||||
.of_match_table = of_match_clk_mt6765_vcodec,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt6765_vcodec_drv);
|
||||
952
drivers/clk/mediatek/clk-mt6765.c
Normal file
952
drivers/clk/mediatek/clk-mt6765.c
Normal file
|
|
@ -0,0 +1,952 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
* Author: Owen Chen <owen.chen@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mux.h"
|
||||
|
||||
#include <dt-bindings/clock/mt6765-clk.h>
|
||||
|
||||
/*fmeter div select 4*/
|
||||
#define _DIV4_ 1
|
||||
|
||||
static DEFINE_SPINLOCK(mt6765_clk_lock);
|
||||
|
||||
/* Total 12 subsys */
|
||||
static void __iomem *cksys_base;
|
||||
static void __iomem *apmixed_base;
|
||||
|
||||
/* CKSYS */
|
||||
#define CLK_SCP_CFG_0 (cksys_base + 0x200)
|
||||
#define CLK_SCP_CFG_1 (cksys_base + 0x204)
|
||||
|
||||
/* CG */
|
||||
#define AP_PLL_CON3 (apmixed_base + 0x0C)
|
||||
#define PLLON_CON0 (apmixed_base + 0x44)
|
||||
#define PLLON_CON1 (apmixed_base + 0x48)
|
||||
|
||||
/* clk cfg update */
|
||||
#define CLK_CFG_0 0x40
|
||||
#define CLK_CFG_0_SET 0x44
|
||||
#define CLK_CFG_0_CLR 0x48
|
||||
#define CLK_CFG_1 0x50
|
||||
#define CLK_CFG_1_SET 0x54
|
||||
#define CLK_CFG_1_CLR 0x58
|
||||
#define CLK_CFG_2 0x60
|
||||
#define CLK_CFG_2_SET 0x64
|
||||
#define CLK_CFG_2_CLR 0x68
|
||||
#define CLK_CFG_3 0x70
|
||||
#define CLK_CFG_3_SET 0x74
|
||||
#define CLK_CFG_3_CLR 0x78
|
||||
#define CLK_CFG_4 0x80
|
||||
#define CLK_CFG_4_SET 0x84
|
||||
#define CLK_CFG_4_CLR 0x88
|
||||
#define CLK_CFG_5 0x90
|
||||
#define CLK_CFG_5_SET 0x94
|
||||
#define CLK_CFG_5_CLR 0x98
|
||||
#define CLK_CFG_6 0xa0
|
||||
#define CLK_CFG_6_SET 0xa4
|
||||
#define CLK_CFG_6_CLR 0xa8
|
||||
#define CLK_CFG_7 0xb0
|
||||
#define CLK_CFG_7_SET 0xb4
|
||||
#define CLK_CFG_7_CLR 0xb8
|
||||
#define CLK_CFG_8 0xc0
|
||||
#define CLK_CFG_8_SET 0xc4
|
||||
#define CLK_CFG_8_CLR 0xc8
|
||||
#define CLK_CFG_9 0xd0
|
||||
#define CLK_CFG_9_SET 0xd4
|
||||
#define CLK_CFG_9_CLR 0xd8
|
||||
#define CLK_CFG_10 0xe0
|
||||
#define CLK_CFG_10_SET 0xe4
|
||||
#define CLK_CFG_10_CLR 0xe8
|
||||
#define CLK_CFG_UPDATE 0x004
|
||||
|
||||
static const struct mtk_fixed_clk fixed_clks[] = {
|
||||
FIXED_CLK(CLK_TOP_F_FRTC, "f_frtc_ck", "clk32k", 32768),
|
||||
FIXED_CLK(CLK_TOP_CLK26M, "clk_26m_ck", "clk26m", 26000000),
|
||||
FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 466000000),
|
||||
};
|
||||
|
||||
static const struct mtk_fixed_factor top_divs[] = {
|
||||
FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
|
||||
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
|
||||
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
|
||||
FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
|
||||
FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
|
||||
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
|
||||
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
|
||||
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
|
||||
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
|
||||
FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "univpll", 2, 13),
|
||||
FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4),
|
||||
FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8),
|
||||
FACTOR(CLK_TOP_USB20_192M_D16,
|
||||
"usb20_192m_d16", "usb20_192m_ck", 1, 16),
|
||||
FACTOR(CLK_TOP_USB20_192M_D32,
|
||||
"usb20_192m_d32", "usb20_192m_ck", 1, 32),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
|
||||
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
|
||||
FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
|
||||
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2),
|
||||
FACTOR(CLK_TOP_MPLL, "mpll_ck", "mpll", 1, 1),
|
||||
FACTOR(CLK_TOP_DA_MPLL_104M_DIV, "mpll_104m_div", "mpll_ck", 1, 2),
|
||||
FACTOR(CLK_TOP_DA_MPLL_52M_DIV, "mpll_52m_div", "mpll_ck", 1, 4),
|
||||
FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
|
||||
FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
|
||||
FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
|
||||
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
|
||||
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
|
||||
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8),
|
||||
FACTOR(CLK_TOP_ULPOSC1, "ulposc1_ck", "ulposc1", 1, 1),
|
||||
FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1_ck", 1, 2),
|
||||
FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1_ck", 1, 4),
|
||||
FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1_ck", 1, 8),
|
||||
FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1_ck", 1, 16),
|
||||
FACTOR(CLK_TOP_ULPOSC1_D32, "ulposc1_d32", "ulposc1_ck", 1, 32),
|
||||
FACTOR(CLK_TOP_F_F26M, "f_f26m_ck", "clk_26m_ck", 1, 1),
|
||||
FACTOR(CLK_TOP_AXI, "axi_ck", "axi_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_MM, "mm_ck", "mm_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_SCP, "scp_ck", "scp_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_MFG, "mfg_ck", "mfg_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_SPI, "spi_ck", "spi_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck", "msdc50_0_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_AUDIO, "audio_ck", "audio_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_AUD_1, "aud_1_ck", "aud_1_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_AUD_ENGEN1, "aud_engen1_ck", "aud_engen1_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_F_FDISP_PWM, "f_fdisp_pwm_ck", "disp_pwm_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_SSPM, "sspm_ck", "sspm_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_DXCC, "dxcc_ck", "dxcc_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_I2C, "i2c_ck", "i2c_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_F_FPWM, "f_fpwm_ck", "pwm_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_F_FSENINF, "f_fseninf_ck", "seninf_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_AES_FDE, "aes_fde_ck", "aes_fde_sel", 1, 1),
|
||||
FACTOR(CLK_TOP_F_BIST2FPC, "f_bist2fpc_ck", "univpll2_d2", 1, 1),
|
||||
FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL0, "arm_div_pll0", "syspll_d2", 1, 1),
|
||||
FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL1, "arm_div_pll1", "syspll_ck", 1, 1),
|
||||
FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL2, "arm_div_pll2", "univpll_d2", 1, 1),
|
||||
FACTOR(CLK_TOP_DA_USB20_48M_DIV,
|
||||
"usb20_48m_div", "usb20_192m_d4", 1, 1),
|
||||
FACTOR(CLK_TOP_DA_UNIV_48M_DIV, "univ_48m_div", "usb20_192m_d4", 1, 1),
|
||||
};
|
||||
|
||||
static const char * const axi_parents[] = {
|
||||
"clk26m",
|
||||
"syspll_d7",
|
||||
"syspll1_d4",
|
||||
"syspll3_d2"
|
||||
};
|
||||
|
||||
static const char * const mem_parents[] = {
|
||||
"clk26m",
|
||||
"dmpll_ck",
|
||||
"apll1_ck"
|
||||
};
|
||||
|
||||
static const char * const mm_parents[] = {
|
||||
"clk26m",
|
||||
"mmpll_ck",
|
||||
"syspll1_d2",
|
||||
"syspll_d5",
|
||||
"syspll1_d4",
|
||||
"univpll_d5",
|
||||
"univpll1_d2",
|
||||
"mmpll_d2"
|
||||
};
|
||||
|
||||
static const char * const scp_parents[] = {
|
||||
"clk26m",
|
||||
"syspll4_d2",
|
||||
"univpll2_d2",
|
||||
"syspll1_d2",
|
||||
"univpll1_d2",
|
||||
"syspll_d3",
|
||||
"univpll_d3"
|
||||
};
|
||||
|
||||
static const char * const mfg_parents[] = {
|
||||
"clk26m",
|
||||
"mfgpll_ck",
|
||||
"syspll_d3",
|
||||
"univpll_d3"
|
||||
};
|
||||
|
||||
static const char * const atb_parents[] = {
|
||||
"clk26m",
|
||||
"syspll1_d4",
|
||||
"syspll1_d2"
|
||||
};
|
||||
|
||||
static const char * const camtg_parents[] = {
|
||||
"clk26m",
|
||||
"usb20_192m_d8",
|
||||
"univpll2_d8",
|
||||
"usb20_192m_d4",
|
||||
"univpll2_d32",
|
||||
"usb20_192m_d16",
|
||||
"usb20_192m_d32"
|
||||
};
|
||||
|
||||
static const char * const uart_parents[] = {
|
||||
"clk26m",
|
||||
"univpll2_d8"
|
||||
};
|
||||
|
||||
static const char * const spi_parents[] = {
|
||||
"clk26m",
|
||||
"syspll3_d2",
|
||||
"syspll4_d2",
|
||||
"syspll2_d4"
|
||||
};
|
||||
|
||||
static const char * const msdc5hclk_parents[] = {
|
||||
"clk26m",
|
||||
"syspll1_d2",
|
||||
"univpll1_d4",
|
||||
"syspll2_d2"
|
||||
};
|
||||
|
||||
static const char * const msdc50_0_parents[] = {
|
||||
"clk26m",
|
||||
"msdcpll_ck",
|
||||
"syspll2_d2",
|
||||
"syspll4_d2",
|
||||
"univpll1_d2",
|
||||
"syspll1_d2",
|
||||
"univpll_d5",
|
||||
"univpll1_d4"
|
||||
};
|
||||
|
||||
static const char * const msdc30_1_parents[] = {
|
||||
"clk26m",
|
||||
"msdcpll_d2",
|
||||
"univpll2_d2",
|
||||
"syspll2_d2",
|
||||
"syspll1_d4",
|
||||
"univpll1_d4",
|
||||
"usb20_192m_d4",
|
||||
"syspll2_d4"
|
||||
};
|
||||
|
||||
static const char * const audio_parents[] = {
|
||||
"clk26m",
|
||||
"syspll3_d4",
|
||||
"syspll4_d4",
|
||||
"syspll1_d16"
|
||||
};
|
||||
|
||||
static const char * const aud_intbus_parents[] = {
|
||||
"clk26m",
|
||||
"syspll1_d4",
|
||||
"syspll4_d2"
|
||||
};
|
||||
|
||||
static const char * const aud_1_parents[] = {
|
||||
"clk26m",
|
||||
"apll1_ck"
|
||||
};
|
||||
|
||||
static const char * const aud_engen1_parents[] = {
|
||||
"clk26m",
|
||||
"apll1_d2",
|
||||
"apll1_d4",
|
||||
"apll1_d8"
|
||||
};
|
||||
|
||||
static const char * const disp_pwm_parents[] = {
|
||||
"clk26m",
|
||||
"univpll2_d4",
|
||||
"ulposc1_d2",
|
||||
"ulposc1_d8"
|
||||
};
|
||||
|
||||
static const char * const sspm_parents[] = {
|
||||
"clk26m",
|
||||
"syspll1_d2",
|
||||
"syspll_d3"
|
||||
};
|
||||
|
||||
static const char * const dxcc_parents[] = {
|
||||
"clk26m",
|
||||
"syspll1_d2",
|
||||
"syspll1_d4",
|
||||
"syspll1_d8"
|
||||
};
|
||||
|
||||
static const char * const usb_top_parents[] = {
|
||||
"clk26m",
|
||||
"univpll3_d4"
|
||||
};
|
||||
|
||||
static const char * const spm_parents[] = {
|
||||
"clk26m",
|
||||
"syspll1_d8"
|
||||
};
|
||||
|
||||
static const char * const i2c_parents[] = {
|
||||
"clk26m",
|
||||
"univpll3_d4",
|
||||
"univpll3_d2",
|
||||
"syspll1_d8",
|
||||
"syspll2_d8"
|
||||
};
|
||||
|
||||
static const char * const pwm_parents[] = {
|
||||
"clk26m",
|
||||
"univpll3_d4",
|
||||
"syspll1_d8"
|
||||
};
|
||||
|
||||
static const char * const seninf_parents[] = {
|
||||
"clk26m",
|
||||
"univpll1_d4",
|
||||
"univpll1_d2",
|
||||
"univpll2_d2"
|
||||
};
|
||||
|
||||
static const char * const aes_fde_parents[] = {
|
||||
"clk26m",
|
||||
"msdcpll_ck",
|
||||
"univpll_d3",
|
||||
"univpll2_d2",
|
||||
"univpll1_d2",
|
||||
"syspll1_d2"
|
||||
};
|
||||
|
||||
static const char * const ulposc_parents[] = {
|
||||
"clk26m",
|
||||
"ulposc1_d4",
|
||||
"ulposc1_d8",
|
||||
"ulposc1_d16",
|
||||
"ulposc1_d32"
|
||||
};
|
||||
|
||||
static const char * const camtm_parents[] = {
|
||||
"clk26m",
|
||||
"univpll1_d4",
|
||||
"univpll1_d2",
|
||||
"univpll2_d2"
|
||||
};
|
||||
|
||||
#define INVALID_UPDATE_REG 0xFFFFFFFF
|
||||
#define INVALID_UPDATE_SHIFT -1
|
||||
#define INVALID_MUX_GATE -1
|
||||
|
||||
static const struct mtk_mux top_muxes[] = {
|
||||
/* CLK_CFG_0 */
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
|
||||
CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
|
||||
0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
|
||||
CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
|
||||
8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
|
||||
CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,
|
||||
CLK_CFG_UPDATE, 2),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
|
||||
CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31,
|
||||
CLK_CFG_UPDATE, 3),
|
||||
/* CLK_CFG_1 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1,
|
||||
CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7,
|
||||
CLK_CFG_UPDATE, 4),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1,
|
||||
CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 2, 15,
|
||||
CLK_CFG_UPDATE, 5),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
|
||||
camtg_parents, CLK_CFG_1, CLK_CFG_1_SET,
|
||||
CLK_CFG_1_CLR, 16, 3, 23, CLK_CFG_UPDATE, 6),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
|
||||
CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR,
|
||||
24, 3, 31, CLK_CFG_UPDATE, 7),
|
||||
/* CLK_CFG_2 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
|
||||
camtg_parents, CLK_CFG_2, CLK_CFG_2_SET,
|
||||
CLK_CFG_2_CLR, 0, 3, 7, CLK_CFG_UPDATE, 8),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg_parents,
|
||||
CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR,
|
||||
8, 3, 15, CLK_CFG_UPDATE, 9),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
|
||||
CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 1, 23,
|
||||
CLK_CFG_UPDATE, 10),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
|
||||
CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31,
|
||||
CLK_CFG_UPDATE, 11),
|
||||
/* CLK_CFG_3 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
|
||||
msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET,
|
||||
CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
|
||||
msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET,
|
||||
CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
|
||||
msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET,
|
||||
CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
|
||||
CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR,
|
||||
24, 2, 31, CLK_CFG_UPDATE, 15),
|
||||
/* CLK_CFG_4 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
|
||||
aud_intbus_parents, CLK_CFG_4, CLK_CFG_4_SET,
|
||||
CLK_CFG_4_CLR, 0, 2, 7, CLK_CFG_UPDATE, 16),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
|
||||
CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR,
|
||||
8, 1, 15, CLK_CFG_UPDATE, 17),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
|
||||
aud_engen1_parents, CLK_CFG_4, CLK_CFG_4_SET,
|
||||
CLK_CFG_4_CLR, 16, 2, 23, CLK_CFG_UPDATE, 18),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
|
||||
disp_pwm_parents, CLK_CFG_4, CLK_CFG_4_SET,
|
||||
CLK_CFG_4_CLR, 24, 2, 31, CLK_CFG_UPDATE, 19),
|
||||
/* CLK_CFG_5 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM_SEL, "sspm_sel", sspm_parents,
|
||||
CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7,
|
||||
CLK_CFG_UPDATE, 20),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
|
||||
CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 2, 15,
|
||||
CLK_CFG_UPDATE, 21),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel",
|
||||
usb_top_parents, CLK_CFG_5, CLK_CFG_5_SET,
|
||||
CLK_CFG_5_CLR, 16, 1, 23, CLK_CFG_UPDATE, 22),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, CLK_CFG_5,
|
||||
CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 1, 31,
|
||||
CLK_CFG_UPDATE, 23),
|
||||
/* CLK_CFG_6 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, CLK_CFG_6,
|
||||
CLK_CFG_6_SET, CLK_CFG_6_CLR, 0, 3, 7, CLK_CFG_UPDATE,
|
||||
24),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, CLK_CFG_6,
|
||||
CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 2, 15, CLK_CFG_UPDATE,
|
||||
25),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", seninf_parents,
|
||||
CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 2, 23,
|
||||
CLK_CFG_UPDATE, 26),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel",
|
||||
aes_fde_parents, CLK_CFG_6, CLK_CFG_6_SET,
|
||||
CLK_CFG_6_CLR, 24, 3, 31, CLK_CFG_UPDATE, 27),
|
||||
/* CLK_CFG_7 */
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRAP_ULPOSC_SEL, "ulposc_sel",
|
||||
ulposc_parents, CLK_CFG_7, CLK_CFG_7_SET,
|
||||
CLK_CFG_7_CLR, 0, 3, 7, CLK_CFG_UPDATE, 28,
|
||||
CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", camtm_parents,
|
||||
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15,
|
||||
CLK_CFG_UPDATE, 29),
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs top0_cg_regs = {
|
||||
.set_ofs = 0x0,
|
||||
.clr_ofs = 0x0,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs top1_cg_regs = {
|
||||
.set_ofs = 0x104,
|
||||
.clr_ofs = 0x104,
|
||||
.sta_ofs = 0x104,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs top2_cg_regs = {
|
||||
.set_ofs = 0x320,
|
||||
.clr_ofs = 0x320,
|
||||
.sta_ofs = 0x320,
|
||||
};
|
||||
|
||||
#define GATE_TOP0(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &top0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_TOP1(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &top1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
#define GATE_TOP2(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &top2_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate top_clks[] = {
|
||||
/* TOP0 */
|
||||
GATE_TOP0(CLK_TOP_MD_32K, "md_32k", "f_frtc_ck", 8),
|
||||
GATE_TOP0(CLK_TOP_MD_26M, "md_26m", "f_f26m_ck", 9),
|
||||
GATE_TOP0(CLK_TOP_MD2_32K, "md2_32k", "f_frtc_ck", 10),
|
||||
GATE_TOP0(CLK_TOP_MD2_26M, "md2_26m", "f_f26m_ck", 11),
|
||||
/* TOP1 */
|
||||
GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL0_EN,
|
||||
"arm_div_pll0_en", "arm_div_pll0", 3),
|
||||
GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL1_EN,
|
||||
"arm_div_pll1_en", "arm_div_pll1", 4),
|
||||
GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL2_EN,
|
||||
"arm_div_pll2_en", "arm_div_pll2", 5),
|
||||
GATE_TOP1(CLK_TOP_FMEM_OCC_DRC_EN, "drc_en", "univpll2_d2", 6),
|
||||
GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_48m_div", 8),
|
||||
GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "univ_48m_div", 9),
|
||||
GATE_TOP1(CLK_TOP_F_UFS_MP_SAP_CFG_EN, "ufs_sap", "f_f26m_ck", 12),
|
||||
GATE_TOP1(CLK_TOP_F_BIST2FPC_EN, "bist2fpc", "f_bist2fpc_ck", 16),
|
||||
/* TOP2 */
|
||||
GATE_TOP2(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2),
|
||||
GATE_TOP2(CLK_TOP_APLL12_DIV1, "apll12_div1", "aud_1_ck", 3),
|
||||
GATE_TOP2(CLK_TOP_APLL12_DIV2, "apll12_div2", "aud_1_ck", 4),
|
||||
GATE_TOP2(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5),
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs ifr0_cg_regs = {
|
||||
.set_ofs = 0x200,
|
||||
.clr_ofs = 0x200,
|
||||
.sta_ofs = 0x200,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs ifr1_cg_regs = {
|
||||
.set_ofs = 0x74,
|
||||
.clr_ofs = 0x74,
|
||||
.sta_ofs = 0x74,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs ifr2_cg_regs = {
|
||||
.set_ofs = 0x80,
|
||||
.clr_ofs = 0x84,
|
||||
.sta_ofs = 0x90,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs ifr3_cg_regs = {
|
||||
.set_ofs = 0x88,
|
||||
.clr_ofs = 0x8c,
|
||||
.sta_ofs = 0x94,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs ifr4_cg_regs = {
|
||||
.set_ofs = 0xa4,
|
||||
.clr_ofs = 0xa8,
|
||||
.sta_ofs = 0xac,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs ifr5_cg_regs = {
|
||||
.set_ofs = 0xc0,
|
||||
.clr_ofs = 0xc4,
|
||||
.sta_ofs = 0xc8,
|
||||
};
|
||||
|
||||
#define GATE_IFR0(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &ifr0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
#define GATE_IFR1(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &ifr1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_IFR2(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &ifr2_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_IFR3(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &ifr3_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_IFR4(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &ifr4_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_IFR5(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &ifr5_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate ifr_clks[] = {
|
||||
/* INFRA_TOPAXI */
|
||||
/* INFRA PERI */
|
||||
/* INFRA mode 0 */
|
||||
GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_ck", 8),
|
||||
GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_ck", 9),
|
||||
GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_ck", 10),
|
||||
GATE_IFR2(CLK_IFR_I2C_AP, "ifr_i2c_ap", "i2c_ck", 11),
|
||||
GATE_IFR2(CLK_IFR_I2C_CCU, "ifr_i2c_ccu", "i2c_ck", 12),
|
||||
GATE_IFR2(CLK_IFR_I2C_SSPM, "ifr_i2c_sspm", "i2c_ck", 13),
|
||||
GATE_IFR2(CLK_IFR_I2C_RSV, "ifr_i2c_rsv", "i2c_ck", 14),
|
||||
GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_ck", 15),
|
||||
GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "f_fpwm_ck", 16),
|
||||
GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "f_fpwm_ck", 17),
|
||||
GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "f_fpwm_ck", 18),
|
||||
GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "f_fpwm_ck", 19),
|
||||
GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "f_fpwm_ck", 20),
|
||||
GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "f_fpwm_ck", 21),
|
||||
GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "f_fuart_ck", 22),
|
||||
GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "f_fuart_ck", 23),
|
||||
GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "f_f26m_ck", 27),
|
||||
GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_dma", "axi_ck", 28),
|
||||
GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_ck", 31),
|
||||
/* INFRA mode 1 */
|
||||
GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_ck", 1),
|
||||
GATE_IFR3(CLK_IFR_MSDC0, "ifr_msdc0", "msdc5hclk", 2),
|
||||
GATE_IFR3(CLK_IFR_MSDC1, "ifr_msdc1", "axi_ck", 4),
|
||||
GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_ck", 9),
|
||||
GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "f_f26m_ck", 10),
|
||||
GATE_IFR3(CLK_IFR_CCIF1_AP, "ifr_ccif1_ap", "axi_ck", 12),
|
||||
GATE_IFR3(CLK_IFR_CCIF1_MD, "ifr_ccif1_md", "axi_ck", 13),
|
||||
GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "f_f26m_ck", 14),
|
||||
GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_ck", 18),
|
||||
GATE_IFR3(CLK_IFR_DEVICE_APC, "ifr_dapc", "axi_ck", 20),
|
||||
GATE_IFR3(CLK_IFR_CCIF_AP, "ifr_ccif_ap", "axi_ck", 23),
|
||||
GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_ck", 25),
|
||||
GATE_IFR3(CLK_IFR_CCIF_MD, "ifr_ccif_md", "axi_ck", 26),
|
||||
/* INFRA mode 2 */
|
||||
GATE_IFR4(CLK_IFR_RG_PWM_FBCLK6, "ifr_pwmfb", "f_f26m_ck", 0),
|
||||
GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "f_fdisp_pwm_ck", 2),
|
||||
GATE_IFR4(CLK_IFR_CLDMA_BCLK, "ifr_cldmabclk", "axi_ck", 3),
|
||||
GATE_IFR4(CLK_IFR_AUDIO_26M_BCLK, "ifr_audio26m", "f_f26m_ck", 4),
|
||||
GATE_IFR4(CLK_IFR_SPI1, "ifr_spi1", "spi_ck", 6),
|
||||
GATE_IFR4(CLK_IFR_I2C4, "ifr_i2c4", "i2c_ck", 7),
|
||||
GATE_IFR4(CLK_IFR_SPI2, "ifr_spi2", "spi_ck", 9),
|
||||
GATE_IFR4(CLK_IFR_SPI3, "ifr_spi3", "spi_ck", 10),
|
||||
GATE_IFR4(CLK_IFR_I2C5, "ifr_i2c5", "i2c_ck", 18),
|
||||
GATE_IFR4(CLK_IFR_I2C5_ARBITER, "ifr_i2c5a", "i2c_ck", 19),
|
||||
GATE_IFR4(CLK_IFR_I2C5_IMM, "ifr_i2c5_imm", "i2c_ck", 20),
|
||||
GATE_IFR4(CLK_IFR_I2C1_ARBITER, "ifr_i2c1a", "i2c_ck", 21),
|
||||
GATE_IFR4(CLK_IFR_I2C1_IMM, "ifr_i2c1_imm", "i2c_ck", 22),
|
||||
GATE_IFR4(CLK_IFR_I2C2_ARBITER, "ifr_i2c2a", "i2c_ck", 23),
|
||||
GATE_IFR4(CLK_IFR_I2C2_IMM, "ifr_i2c2_imm", "i2c_ck", 24),
|
||||
GATE_IFR4(CLK_IFR_SPI4, "ifr_spi4", "spi_ck", 25),
|
||||
GATE_IFR4(CLK_IFR_SPI5, "ifr_spi5", "spi_ck", 26),
|
||||
GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_ck", 27),
|
||||
GATE_IFR4(CLK_IFR_FAES_FDE, "ifr_faes_fde_ck", "aes_fde_ck", 29),
|
||||
/* INFRA mode 3 */
|
||||
GATE_IFR5(CLK_IFR_MSDC0_SELF, "ifr_msdc0sf", "msdc50_0_ck", 0),
|
||||
GATE_IFR5(CLK_IFR_MSDC1_SELF, "ifr_msdc1sf", "msdc50_0_ck", 1),
|
||||
GATE_IFR5(CLK_IFR_I2C6, "ifr_i2c6", "i2c_ck", 6),
|
||||
GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_ck", 7),
|
||||
GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_ck", 8),
|
||||
GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_clk", "msdc50_0_ck", 9),
|
||||
GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_clk", "msdc30_1_ck", 10),
|
||||
GATE_IFR5(CLK_IFR_MCU_PM_BCLK, "ifr_mcu_pm_bclk", "axi_ck", 17),
|
||||
GATE_IFR5(CLK_IFR_CCIF2_AP, "ifr_ccif2_ap", "axi_ck", 18),
|
||||
GATE_IFR5(CLK_IFR_CCIF2_MD, "ifr_ccif2_md", "axi_ck", 19),
|
||||
GATE_IFR5(CLK_IFR_CCIF3_AP, "ifr_ccif3_ap", "axi_ck", 20),
|
||||
GATE_IFR5(CLK_IFR_CCIF3_MD, "ifr_ccif3_md", "axi_ck", 21),
|
||||
};
|
||||
|
||||
/* additional CCF control for mipi26M race condition(disp/camera) */
|
||||
static const struct mtk_gate_regs apmixed_cg_regs = {
|
||||
.set_ofs = 0x14,
|
||||
.clr_ofs = 0x14,
|
||||
.sta_ofs = 0x14,
|
||||
};
|
||||
|
||||
#define GATE_APMIXED(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &apmixed_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate apmixed_clks[] = {
|
||||
/* AUDIO0 */
|
||||
GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m", "f_f26m_ck",
|
||||
4),
|
||||
GATE_APMIXED(CLK_APMIXED_APPLL26M, "apmixed_appll26m", "f_f26m_ck",
|
||||
5),
|
||||
GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", "f_f26m_ck",
|
||||
6),
|
||||
GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m", "f_f26m_ck",
|
||||
7),
|
||||
GATE_APMIXED(CLK_APMIXED_MMSYS_F26M, "apmixed_mmsys26m", "f_f26m_ck",
|
||||
8),
|
||||
GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m", "f_f26m_ck",
|
||||
9),
|
||||
GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", "f_f26m_ck",
|
||||
11),
|
||||
GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m", "f_f26m_ck",
|
||||
13),
|
||||
GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
|
||||
"f_f26m_ck", 14),
|
||||
GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", "f_f26m_ck",
|
||||
16),
|
||||
};
|
||||
|
||||
#define MT6765_PLL_FMAX (3800UL * MHZ)
|
||||
#define MT6765_PLL_FMIN (1500UL * MHZ)
|
||||
|
||||
#define CON0_MT6765_RST_BAR BIT(23)
|
||||
|
||||
#define PLL_INFO_NULL (0xFF)
|
||||
|
||||
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
|
||||
_pcwibits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,\
|
||||
_tuner_en_bit, _pcw_reg, _pcw_shift, _div_table) {\
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.reg = _reg, \
|
||||
.pwr_reg = _pwr_reg, \
|
||||
.en_mask = _en_mask, \
|
||||
.flags = _flags, \
|
||||
.rst_bar_mask = CON0_MT6765_RST_BAR, \
|
||||
.fmax = MT6765_PLL_FMAX, \
|
||||
.fmin = MT6765_PLL_FMIN, \
|
||||
.pcwbits = _pcwbits, \
|
||||
.pcwibits = _pcwibits, \
|
||||
.pd_reg = _pd_reg, \
|
||||
.pd_shift = _pd_shift, \
|
||||
.tuner_reg = _tuner_reg, \
|
||||
.tuner_en_reg = _tuner_en_reg, \
|
||||
.tuner_en_bit = _tuner_en_bit, \
|
||||
.pcw_reg = _pcw_reg, \
|
||||
.pcw_shift = _pcw_shift, \
|
||||
.div_table = _div_table, \
|
||||
}
|
||||
|
||||
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
|
||||
_pcwibits, _pd_reg, _pd_shift, _tuner_reg, \
|
||||
_tuner_en_reg, _tuner_en_bit, _pcw_reg, \
|
||||
_pcw_shift) \
|
||||
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
|
||||
_pcwbits, _pcwibits, _pd_reg, _pd_shift, \
|
||||
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
|
||||
_pcw_reg, _pcw_shift, NULL) \
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, BIT(0),
|
||||
PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0),
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, BIT(0),
|
||||
PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0),
|
||||
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, BIT(0),
|
||||
PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, BIT(0),
|
||||
(HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240,
|
||||
0),
|
||||
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, BIT(0),
|
||||
0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, BIT(0),
|
||||
0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0),
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, BIT(0),
|
||||
HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, BIT(0),
|
||||
0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, BIT(0),
|
||||
0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0),
|
||||
PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, BIT(0),
|
||||
PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0),
|
||||
};
|
||||
|
||||
static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
void __iomem *base;
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base)) {
|
||||
pr_err("%s(): ioremap failed\n", __func__);
|
||||
return PTR_ERR(base);
|
||||
}
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
|
||||
|
||||
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
|
||||
|
||||
mtk_clk_register_gates(node, apmixed_clks,
|
||||
ARRAY_SIZE(apmixed_clks), clk_data);
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
apmixed_base = base;
|
||||
/* MPLL, CCIPLL, MAINPLL set HW mode, TDCLKSQ, CLKSQ1 */
|
||||
writel(readl(AP_PLL_CON3) & 0xFFFFFFE1, AP_PLL_CON3);
|
||||
writel(readl(PLLON_CON0) & 0x01041041, PLLON_CON0);
|
||||
writel(readl(PLLON_CON1) & 0x01041041, PLLON_CON1);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int clk_mt6765_top_probe(struct platform_device *pdev)
|
||||
{
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
void __iomem *base;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base)) {
|
||||
pr_err("%s(): ioremap failed\n", __func__);
|
||||
return PTR_ERR(base);
|
||||
}
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
|
||||
|
||||
mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
|
||||
clk_data);
|
||||
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
|
||||
clk_data);
|
||||
mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
|
||||
&mt6765_clk_lock, clk_data);
|
||||
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
cksys_base = base;
|
||||
/* [4]:no need */
|
||||
writel(readl(CLK_SCP_CFG_0) | 0x3EF, CLK_SCP_CFG_0);
|
||||
/*[1,2,3,8]: no need*/
|
||||
writel(readl(CLK_SCP_CFG_1) | 0x1, CLK_SCP_CFG_1);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int clk_mt6765_ifr_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
void __iomem *base;
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base)) {
|
||||
pr_err("%s(): ioremap failed\n", __func__);
|
||||
return PTR_ERR(base);
|
||||
}
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks),
|
||||
clk_data);
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6765[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt6765-apmixedsys",
|
||||
.data = clk_mt6765_apmixed_probe,
|
||||
}, {
|
||||
.compatible = "mediatek,mt6765-topckgen",
|
||||
.data = clk_mt6765_top_probe,
|
||||
}, {
|
||||
.compatible = "mediatek,mt6765-infracfg",
|
||||
.data = clk_mt6765_ifr_probe,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static int clk_mt6765_probe(struct platform_device *pdev)
|
||||
{
|
||||
int (*clk_probe)(struct platform_device *d);
|
||||
int r;
|
||||
|
||||
clk_probe = of_device_get_match_data(&pdev->dev);
|
||||
if (!clk_probe)
|
||||
return -EINVAL;
|
||||
|
||||
r = clk_probe(pdev);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6765_drv = {
|
||||
.probe = clk_mt6765_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt6765",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_clk_mt6765,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init clk_mt6765_init(void)
|
||||
{
|
||||
return platform_driver_register(&clk_mt6765_drv);
|
||||
}
|
||||
|
||||
arch_initcall(clk_mt6765_init);
|
||||
|
|
@ -160,7 +160,7 @@ struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
|
|||
spinlock_t *lock)
|
||||
{
|
||||
struct mtk_clk_mux *clk_mux;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
struct clk *clk;
|
||||
|
||||
clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);
|
||||
|
|
|
|||
48
include/dt-bindings/clock/bt1-ccu.h
Normal file
48
include/dt-bindings/clock/bt1-ccu.h
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
*
|
||||
* Baikal-T1 CCU clock indices
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H
|
||||
#define __DT_BINDINGS_CLOCK_BT1_CCU_H
|
||||
|
||||
#define CCU_CPU_PLL 0
|
||||
#define CCU_SATA_PLL 1
|
||||
#define CCU_DDR_PLL 2
|
||||
#define CCU_PCIE_PLL 3
|
||||
#define CCU_ETH_PLL 4
|
||||
|
||||
#define CCU_AXI_MAIN_CLK 0
|
||||
#define CCU_AXI_DDR_CLK 1
|
||||
#define CCU_AXI_SATA_CLK 2
|
||||
#define CCU_AXI_GMAC0_CLK 3
|
||||
#define CCU_AXI_GMAC1_CLK 4
|
||||
#define CCU_AXI_XGMAC_CLK 5
|
||||
#define CCU_AXI_PCIE_M_CLK 6
|
||||
#define CCU_AXI_PCIE_S_CLK 7
|
||||
#define CCU_AXI_USB_CLK 8
|
||||
#define CCU_AXI_HWA_CLK 9
|
||||
#define CCU_AXI_SRAM_CLK 10
|
||||
|
||||
#define CCU_SYS_SATA_REF_CLK 0
|
||||
#define CCU_SYS_APB_CLK 1
|
||||
#define CCU_SYS_GMAC0_TX_CLK 2
|
||||
#define CCU_SYS_GMAC0_PTP_CLK 3
|
||||
#define CCU_SYS_GMAC1_TX_CLK 4
|
||||
#define CCU_SYS_GMAC1_PTP_CLK 5
|
||||
#define CCU_SYS_XGMAC_REF_CLK 6
|
||||
#define CCU_SYS_XGMAC_PTP_CLK 7
|
||||
#define CCU_SYS_USB_CLK 8
|
||||
#define CCU_SYS_PVT_CLK 9
|
||||
#define CCU_SYS_HWA_CLK 10
|
||||
#define CCU_SYS_UART_CLK 11
|
||||
#define CCU_SYS_I2C1_CLK 12
|
||||
#define CCU_SYS_I2C2_CLK 13
|
||||
#define CCU_SYS_GPIO_CLK 14
|
||||
#define CCU_SYS_TIMER0_CLK 15
|
||||
#define CCU_SYS_TIMER1_CLK 16
|
||||
#define CCU_SYS_TIMER2_CLK 17
|
||||
#define CCU_SYS_WDT_CLK 18
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */
|
||||
313
include/dt-bindings/clock/mt6765-clk.h
Normal file
313
include/dt-bindings/clock/mt6765-clk.h
Normal file
|
|
@ -0,0 +1,313 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MT6765_H
|
||||
#define _DT_BINDINGS_CLK_MT6765_H
|
||||
|
||||
/* FIX Clks */
|
||||
#define CLK_TOP_CLK26M 0
|
||||
|
||||
/* APMIXEDSYS */
|
||||
#define CLK_APMIXED_ARMPLL_L 0
|
||||
#define CLK_APMIXED_ARMPLL 1
|
||||
#define CLK_APMIXED_CCIPLL 2
|
||||
#define CLK_APMIXED_MAINPLL 3
|
||||
#define CLK_APMIXED_MFGPLL 4
|
||||
#define CLK_APMIXED_MMPLL 5
|
||||
#define CLK_APMIXED_UNIV2PLL 6
|
||||
#define CLK_APMIXED_MSDCPLL 7
|
||||
#define CLK_APMIXED_APLL1 8
|
||||
#define CLK_APMIXED_MPLL 9
|
||||
#define CLK_APMIXED_ULPOSC1 10
|
||||
#define CLK_APMIXED_ULPOSC2 11
|
||||
#define CLK_APMIXED_SSUSB26M 12
|
||||
#define CLK_APMIXED_APPLL26M 13
|
||||
#define CLK_APMIXED_MIPIC0_26M 14
|
||||
#define CLK_APMIXED_MDPLLGP26M 15
|
||||
#define CLK_APMIXED_MMSYS_F26M 16
|
||||
#define CLK_APMIXED_UFS26M 17
|
||||
#define CLK_APMIXED_MIPIC1_26M 18
|
||||
#define CLK_APMIXED_MEMPLL26M 19
|
||||
#define CLK_APMIXED_CLKSQ_LVPLL_26M 20
|
||||
#define CLK_APMIXED_MIPID0_26M 21
|
||||
#define CLK_APMIXED_NR_CLK 22
|
||||
|
||||
/* TOPCKGEN */
|
||||
#define CLK_TOP_SYSPLL 0
|
||||
#define CLK_TOP_SYSPLL_D2 1
|
||||
#define CLK_TOP_SYSPLL1_D2 2
|
||||
#define CLK_TOP_SYSPLL1_D4 3
|
||||
#define CLK_TOP_SYSPLL1_D8 4
|
||||
#define CLK_TOP_SYSPLL1_D16 5
|
||||
#define CLK_TOP_SYSPLL_D3 6
|
||||
#define CLK_TOP_SYSPLL2_D2 7
|
||||
#define CLK_TOP_SYSPLL2_D4 8
|
||||
#define CLK_TOP_SYSPLL2_D8 9
|
||||
#define CLK_TOP_SYSPLL_D5 10
|
||||
#define CLK_TOP_SYSPLL3_D2 11
|
||||
#define CLK_TOP_SYSPLL3_D4 12
|
||||
#define CLK_TOP_SYSPLL_D7 13
|
||||
#define CLK_TOP_SYSPLL4_D2 14
|
||||
#define CLK_TOP_SYSPLL4_D4 15
|
||||
#define CLK_TOP_USB20_192M 16
|
||||
#define CLK_TOP_USB20_192M_D4 17
|
||||
#define CLK_TOP_USB20_192M_D8 18
|
||||
#define CLK_TOP_USB20_192M_D16 19
|
||||
#define CLK_TOP_USB20_192M_D32 20
|
||||
#define CLK_TOP_UNIVPLL 21
|
||||
#define CLK_TOP_UNIVPLL_D2 22
|
||||
#define CLK_TOP_UNIVPLL1_D2 23
|
||||
#define CLK_TOP_UNIVPLL1_D4 24
|
||||
#define CLK_TOP_UNIVPLL_D3 25
|
||||
#define CLK_TOP_UNIVPLL2_D2 26
|
||||
#define CLK_TOP_UNIVPLL2_D4 27
|
||||
#define CLK_TOP_UNIVPLL2_D8 28
|
||||
#define CLK_TOP_UNIVPLL2_D32 29
|
||||
#define CLK_TOP_UNIVPLL_D5 30
|
||||
#define CLK_TOP_UNIVPLL3_D2 31
|
||||
#define CLK_TOP_UNIVPLL3_D4 32
|
||||
#define CLK_TOP_MMPLL 33
|
||||
#define CLK_TOP_MMPLL_D2 34
|
||||
#define CLK_TOP_MPLL 35
|
||||
#define CLK_TOP_DA_MPLL_104M_DIV 36
|
||||
#define CLK_TOP_DA_MPLL_52M_DIV 37
|
||||
#define CLK_TOP_MFGPLL 38
|
||||
#define CLK_TOP_MSDCPLL 39
|
||||
#define CLK_TOP_MSDCPLL_D2 40
|
||||
#define CLK_TOP_APLL1 41
|
||||
#define CLK_TOP_APLL1_D2 42
|
||||
#define CLK_TOP_APLL1_D4 43
|
||||
#define CLK_TOP_APLL1_D8 44
|
||||
#define CLK_TOP_ULPOSC1 45
|
||||
#define CLK_TOP_ULPOSC1_D2 46
|
||||
#define CLK_TOP_ULPOSC1_D4 47
|
||||
#define CLK_TOP_ULPOSC1_D8 48
|
||||
#define CLK_TOP_ULPOSC1_D16 49
|
||||
#define CLK_TOP_ULPOSC1_D32 50
|
||||
#define CLK_TOP_DMPLL 51
|
||||
#define CLK_TOP_F_FRTC 52
|
||||
#define CLK_TOP_F_F26M 53
|
||||
#define CLK_TOP_AXI 54
|
||||
#define CLK_TOP_MM 55
|
||||
#define CLK_TOP_SCP 56
|
||||
#define CLK_TOP_MFG 57
|
||||
#define CLK_TOP_F_FUART 58
|
||||
#define CLK_TOP_SPI 59
|
||||
#define CLK_TOP_MSDC50_0 60
|
||||
#define CLK_TOP_MSDC30_1 61
|
||||
#define CLK_TOP_AUDIO 62
|
||||
#define CLK_TOP_AUD_1 63
|
||||
#define CLK_TOP_AUD_ENGEN1 64
|
||||
#define CLK_TOP_F_FDISP_PWM 65
|
||||
#define CLK_TOP_SSPM 66
|
||||
#define CLK_TOP_DXCC 67
|
||||
#define CLK_TOP_I2C 68
|
||||
#define CLK_TOP_F_FPWM 69
|
||||
#define CLK_TOP_F_FSENINF 70
|
||||
#define CLK_TOP_AES_FDE 71
|
||||
#define CLK_TOP_F_BIST2FPC 72
|
||||
#define CLK_TOP_ARMPLL_DIVIDER_PLL0 73
|
||||
#define CLK_TOP_ARMPLL_DIVIDER_PLL1 74
|
||||
#define CLK_TOP_ARMPLL_DIVIDER_PLL2 75
|
||||
#define CLK_TOP_DA_USB20_48M_DIV 76
|
||||
#define CLK_TOP_DA_UNIV_48M_DIV 77
|
||||
#define CLK_TOP_APLL12_DIV0 78
|
||||
#define CLK_TOP_APLL12_DIV1 79
|
||||
#define CLK_TOP_APLL12_DIV2 80
|
||||
#define CLK_TOP_APLL12_DIV3 81
|
||||
#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82
|
||||
#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83
|
||||
#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84
|
||||
#define CLK_TOP_FMEM_OCC_DRC_EN 85
|
||||
#define CLK_TOP_USB20_48M_EN 86
|
||||
#define CLK_TOP_UNIVPLL_48M_EN 87
|
||||
#define CLK_TOP_MPLL_104M_EN 88
|
||||
#define CLK_TOP_MPLL_52M_EN 89
|
||||
#define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90
|
||||
#define CLK_TOP_F_BIST2FPC_EN 91
|
||||
#define CLK_TOP_MD_32K 92
|
||||
#define CLK_TOP_MD_26M 93
|
||||
#define CLK_TOP_MD2_32K 94
|
||||
#define CLK_TOP_MD2_26M 95
|
||||
#define CLK_TOP_AXI_SEL 96
|
||||
#define CLK_TOP_MEM_SEL 97
|
||||
#define CLK_TOP_MM_SEL 98
|
||||
#define CLK_TOP_SCP_SEL 99
|
||||
#define CLK_TOP_MFG_SEL 100
|
||||
#define CLK_TOP_ATB_SEL 101
|
||||
#define CLK_TOP_CAMTG_SEL 102
|
||||
#define CLK_TOP_CAMTG1_SEL 103
|
||||
#define CLK_TOP_CAMTG2_SEL 104
|
||||
#define CLK_TOP_CAMTG3_SEL 105
|
||||
#define CLK_TOP_UART_SEL 106
|
||||
#define CLK_TOP_SPI_SEL 107
|
||||
#define CLK_TOP_MSDC50_0_HCLK_SEL 108
|
||||
#define CLK_TOP_MSDC50_0_SEL 109
|
||||
#define CLK_TOP_MSDC30_1_SEL 110
|
||||
#define CLK_TOP_AUDIO_SEL 111
|
||||
#define CLK_TOP_AUD_INTBUS_SEL 112
|
||||
#define CLK_TOP_AUD_1_SEL 113
|
||||
#define CLK_TOP_AUD_ENGEN1_SEL 114
|
||||
#define CLK_TOP_DISP_PWM_SEL 115
|
||||
#define CLK_TOP_SSPM_SEL 116
|
||||
#define CLK_TOP_DXCC_SEL 117
|
||||
#define CLK_TOP_USB_TOP_SEL 118
|
||||
#define CLK_TOP_SPM_SEL 119
|
||||
#define CLK_TOP_I2C_SEL 120
|
||||
#define CLK_TOP_PWM_SEL 121
|
||||
#define CLK_TOP_SENINF_SEL 122
|
||||
#define CLK_TOP_AES_FDE_SEL 123
|
||||
#define CLK_TOP_PWRAP_ULPOSC_SEL 124
|
||||
#define CLK_TOP_CAMTM_SEL 125
|
||||
#define CLK_TOP_NR_CLK 126
|
||||
|
||||
/* INFRACFG */
|
||||
#define CLK_IFR_ICUSB 0
|
||||
#define CLK_IFR_GCE 1
|
||||
#define CLK_IFR_THERM 2
|
||||
#define CLK_IFR_I2C_AP 3
|
||||
#define CLK_IFR_I2C_CCU 4
|
||||
#define CLK_IFR_I2C_SSPM 5
|
||||
#define CLK_IFR_I2C_RSV 6
|
||||
#define CLK_IFR_PWM_HCLK 7
|
||||
#define CLK_IFR_PWM1 8
|
||||
#define CLK_IFR_PWM2 9
|
||||
#define CLK_IFR_PWM3 10
|
||||
#define CLK_IFR_PWM4 11
|
||||
#define CLK_IFR_PWM5 12
|
||||
#define CLK_IFR_PWM 13
|
||||
#define CLK_IFR_UART0 14
|
||||
#define CLK_IFR_UART1 15
|
||||
#define CLK_IFR_GCE_26M 16
|
||||
#define CLK_IFR_CQ_DMA_FPC 17
|
||||
#define CLK_IFR_BTIF 18
|
||||
#define CLK_IFR_SPI0 19
|
||||
#define CLK_IFR_MSDC0 20
|
||||
#define CLK_IFR_MSDC1 21
|
||||
#define CLK_IFR_TRNG 22
|
||||
#define CLK_IFR_AUXADC 23
|
||||
#define CLK_IFR_CCIF1_AP 24
|
||||
#define CLK_IFR_CCIF1_MD 25
|
||||
#define CLK_IFR_AUXADC_MD 26
|
||||
#define CLK_IFR_AP_DMA 27
|
||||
#define CLK_IFR_DEVICE_APC 28
|
||||
#define CLK_IFR_CCIF_AP 29
|
||||
#define CLK_IFR_AUDIO 30
|
||||
#define CLK_IFR_CCIF_MD 31
|
||||
#define CLK_IFR_RG_PWM_FBCLK6 32
|
||||
#define CLK_IFR_DISP_PWM 33
|
||||
#define CLK_IFR_CLDMA_BCLK 34
|
||||
#define CLK_IFR_AUDIO_26M_BCLK 35
|
||||
#define CLK_IFR_SPI1 36
|
||||
#define CLK_IFR_I2C4 37
|
||||
#define CLK_IFR_SPI2 38
|
||||
#define CLK_IFR_SPI3 39
|
||||
#define CLK_IFR_I2C5 40
|
||||
#define CLK_IFR_I2C5_ARBITER 41
|
||||
#define CLK_IFR_I2C5_IMM 42
|
||||
#define CLK_IFR_I2C1_ARBITER 43
|
||||
#define CLK_IFR_I2C1_IMM 44
|
||||
#define CLK_IFR_I2C2_ARBITER 45
|
||||
#define CLK_IFR_I2C2_IMM 46
|
||||
#define CLK_IFR_SPI4 47
|
||||
#define CLK_IFR_SPI5 48
|
||||
#define CLK_IFR_CQ_DMA 49
|
||||
#define CLK_IFR_FAES_FDE 50
|
||||
#define CLK_IFR_MSDC0_SELF 51
|
||||
#define CLK_IFR_MSDC1_SELF 52
|
||||
#define CLK_IFR_I2C6 53
|
||||
#define CLK_IFR_AP_MSDC0 54
|
||||
#define CLK_IFR_MD_MSDC0 55
|
||||
#define CLK_IFR_MSDC0_SRC 56
|
||||
#define CLK_IFR_MSDC1_SRC 57
|
||||
#define CLK_IFR_AES_TOP0_BCLK 58
|
||||
#define CLK_IFR_MCU_PM_BCLK 59
|
||||
#define CLK_IFR_CCIF2_AP 60
|
||||
#define CLK_IFR_CCIF2_MD 61
|
||||
#define CLK_IFR_CCIF3_AP 62
|
||||
#define CLK_IFR_CCIF3_MD 63
|
||||
#define CLK_IFR_NR_CLK 64
|
||||
|
||||
/* AUDIO */
|
||||
#define CLK_AUDIO_AFE 0
|
||||
#define CLK_AUDIO_22M 1
|
||||
#define CLK_AUDIO_APLL_TUNER 2
|
||||
#define CLK_AUDIO_ADC 3
|
||||
#define CLK_AUDIO_DAC 4
|
||||
#define CLK_AUDIO_DAC_PREDIS 5
|
||||
#define CLK_AUDIO_TML 6
|
||||
#define CLK_AUDIO_I2S1_BCLK 7
|
||||
#define CLK_AUDIO_I2S2_BCLK 8
|
||||
#define CLK_AUDIO_I2S3_BCLK 9
|
||||
#define CLK_AUDIO_I2S4_BCLK 10
|
||||
#define CLK_AUDIO_NR_CLK 11
|
||||
|
||||
/* MIPI_RX_ANA_CSI0A */
|
||||
|
||||
#define CLK_MIPI0A_CSR_CSI_EN_0A 0
|
||||
#define CLK_MIPI0A_NR_CLK 1
|
||||
|
||||
/* MMSYS_CONFIG */
|
||||
|
||||
#define CLK_MM_MDP_RDMA0 0
|
||||
#define CLK_MM_MDP_CCORR0 1
|
||||
#define CLK_MM_MDP_RSZ0 2
|
||||
#define CLK_MM_MDP_RSZ1 3
|
||||
#define CLK_MM_MDP_TDSHP0 4
|
||||
#define CLK_MM_MDP_WROT0 5
|
||||
#define CLK_MM_MDP_WDMA0 6
|
||||
#define CLK_MM_DISP_OVL0 7
|
||||
#define CLK_MM_DISP_OVL0_2L 8
|
||||
#define CLK_MM_DISP_RSZ0 9
|
||||
#define CLK_MM_DISP_RDMA0 10
|
||||
#define CLK_MM_DISP_WDMA0 11
|
||||
#define CLK_MM_DISP_COLOR0 12
|
||||
#define CLK_MM_DISP_CCORR0 13
|
||||
#define CLK_MM_DISP_AAL0 14
|
||||
#define CLK_MM_DISP_GAMMA0 15
|
||||
#define CLK_MM_DISP_DITHER0 16
|
||||
#define CLK_MM_DSI0 17
|
||||
#define CLK_MM_FAKE_ENG 18
|
||||
#define CLK_MM_SMI_COMMON 19
|
||||
#define CLK_MM_SMI_LARB0 20
|
||||
#define CLK_MM_SMI_COMM0 21
|
||||
#define CLK_MM_SMI_COMM1 22
|
||||
#define CLK_MM_CAM_MDP 23
|
||||
#define CLK_MM_SMI_IMG 24
|
||||
#define CLK_MM_SMI_CAM 25
|
||||
#define CLK_MM_IMG_DL_RELAY 26
|
||||
#define CLK_MM_IMG_DL_ASYNC_TOP 27
|
||||
#define CLK_MM_DIG_DSI 28
|
||||
#define CLK_MM_F26M_HRTWT 29
|
||||
#define CLK_MM_NR_CLK 30
|
||||
|
||||
/* IMGSYS */
|
||||
|
||||
#define CLK_IMG_LARB2 0
|
||||
#define CLK_IMG_DIP 1
|
||||
#define CLK_IMG_FDVT 2
|
||||
#define CLK_IMG_DPE 3
|
||||
#define CLK_IMG_RSC 4
|
||||
#define CLK_IMG_NR_CLK 5
|
||||
|
||||
/* VENCSYS */
|
||||
|
||||
#define CLK_VENC_SET0_LARB 0
|
||||
#define CLK_VENC_SET1_VENC 1
|
||||
#define CLK_VENC_SET2_JPGENC 2
|
||||
#define CLK_VENC_SET3_VDEC 3
|
||||
#define CLK_VENC_NR_CLK 4
|
||||
|
||||
/* CAMSYS */
|
||||
|
||||
#define CLK_CAM_LARB3 0
|
||||
#define CLK_CAM_DFP_VAD 1
|
||||
#define CLK_CAM 2
|
||||
#define CLK_CAMTG 3
|
||||
#define CLK_CAM_SENINF 4
|
||||
#define CLK_CAMSV0 5
|
||||
#define CLK_CAMSV1 6
|
||||
#define CLK_CAMSV2 7
|
||||
#define CLK_CAM_CCU 8
|
||||
#define CLK_CAM_NR_CLK 9
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT6765_H */
|
||||
25
include/dt-bindings/reset/bt1-ccu.h
Normal file
25
include/dt-bindings/reset/bt1-ccu.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
*
|
||||
* Baikal-T1 CCU reset indices
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_RESET_BT1_CCU_H
|
||||
#define __DT_BINDINGS_RESET_BT1_CCU_H
|
||||
|
||||
#define CCU_AXI_MAIN_RST 0
|
||||
#define CCU_AXI_DDR_RST 1
|
||||
#define CCU_AXI_SATA_RST 2
|
||||
#define CCU_AXI_GMAC0_RST 3
|
||||
#define CCU_AXI_GMAC1_RST 4
|
||||
#define CCU_AXI_XGMAC_RST 5
|
||||
#define CCU_AXI_PCIE_M_RST 6
|
||||
#define CCU_AXI_PCIE_S_RST 7
|
||||
#define CCU_AXI_USB_RST 8
|
||||
#define CCU_AXI_HWA_RST 9
|
||||
#define CCU_AXI_SRAM_RST 10
|
||||
|
||||
#define CCU_SYS_SATA_REF_RST 0
|
||||
#define CCU_SYS_APB_RST 1
|
||||
|
||||
#endif /* __DT_BINDINGS_RESET_BT1_CCU_H */
|
||||
Loading…
Reference in New Issue
Block a user