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clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412

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This additional frequency is required for HDMI audio support
on Odroid U3 board.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Sylwester Nawrocki 2018-03-14 12:32:26 +01:00
parent 5b23fceec1
commit 182c084da5
1 changed files with 1 additions and 0 deletions
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drivers/clk/samsung/clk-exynos4.c
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@ -1319,6 +1319,7 @@ static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst =
}; };
static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = { static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {
PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690),
PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0), PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0),
PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381), PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381),
PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0), PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0),