forked from luck/tmp_suning_uos_patched
KVM/arm64 fixes for Linux 5.9, take #1
- Multiple stolen time fixes, with a new capability to match x86 - Fix for hugetlbfs mappings when PUD and PMD are the same level - Fix for hugetlbfs mappings when PTE mappings are enforced (dirty logging, for example) - Fix tracing output of 64bit values -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAl9SGP4PHG1hekBrZXJu ZWwub3JnAAoJECPQ0LrRPXpDWSoP/iZdsgkcMXM1qGRpMtn0FDVQiL2zd8QOEki+ /ldkeLvcUC9aqVOWdCM1fTweIvyPM0KSRxfbQRVGRGXym9bUMzx1laSl0CLXgi9q fa/lbmZOLG5PovQLe8eNon6aXybWWwuxfh/dhpBWLg5VGb0fXFutH3Cs2MGbX/Ec 6qMvbwO09SGSTrXSQepbhFkAmViBAgUH2kiRhKReDfvRc4OwsbxdlmA5r9Ek6R5L x7tH8mYwOJVP1OEZWYRX+9GG1n8hCIKKSuRrhMbZtErTSNdf+YhldC6DuJF0zWVE nsoKzIEl15kIl0akkC6oA3MLNX1sfRh9C2J85Rt+odN4fY4MidrfcqRgWE2X3cuu CKDsr0Lb6aTtfZASHm7QQRsM4hujWoArBq6ZvUNjpfNXOPe4ovxX9TkPHp6OezuK v3PRzXQxUtmreK+02ZzalL6IBwAQrmLKxXM2P2Nuh4gDMgFC/BrHMxc1QVSnmb/m flMuKtvm+fkwKySQvX22FZrzhPfCMAuxCh28WdDSW2pnmZ8H0M3922y45xw3QTpg SltMtIcpO6ipzMsrVvO/hI/GvByFNN6jcLVGUV1Wx8mNdcf2kPeebA4hINKt5UDh gpwkz4zb2Bgp/YdgiG8NzBjpk2FMO0IPiAnouPrXenizbesAlKR2V3uFqa70PW/A BBkHnakS =VBrL -----END PGP SIGNATURE----- Merge tag 'kvmarm-fixes-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 fixes for Linux 5.9, take #1 - Multiple stolen time fixes, with a new capability to match x86 - Fix for hugetlbfs mappings when PUD and PMD are the same level - Fix for hugetlbfs mappings when PTE mappings are enforced (dirty logging, for example) - Fix tracing output of 64bit values
This commit is contained in:
Paolo Bonzini
commit
1b67fd086d
10
.mailmap
10
.mailmap
|
|
@ -2,11 +2,16 @@
|
|||
# This list is used by git-shortlog to fix a few botched name translations
|
||||
# in the git archive, either because the author's full name was messed up
|
||||
# and/or not always written the same way, making contributions from the
|
||||
# same person appearing not to be so or badly displayed.
|
||||
# same person appearing not to be so or badly displayed. Also allows for
|
||||
# old email addresses to map to new email addresses.
|
||||
#
|
||||
# For format details, see "MAPPING AUTHORS" in "man git-shortlog".
|
||||
#
|
||||
# Please keep this list dictionary sorted.
|
||||
#
|
||||
# This comment is parsed by git-shortlog:
|
||||
# repo-abbrev: /pub/scm/linux/kernel/git/
|
||||
#
|
||||
|
||||
Aaron Durbin <adurbin@google.com>
|
||||
Adam Oldham <oldhamca@gmail.com>
|
||||
Adam Radford <aradford@gmail.com>
|
||||
|
|
@ -99,6 +104,7 @@ Gerald Schaefer <gerald.schaefer@linux.ibm.com> <geraldsc@linux.vnet.ibm.com>
|
|||
Greg Kroah-Hartman <greg@echidna.(none)>
|
||||
Greg Kroah-Hartman <gregkh@suse.de>
|
||||
Greg Kroah-Hartman <greg@kroah.com>
|
||||
Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
|
||||
Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com>
|
||||
Hanjun Guo <guohanjun@huawei.com> <hanjun.guo@linaro.org>
|
||||
Heiko Carstens <hca@linux.ibm.com> <h.carstens@de.ibm.com>
|
||||
|
|
|
|||
|
|
@ -202,6 +202,25 @@ Description:
|
|||
functions. See the section named 'NVDIMM Root Device _DSMs' in
|
||||
the ACPI specification.
|
||||
|
||||
What: /sys/bus/nd/devices/ndbusX/nfit/firmware_activate_noidle
|
||||
Date: Apr, 2020
|
||||
KernelVersion: v5.8
|
||||
Contact: linux-nvdimm@lists.01.org
|
||||
Description:
|
||||
(RW) The Intel platform implementation of firmware activate
|
||||
support exposes an option let the platform force idle devices in
|
||||
the system over the activation event, or trust that the OS will
|
||||
do it. The safe default is to let the platform force idle
|
||||
devices since the kernel is already in a suspend state, and on
|
||||
the chance that a driver does not properly quiesce bus-mastering
|
||||
after a suspend callback the platform will handle it. However,
|
||||
the activation might abort if, for example, platform firmware
|
||||
determines that the activation time exceeds the max PCI-E
|
||||
completion timeout. Since the platform does not know whether the
|
||||
OS is running the activation from a suspend context it aborts,
|
||||
but if the system owner trusts driver suspend callback to be
|
||||
sufficient then 'firmware_activation_noidle' can be
|
||||
enabled to bypass the activation abort.
|
||||
|
||||
What: /sys/bus/nd/devices/regionX/nfit/range_index
|
||||
Date: Jun, 2015
|
||||
|
|
|
|||
2
Documentation/ABI/testing/sysfs-bus-nvdimm
Normal file
2
Documentation/ABI/testing/sysfs-bus-nvdimm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
The libnvdimm sub-system implements a common sysfs interface for
|
||||
platform nvdimm resources. See Documentation/driver-api/nvdimm/.
|
||||
15
Documentation/ABI/testing/sysfs-driver-input-exc3000
Normal file
15
Documentation/ABI/testing/sysfs-driver-input-exc3000
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
What: /sys/bus/i2c/devices/xxx/fw_version
|
||||
Date: Aug 2020
|
||||
Contact: linux-input@vger.kernel.org
|
||||
Description: Reports the firmware version provided by the touchscreen, for example "00_T6" on a EXC80H60
|
||||
|
||||
Access: Read
|
||||
Valid values: Represented as string
|
||||
|
||||
What: /sys/bus/i2c/devices/xxx/model
|
||||
Date: Aug 2020
|
||||
Contact: linux-input@vger.kernel.org
|
||||
Description: Reports the model identification provided by the touchscreen, for example "Orion_1320" on a EXC80H60
|
||||
|
||||
Access: Read
|
||||
Valid values: Represented as string
|
||||
|
|
@ -229,7 +229,9 @@ Date: August 2017
|
|||
Contact: "Jaegeuk Kim" <jaegeuk@kernel.org>
|
||||
Description: Do background GC agressively when set. When gc_urgent = 1,
|
||||
background thread starts to do GC by given gc_urgent_sleep_time
|
||||
interval. It is set to 0 by default.
|
||||
interval. When gc_urgent = 2, F2FS will lower the bar of
|
||||
checking idle in order to process outstanding discard commands
|
||||
and GC a little bit aggressively. It is set to 0 by default.
|
||||
|
||||
What: /sys/fs/f2fs/<disk>/gc_urgent_sleep_time
|
||||
Date: August 2017
|
||||
|
|
|
|||
|
|
@ -1274,6 +1274,10 @@ PAGE_SIZE multiple when read back.
|
|||
Amount of memory used for storing in-kernel data
|
||||
structures.
|
||||
|
||||
percpu
|
||||
Amount of memory used for storing per-cpu kernel
|
||||
data structures.
|
||||
|
||||
sock
|
||||
Amount of memory used in network transmission buffers
|
||||
|
||||
|
|
|
|||
|
|
@ -80,6 +80,10 @@ The possible values in this file are:
|
|||
- The processor is not vulnerable.
|
||||
* - KVM: Mitigation: Split huge pages
|
||||
- Software changes mitigate this issue.
|
||||
* - KVM: Mitigation: VMX unsupported
|
||||
- KVM is not vulnerable because Virtual Machine Extensions (VMX) is not supported.
|
||||
* - KVM: Mitigation: VMX disabled
|
||||
- KVM is not vulnerable because Virtual Machine Extensions (VMX) is disabled.
|
||||
* - KVM: Vulnerable
|
||||
- The processor is vulnerable, but no mitigation enabled
|
||||
|
||||
|
|
|
|||
|
|
@ -724,7 +724,7 @@
|
|||
memory region [offset, offset + size] for that kernel
|
||||
image. If '@offset' is omitted, then a suitable offset
|
||||
is selected automatically.
|
||||
[KNL, x86_64] select a region under 4G first, and
|
||||
[KNL, X86-64] Select a region under 4G first, and
|
||||
fall back to reserve region above 4G when '@offset'
|
||||
hasn't been specified.
|
||||
See Documentation/admin-guide/kdump/kdump.rst for further details.
|
||||
|
|
@ -737,14 +737,14 @@
|
|||
Documentation/admin-guide/kdump/kdump.rst for an example.
|
||||
|
||||
crashkernel=size[KMG],high
|
||||
[KNL, x86_64] range could be above 4G. Allow kernel
|
||||
[KNL, X86-64] range could be above 4G. Allow kernel
|
||||
to allocate physical memory region from top, so could
|
||||
be above 4G if system have more than 4G ram installed.
|
||||
Otherwise memory region will be allocated below 4G, if
|
||||
available.
|
||||
It will be ignored if crashkernel=X is specified.
|
||||
crashkernel=size[KMG],low
|
||||
[KNL, x86_64] range under 4G. When crashkernel=X,high
|
||||
[KNL, X86-64] range under 4G. When crashkernel=X,high
|
||||
is passed, kernel could allocate physical memory region
|
||||
above 4G, that cause second kernel crash on system
|
||||
that require some amount of low memory, e.g. swiotlb
|
||||
|
|
@ -1427,7 +1427,7 @@
|
|||
|
||||
gamma= [HW,DRM]
|
||||
|
||||
gart_fix_e820= [X86_64] disable the fix e820 for K8 GART
|
||||
gart_fix_e820= [X86-64] disable the fix e820 for K8 GART
|
||||
Format: off | on
|
||||
default: on
|
||||
|
||||
|
|
@ -1814,7 +1814,7 @@
|
|||
Format: 0 | 1
|
||||
Default set by CONFIG_INIT_ON_FREE_DEFAULT_ON.
|
||||
|
||||
init_pkru= [x86] Specify the default memory protection keys rights
|
||||
init_pkru= [X86] Specify the default memory protection keys rights
|
||||
register contents for all processes. 0x55555554 by
|
||||
default (disallow access to all but pkey 0). Can
|
||||
override in debugfs after boot.
|
||||
|
|
@ -1822,7 +1822,7 @@
|
|||
inport.irq= [HW] Inport (ATI XL and Microsoft) busmouse driver
|
||||
Format: <irq>
|
||||
|
||||
int_pln_enable [x86] Enable power limit notification interrupt
|
||||
int_pln_enable [X86] Enable power limit notification interrupt
|
||||
|
||||
integrity_audit=[IMA]
|
||||
Format: { "0" | "1" }
|
||||
|
|
@ -1840,7 +1840,7 @@
|
|||
bypassed by not enabling DMAR with this option. In
|
||||
this case, gfx device will use physical address for
|
||||
DMA.
|
||||
forcedac [x86_64]
|
||||
forcedac [X86-64]
|
||||
With this option iommu will not optimize to look
|
||||
for io virtual address below 32-bit forcing dual
|
||||
address cycle on pci bus for cards supporting greater
|
||||
|
|
@ -1925,7 +1925,7 @@
|
|||
strict regions from userspace.
|
||||
relaxed
|
||||
|
||||
iommu= [x86]
|
||||
iommu= [X86]
|
||||
off
|
||||
force
|
||||
noforce
|
||||
|
|
@ -1935,8 +1935,8 @@
|
|||
merge
|
||||
nomerge
|
||||
soft
|
||||
pt [x86]
|
||||
nopt [x86]
|
||||
pt [X86]
|
||||
nopt [X86]
|
||||
nobypass [PPC/POWERNV]
|
||||
Disable IOMMU bypass, using IOMMU for PCI devices.
|
||||
|
||||
|
|
@ -2079,21 +2079,21 @@
|
|||
|
||||
iucv= [HW,NET]
|
||||
|
||||
ivrs_ioapic [HW,X86_64]
|
||||
ivrs_ioapic [HW,X86-64]
|
||||
Provide an override to the IOAPIC-ID<->DEVICE-ID
|
||||
mapping provided in the IVRS ACPI table. For
|
||||
example, to map IOAPIC-ID decimal 10 to
|
||||
PCI device 00:14.0 write the parameter as:
|
||||
ivrs_ioapic[10]=00:14.0
|
||||
|
||||
ivrs_hpet [HW,X86_64]
|
||||
ivrs_hpet [HW,X86-64]
|
||||
Provide an override to the HPET-ID<->DEVICE-ID
|
||||
mapping provided in the IVRS ACPI table. For
|
||||
example, to map HPET-ID decimal 0 to
|
||||
PCI device 00:14.0 write the parameter as:
|
||||
ivrs_hpet[0]=00:14.0
|
||||
|
||||
ivrs_acpihid [HW,X86_64]
|
||||
ivrs_acpihid [HW,X86-64]
|
||||
Provide an override to the ACPI-HID:UID<->DEVICE-ID
|
||||
mapping provided in the IVRS ACPI table. For
|
||||
example, to map UART-HID:UID AMD0020:0 to
|
||||
|
|
@ -2370,7 +2370,7 @@
|
|||
lapic [X86-32,APIC] Enable the local APIC even if BIOS
|
||||
disabled it.
|
||||
|
||||
lapic= [x86,APIC] "notscdeadline" Do not use TSC deadline
|
||||
lapic= [X86,APIC] "notscdeadline" Do not use TSC deadline
|
||||
value for LAPIC timer one-shot implementation. Default
|
||||
back to the programmable timer unit in the LAPIC.
|
||||
|
||||
|
|
@ -3188,12 +3188,12 @@
|
|||
register save and restore. The kernel will only save
|
||||
legacy floating-point registers on task switch.
|
||||
|
||||
nohugeiomap [KNL,x86,PPC] Disable kernel huge I/O mappings.
|
||||
nohugeiomap [KNL,X86,PPC] Disable kernel huge I/O mappings.
|
||||
|
||||
nosmt [KNL,S390] Disable symmetric multithreading (SMT).
|
||||
Equivalent to smt=1.
|
||||
|
||||
[KNL,x86] Disable symmetric multithreading (SMT).
|
||||
[KNL,X86] Disable symmetric multithreading (SMT).
|
||||
nosmt=force: Force disable SMT, cannot be undone
|
||||
via the sysfs control file.
|
||||
|
||||
|
|
@ -3955,7 +3955,7 @@
|
|||
pt. [PARIDE]
|
||||
See Documentation/admin-guide/blockdev/paride.rst.
|
||||
|
||||
pti= [X86_64] Control Page Table Isolation of user and
|
||||
pti= [X86-64] Control Page Table Isolation of user and
|
||||
kernel address spaces. Disabling this feature
|
||||
removes hardening, but improves performance of
|
||||
system calls and interrupts.
|
||||
|
|
@ -3967,7 +3967,7 @@
|
|||
|
||||
Not specifying this option is equivalent to pti=auto.
|
||||
|
||||
nopti [X86_64]
|
||||
nopti [X86-64]
|
||||
Equivalent to pti=off
|
||||
|
||||
pty.legacy_count=
|
||||
|
|
|
|||
|
|
@ -54,10 +54,13 @@ registered (see `below <status_attr_>`_).
|
|||
Operation Modes
|
||||
===============
|
||||
|
||||
``intel_pstate`` can operate in three different modes: in the active mode with
|
||||
or without hardware-managed P-states support and in the passive mode. Which of
|
||||
them will be in effect depends on what kernel command line options are used and
|
||||
on the capabilities of the processor.
|
||||
``intel_pstate`` can operate in two different modes, active or passive. In the
|
||||
active mode, it uses its own internal performance scaling governor algorithm or
|
||||
allows the hardware to do preformance scaling by itself, while in the passive
|
||||
mode it responds to requests made by a generic ``CPUFreq`` governor implementing
|
||||
a certain performance scaling algorithm. Which of them will be in effect
|
||||
depends on what kernel command line options are used and on the capabilities of
|
||||
the processor.
|
||||
|
||||
Active Mode
|
||||
-----------
|
||||
|
|
@ -194,10 +197,11 @@ This is the default operation mode of ``intel_pstate`` for processors without
|
|||
hardware-managed P-states (HWP) support. It is always used if the
|
||||
``intel_pstate=passive`` argument is passed to the kernel in the command line
|
||||
regardless of whether or not the given processor supports HWP. [Note that the
|
||||
``intel_pstate=no_hwp`` setting implies ``intel_pstate=passive`` if it is used
|
||||
without ``intel_pstate=active``.] Like in the active mode without HWP support,
|
||||
in this mode ``intel_pstate`` may refuse to work with processors that are not
|
||||
recognized by it.
|
||||
``intel_pstate=no_hwp`` setting causes the driver to start in the passive mode
|
||||
if it is not combined with ``intel_pstate=active``.] Like in the active mode
|
||||
without HWP support, in this mode ``intel_pstate`` may refuse to work with
|
||||
processors that are not recognized by it if HWP is prevented from being enabled
|
||||
through the kernel command line.
|
||||
|
||||
If the driver works in this mode, the ``scaling_driver`` policy attribute in
|
||||
``sysfs`` for all ``CPUFreq`` policies contains the string "intel_cpufreq".
|
||||
|
|
@ -318,10 +322,9 @@ manuals need to be consulted to get to it too.
|
|||
|
||||
For this reason, there is a list of supported processors in ``intel_pstate`` and
|
||||
the driver initialization will fail if the detected processor is not in that
|
||||
list, unless it supports the `HWP feature <Active Mode_>`_. [The interface to
|
||||
obtain all of the information listed above is the same for all of the processors
|
||||
supporting the HWP feature, which is why they all are supported by
|
||||
``intel_pstate``.]
|
||||
list, unless it supports the HWP feature. [The interface to obtain all of the
|
||||
information listed above is the same for all of the processors supporting the
|
||||
HWP feature, which is why ``intel_pstate`` works with all of them.]
|
||||
|
||||
|
||||
User Space Interface in ``sysfs``
|
||||
|
|
@ -425,22 +428,16 @@ argument is passed to the kernel in the command line.
|
|||
as well as the per-policy ones) are then reset to their default
|
||||
values, possibly depending on the target operation mode.]
|
||||
|
||||
That only is supported in some configurations, though (for example, if
|
||||
the `HWP feature is enabled in the processor <Active Mode With HWP_>`_,
|
||||
the operation mode of the driver cannot be changed), and if it is not
|
||||
supported in the current configuration, writes to this attribute will
|
||||
fail with an appropriate error.
|
||||
|
||||
``energy_efficiency``
|
||||
This attribute is only present on platforms, which have CPUs matching
|
||||
Kaby Lake or Coffee Lake desktop CPU model. By default
|
||||
energy efficiency optimizations are disabled on these CPU models in HWP
|
||||
mode by this driver. Enabling energy efficiency may limit maximum
|
||||
operating frequency in both HWP and non HWP mode. In non HWP mode,
|
||||
optimizations are done only in the turbo frequency range. In HWP mode,
|
||||
optimizations are done in the entire frequency range. Setting this
|
||||
attribute to "1" enables energy efficiency optimizations and setting
|
||||
to "0" disables energy efficiency optimizations.
|
||||
This attribute is only present on platforms with CPUs matching the Kaby
|
||||
Lake or Coffee Lake desktop CPU model. By default, energy-efficiency
|
||||
optimizations are disabled on these CPU models if HWP is enabled.
|
||||
Enabling energy-efficiency optimizations may limit maximum operating
|
||||
frequency with or without the HWP feature. With HWP enabled, the
|
||||
optimizations are done only in the turbo frequency range. Without it,
|
||||
they are done in the entire available frequency range. Setting this
|
||||
attribute to "1" enables the energy-efficiency optimizations and setting
|
||||
to "0" disables them.
|
||||
|
||||
Interpretation of Policy Attributes
|
||||
-----------------------------------
|
||||
|
|
@ -484,8 +481,8 @@ Next, the following policy attributes have special meaning if
|
|||
policy for the time interval between the last two invocations of the
|
||||
driver's utilization update callback by the CPU scheduler for that CPU.
|
||||
|
||||
One more policy attribute is present if the `HWP feature is enabled in the
|
||||
processor <Active Mode With HWP_>`_:
|
||||
One more policy attribute is present if the HWP feature is enabled in the
|
||||
processor:
|
||||
|
||||
``base_frequency``
|
||||
Shows the base frequency of the CPU. Any frequency above this will be
|
||||
|
|
@ -526,11 +523,11 @@ on the following rules, regardless of the current operation mode of the driver:
|
|||
|
||||
3. The global and per-policy limits can be set independently.
|
||||
|
||||
If the `HWP feature is enabled in the processor <Active Mode With HWP_>`_, the
|
||||
resulting effective values are written into its registers whenever the limits
|
||||
change in order to request its internal P-state selection logic to always set
|
||||
P-states within these limits. Otherwise, the limits are taken into account by
|
||||
scaling governors (in the `passive mode <Passive Mode_>`_) and by the driver
|
||||
In the `active mode with the HWP feature enabled <Active Mode With HWP_>`_, the
|
||||
resulting effective values are written into hardware registers whenever the
|
||||
limits change in order to request its internal P-state selection logic to always
|
||||
set P-states within these limits. Otherwise, the limits are taken into account
|
||||
by scaling governors (in the `passive mode <Passive Mode_>`_) and by the driver
|
||||
every time before setting a new P-state for a CPU.
|
||||
|
||||
Additionally, if the ``intel_pstate=per_cpu_perf_limits`` command line argument
|
||||
|
|
@ -541,12 +538,11 @@ at all and the only way to set the limits is by using the policy attributes.
|
|||
Energy vs Performance Hints
|
||||
---------------------------
|
||||
|
||||
If ``intel_pstate`` works in the `active mode with the HWP feature enabled
|
||||
<Active Mode With HWP_>`_ in the processor, additional attributes are present
|
||||
in every ``CPUFreq`` policy directory in ``sysfs``. They are intended to allow
|
||||
user space to help ``intel_pstate`` to adjust the processor's internal P-state
|
||||
selection logic by focusing it on performance or on energy-efficiency, or
|
||||
somewhere between the two extremes:
|
||||
If the hardware-managed P-states (HWP) is enabled in the processor, additional
|
||||
attributes, intended to allow user space to help ``intel_pstate`` to adjust the
|
||||
processor's internal P-state selection logic by focusing it on performance or on
|
||||
energy-efficiency, or somewhere between the two extremes, are present in every
|
||||
``CPUFreq`` policy directory in ``sysfs``. They are :
|
||||
|
||||
``energy_performance_preference``
|
||||
Current value of the energy vs performance hint for the given policy
|
||||
|
|
@ -650,12 +646,14 @@ of them have to be prepended with the ``intel_pstate=`` prefix.
|
|||
Do not register ``intel_pstate`` as the scaling driver even if the
|
||||
processor is supported by it.
|
||||
|
||||
``active``
|
||||
Register ``intel_pstate`` in the `active mode <Active Mode_>`_ to start
|
||||
with.
|
||||
|
||||
``passive``
|
||||
Register ``intel_pstate`` in the `passive mode <Passive Mode_>`_ to
|
||||
start with.
|
||||
|
||||
This option implies the ``no_hwp`` one described below.
|
||||
|
||||
``force``
|
||||
Register ``intel_pstate`` as the scaling driver instead of
|
||||
``acpi-cpufreq`` even if the latter is preferred on the given system.
|
||||
|
|
@ -670,13 +668,12 @@ of them have to be prepended with the ``intel_pstate=`` prefix.
|
|||
driver is used instead of ``acpi-cpufreq``.
|
||||
|
||||
``no_hwp``
|
||||
Do not enable the `hardware-managed P-states (HWP) feature
|
||||
<Active Mode With HWP_>`_ even if it is supported by the processor.
|
||||
Do not enable the hardware-managed P-states (HWP) feature even if it is
|
||||
supported by the processor.
|
||||
|
||||
``hwp_only``
|
||||
Register ``intel_pstate`` as the scaling driver only if the
|
||||
`hardware-managed P-states (HWP) feature <Active Mode With HWP_>`_ is
|
||||
supported by the processor.
|
||||
hardware-managed P-states (HWP) feature is supported by the processor.
|
||||
|
||||
``support_acpi_ppc``
|
||||
Take ACPI ``_PPC`` performance limits into account.
|
||||
|
|
|
|||
|
|
@ -164,7 +164,8 @@ core_pattern
|
|||
%s signal number
|
||||
%t UNIX time of dump
|
||||
%h hostname
|
||||
%e executable filename (may be shortened)
|
||||
%e executable filename (may be shortened, could be changed by prctl etc)
|
||||
%f executable filename
|
||||
%E executable path
|
||||
%c maximum size of core file by resource limit RLIMIT_CORE
|
||||
%<OTHER> both are dropped
|
||||
|
|
|
|||
|
|
@ -119,6 +119,21 @@ all zones are compacted such that free memory is available in contiguous
|
|||
blocks where possible. This can be important for example in the allocation of
|
||||
huge pages although processes will also directly compact memory as required.
|
||||
|
||||
compaction_proactiveness
|
||||
========================
|
||||
|
||||
This tunable takes a value in the range [0, 100] with a default value of
|
||||
20. This tunable determines how aggressively compaction is done in the
|
||||
background. Setting it to 0 disables proactive compaction.
|
||||
|
||||
Note that compaction has a non-trivial system-wide impact as pages
|
||||
belonging to different processes are moved around, which could also lead
|
||||
to latency spikes in unsuspecting applications. The kernel employs
|
||||
various heuristics to avoid wasting CPU cycles if it detects that
|
||||
proactive compaction is not being effective.
|
||||
|
||||
Be careful when setting it to extreme values like 100, as that may
|
||||
cause excessive background compaction activity.
|
||||
|
||||
compact_unevictable_allowed
|
||||
===========================
|
||||
|
|
|
|||
|
|
@ -125,6 +125,9 @@ stable kernels.
|
|||
| Cavium | ThunderX2 Core | #219 | CAVIUM_TX2_ERRATUM_219 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| Marvell | ARM-MMU-500 | #582743 | N/A |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
|
|
|
|||
|
|
@ -246,17 +246,6 @@ program is loaded the kernel will print warning message, so
|
|||
this helper is only useful for experiments and prototypes.
|
||||
Tracing BPF programs are root only.
|
||||
|
||||
Q: bpf_trace_printk() helper warning
|
||||
------------------------------------
|
||||
Q: When bpf_trace_printk() helper is used the kernel prints nasty
|
||||
warning message. Why is that?
|
||||
|
||||
A: This is done to nudge program authors into better interfaces when
|
||||
programs need to pass data to user space. Like bpf_perf_event_output()
|
||||
can be used to efficiently stream data via perf ring buffer.
|
||||
BPF maps can be used for asynchronous data sharing between kernel
|
||||
and user space. bpf_trace_printk() should only be used for debugging.
|
||||
|
||||
Q: New functionality via kernel modules?
|
||||
----------------------------------------
|
||||
Q: Can BPF functionality such as new program or map types, new
|
||||
|
|
|
|||
|
|
@ -557,7 +557,7 @@ phase. Currently, the capabilities are any of::
|
|||
CDC_DRIVE_STATUS /* driver implements drive status */
|
||||
|
||||
The capability flag is declared *const*, to prevent drivers from
|
||||
accidentally tampering with the contents. The capability fags actually
|
||||
accidentally tampering with the contents. The capability flags actually
|
||||
inform `cdrom.c` of what the driver can do. If the drive found
|
||||
by the driver does not have the capability, is can be masked out by
|
||||
the *cdrom_device_info* variable *mask*. For instance, the SCSI CD-ROM
|
||||
|
|
@ -736,7 +736,7 @@ Description of routines in `cdrom.c`
|
|||
|
||||
Only a few routines in `cdrom.c` are exported to the drivers. In this
|
||||
new section we will discuss these, as well as the functions that `take
|
||||
over' the CD-ROM interface to the kernel. The header file belonging
|
||||
over` the CD-ROM interface to the kernel. The header file belonging
|
||||
to `cdrom.c` is called `cdrom.h`. Formerly, some of the contents of this
|
||||
file were placed in the file `ucdrom.h`, but this file has now been
|
||||
merged back into `cdrom.h`.
|
||||
|
|
|
|||
|
|
@ -20,48 +20,48 @@ only ID allocation, and as a result is much more memory-efficient.
|
|||
IDR usage
|
||||
=========
|
||||
|
||||
Start by initialising an IDR, either with :c:func:`DEFINE_IDR`
|
||||
for statically allocated IDRs or :c:func:`idr_init` for dynamically
|
||||
Start by initialising an IDR, either with DEFINE_IDR()
|
||||
for statically allocated IDRs or idr_init() for dynamically
|
||||
allocated IDRs.
|
||||
|
||||
You can call :c:func:`idr_alloc` to allocate an unused ID. Look up
|
||||
the pointer you associated with the ID by calling :c:func:`idr_find`
|
||||
and free the ID by calling :c:func:`idr_remove`.
|
||||
You can call idr_alloc() to allocate an unused ID. Look up
|
||||
the pointer you associated with the ID by calling idr_find()
|
||||
and free the ID by calling idr_remove().
|
||||
|
||||
If you need to change the pointer associated with an ID, you can call
|
||||
:c:func:`idr_replace`. One common reason to do this is to reserve an
|
||||
idr_replace(). One common reason to do this is to reserve an
|
||||
ID by passing a ``NULL`` pointer to the allocation function; initialise the
|
||||
object with the reserved ID and finally insert the initialised object
|
||||
into the IDR.
|
||||
|
||||
Some users need to allocate IDs larger than ``INT_MAX``. So far all of
|
||||
these users have been content with a ``UINT_MAX`` limit, and they use
|
||||
:c:func:`idr_alloc_u32`. If you need IDs that will not fit in a u32,
|
||||
idr_alloc_u32(). If you need IDs that will not fit in a u32,
|
||||
we will work with you to address your needs.
|
||||
|
||||
If you need to allocate IDs sequentially, you can use
|
||||
:c:func:`idr_alloc_cyclic`. The IDR becomes less efficient when dealing
|
||||
idr_alloc_cyclic(). The IDR becomes less efficient when dealing
|
||||
with larger IDs, so using this function comes at a slight cost.
|
||||
|
||||
To perform an action on all pointers used by the IDR, you can
|
||||
either use the callback-based :c:func:`idr_for_each` or the
|
||||
iterator-style :c:func:`idr_for_each_entry`. You may need to use
|
||||
:c:func:`idr_for_each_entry_continue` to continue an iteration. You can
|
||||
also use :c:func:`idr_get_next` if the iterator doesn't fit your needs.
|
||||
either use the callback-based idr_for_each() or the
|
||||
iterator-style idr_for_each_entry(). You may need to use
|
||||
idr_for_each_entry_continue() to continue an iteration. You can
|
||||
also use idr_get_next() if the iterator doesn't fit your needs.
|
||||
|
||||
When you have finished using an IDR, you can call :c:func:`idr_destroy`
|
||||
When you have finished using an IDR, you can call idr_destroy()
|
||||
to release the memory used by the IDR. This will not free the objects
|
||||
pointed to from the IDR; if you want to do that, use one of the iterators
|
||||
to do it.
|
||||
|
||||
You can use :c:func:`idr_is_empty` to find out whether there are any
|
||||
You can use idr_is_empty() to find out whether there are any
|
||||
IDs currently allocated.
|
||||
|
||||
If you need to take a lock while allocating a new ID from the IDR,
|
||||
you may need to pass a restrictive set of GFP flags, which can lead
|
||||
to the IDR being unable to allocate memory. To work around this,
|
||||
you can call :c:func:`idr_preload` before taking the lock, and then
|
||||
:c:func:`idr_preload_end` after the allocation.
|
||||
you can call idr_preload() before taking the lock, and then
|
||||
idr_preload_end() after the allocation.
|
||||
|
||||
.. kernel-doc:: include/linux/idr.h
|
||||
:doc: idr sync
|
||||
|
|
|
|||
|
|
@ -175,13 +175,20 @@ For example, to check drivers/net/wireless/ one may write::
|
|||
make coccicheck M=drivers/net/wireless/
|
||||
|
||||
To apply Coccinelle on a file basis, instead of a directory basis, the
|
||||
following command may be used::
|
||||
C variable is used by the makefile to select which files to work with.
|
||||
This variable can be used to run scripts for the entire kernel, a
|
||||
specific directory, or for a single file.
|
||||
|
||||
make C=1 CHECK="scripts/coccicheck"
|
||||
For example, to check drivers/bluetooth/bfusb.c, the value 1 is
|
||||
passed to the C variable to check files that make considers
|
||||
need to be compiled.::
|
||||
|
||||
To check only newly edited code, use the value 2 for the C flag, i.e.::
|
||||
make C=1 CHECK=scripts/coccicheck drivers/bluetooth/bfusb.o
|
||||
|
||||
make C=2 CHECK="scripts/coccicheck"
|
||||
The value 2 is passed to the C variable to check files regardless of
|
||||
whether they need to be compiled or not.::
|
||||
|
||||
make C=2 CHECK=scripts/coccicheck drivers/bluetooth/bfusb.o
|
||||
|
||||
In these modes, which work on a file basis, there is no information
|
||||
about semantic patches displayed, and no commit message proposed.
|
||||
|
|
|
|||
|
|
@ -316,7 +316,7 @@ driver as a loadable kernel module kgdbwait will not do anything.
|
|||
Kernel parameter: ``kgdbcon``
|
||||
-----------------------------
|
||||
|
||||
The ``kgdbcon`` feature allows you to see :c:func:`printk` messages inside gdb
|
||||
The ``kgdbcon`` feature allows you to see printk() messages inside gdb
|
||||
while gdb is connected to the kernel. Kdb does not make use of the kgdbcon
|
||||
feature.
|
||||
|
||||
|
|
@ -432,7 +432,7 @@ This is a quick example of how to use kdb.
|
|||
``ps`` Displays only the active processes
|
||||
``ps A`` Shows all the processes
|
||||
``summary`` Shows kernel version info and memory usage
|
||||
``bt`` Get a backtrace of the current process using :c:func:`dump_stack`
|
||||
``bt`` Get a backtrace of the current process using dump_stack()
|
||||
``dmesg`` View the kernel syslog buffer
|
||||
``go`` Continue the system
|
||||
=========== =================================================================
|
||||
|
|
@ -724,7 +724,7 @@ The kernel debugger is organized into a number of components:
|
|||
The arch-specific portion implements:
|
||||
|
||||
- contains an arch-specific trap catcher which invokes
|
||||
:c:func:`kgdb_handle_exception` to start kgdb about doing its work
|
||||
kgdb_handle_exception() to start kgdb about doing its work
|
||||
|
||||
- translation to and from gdb specific packet format to :c:type:`pt_regs`
|
||||
|
||||
|
|
@ -769,7 +769,7 @@ The kernel debugger is organized into a number of components:
|
|||
config. Later run ``modprobe kdb_hello`` and the next time you
|
||||
enter the kdb shell, you can run the ``hello`` command.
|
||||
|
||||
- The implementation for :c:func:`kdb_printf` which emits messages directly
|
||||
- The implementation for kdb_printf() which emits messages directly
|
||||
to I/O drivers, bypassing the kernel log.
|
||||
|
||||
- SW / HW breakpoint management for the kdb shell
|
||||
|
|
@ -875,7 +875,7 @@ kernel when ``CONFIG_KDB_KEYBOARD=y`` is set in the kernel configuration.
|
|||
The core polled keyboard driver for PS/2 type keyboards is in
|
||||
``drivers/char/kdb_keyboard.c``. This driver is hooked into the debug core
|
||||
when kgdboc populates the callback in the array called
|
||||
:c:type:`kdb_poll_funcs[]`. The :c:func:`kdb_get_kbd_char` is the top-level
|
||||
:c:type:`kdb_poll_funcs[]`. The kdb_get_kbd_char() is the top-level
|
||||
function which polls hardware for single character input.
|
||||
|
||||
kgdboc and kms
|
||||
|
|
@ -887,10 +887,10 @@ that you have a video driver which has a frame buffer console and atomic
|
|||
kernel mode setting support.
|
||||
|
||||
Every time the kernel debugger is entered it calls
|
||||
:c:func:`kgdboc_pre_exp_handler` which in turn calls :c:func:`con_debug_enter`
|
||||
kgdboc_pre_exp_handler() which in turn calls con_debug_enter()
|
||||
in the virtual console layer. On resuming kernel execution, the kernel
|
||||
debugger calls :c:func:`kgdboc_post_exp_handler` which in turn calls
|
||||
:c:func:`con_debug_leave`.
|
||||
debugger calls kgdboc_post_exp_handler() which in turn calls
|
||||
con_debug_leave().
|
||||
|
||||
Any video driver that wants to be compatible with the kernel debugger
|
||||
and the atomic kms callbacks must implement the ``mode_set_base_atomic``,
|
||||
|
|
|
|||
|
|
@ -10,6 +10,15 @@ maintainers:
|
|||
- Eric Anholt <eric@anholt.net>
|
||||
- Stefan Wahren <wahrenst@gmx.net>
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: raspberrypi,bcm2835-firmware
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -273,8 +273,8 @@ properties:
|
|||
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
|
||||
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
|
||||
- myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
|
||||
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
|
||||
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / Bluetooth Module on Colibri Evaluation Board
|
||||
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Eval Board
|
||||
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT Module on Colibri Eval Board
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: Kontron N6411 S Board
|
||||
|
|
@ -312,9 +312,12 @@ properties:
|
|||
- toradex,colibri-imx7d # Colibri iMX7 Dual Module
|
||||
- toradex,colibri-imx7d-aster # Colibri iMX7 Dual Module on Aster Carrier Board
|
||||
- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
|
||||
- toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on Aster Carrier Board
|
||||
- toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on Colibri Evaluation Board V3
|
||||
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on Colibri Evaluation Board V3
|
||||
- toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on
|
||||
# Aster Carrier Board
|
||||
- toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on
|
||||
# Colibri Evaluation Board V3
|
||||
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on
|
||||
# Colibri Evaluation Board V3
|
||||
- tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM
|
||||
- zii,imx7d-rmu2 # ZII RMU2 Board
|
||||
- zii,imx7d-rpu2 # ZII RPU2 Board
|
||||
|
|
|
|||
|
|
@ -0,0 +1,44 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/keystone/ti,k3-sci-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Common K3 TI-SCI bindings
|
||||
|
||||
maintainers:
|
||||
- Nishanth Menon <nm@ti.com>
|
||||
|
||||
description: |
|
||||
The TI K3 family of SoCs usually have a central System Controller Processor
|
||||
that is responsible for managing various SoC-level resources like clocks,
|
||||
resets, interrupts etc. The communication with that processor is performed
|
||||
through the TI-SCI protocol.
|
||||
|
||||
Each specific device management node like a clock controller node, a reset
|
||||
controller node or an interrupt-controller node should define a common set
|
||||
of properties that enables them to implement the corresponding functionality
|
||||
over the TI-SCI protocol. The following are some of the common properties
|
||||
needed by such individual nodes. The required properties for each device
|
||||
management node is defined in the respective binding.
|
||||
|
||||
properties:
|
||||
ti,sci:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Should be a phandle to the TI-SCI System Controller node
|
||||
|
||||
ti,sci-dev-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Should contain the TI-SCI device id corresponding to the device. Please
|
||||
refer to the corresponding System Controller documentation for valid
|
||||
values for the desired device.
|
||||
|
||||
ti,sci-proc-ids:
|
||||
description: Should contain a single tuple of <proc_id host_id>.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- description: TI-SCI processor id for the remote processor device
|
||||
- description: TI-SCI host id to which processor control ownership
|
||||
should be transferred to
|
||||
|
|
@ -1,125 +0,0 @@
|
|||
Binding for IDT VersaClock 5,6 programmable i2c clock generators.
|
||||
|
||||
The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
|
||||
generators providing from 3 to 12 output clocks.
|
||||
|
||||
==I2C device node==
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be one of
|
||||
"idt,5p49v5923"
|
||||
"idt,5p49v5925"
|
||||
"idt,5p49v5933"
|
||||
"idt,5p49v5935"
|
||||
"idt,5p49v6901"
|
||||
"idt,5p49v6965"
|
||||
- reg: i2c device address, shall be 0x68 or 0x6a.
|
||||
- #clock-cells: from common clock binding; shall be set to 1.
|
||||
- clocks: from common clock binding; list of parent clock handles,
|
||||
- 5p49v5923 and
|
||||
5p49v5925 and
|
||||
5p49v6901: (required) either or both of XTAL or CLKIN
|
||||
reference clock.
|
||||
- 5p49v5933 and
|
||||
- 5p49v5935: (optional) property not present (internal
|
||||
Xtal used) or CLKIN reference
|
||||
clock.
|
||||
- clock-names: from common clock binding; clock input names, can be
|
||||
- 5p49v5923 and
|
||||
5p49v5925 and
|
||||
5p49v6901: (required) either or both of "xin", "clkin".
|
||||
- 5p49v5933 and
|
||||
- 5p49v5935: (optional) property not present or "clkin".
|
||||
|
||||
For all output ports, a corresponding, optional child node named OUT1,
|
||||
OUT2, etc. can represent a each output, and the node can be used to
|
||||
specify the following:
|
||||
|
||||
- itd,mode: can be one of the following:
|
||||
- VC5_LVPECL
|
||||
- VC5_CMOS
|
||||
- VC5_HCSL33
|
||||
- VC5_LVDS
|
||||
- VC5_CMOS2
|
||||
- VC5_CMOSD
|
||||
- VC5_HCSL25
|
||||
|
||||
- idt,voltage-microvolts: can be one of the following
|
||||
- 1800000
|
||||
- 2500000
|
||||
- 3300000
|
||||
- idt,slew-percent: Percent of normal, can be one of
|
||||
- 80
|
||||
- 85
|
||||
- 90
|
||||
- 100
|
||||
|
||||
==Mapping between clock specifier and physical pins==
|
||||
|
||||
When referencing the provided clock in the DT using phandle and
|
||||
clock specifier, the following mapping applies:
|
||||
|
||||
5P49V5923:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT2
|
||||
|
||||
5P49V5933:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT4
|
||||
|
||||
5P49V5925 and
|
||||
5P49V5935:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT2
|
||||
3 -- OUT3
|
||||
4 -- OUT4
|
||||
|
||||
5P49V6901:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT2
|
||||
3 -- OUT3
|
||||
4 -- OUT4
|
||||
|
||||
==Example==
|
||||
|
||||
/* 25MHz reference crystal */
|
||||
ref25: ref25m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
i2c-master-node {
|
||||
|
||||
/* IDT 5P49V5923 i2c clock generator */
|
||||
vc5: clock-generator@6a {
|
||||
compatible = "idt,5p49v5923";
|
||||
reg = <0x6a>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
/* Connect XIN input to 25MHz reference */
|
||||
clocks = <&ref25m>;
|
||||
clock-names = "xin";
|
||||
|
||||
OUT1 {
|
||||
itd,mode = <VC5_CMOS>;
|
||||
idt,voltage-microvolts = <1800000>;
|
||||
idt,slew-percent = <80>;
|
||||
};
|
||||
OUT2 {
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
/* Consumer referencing the 5P49V5923 pin OUT1 */
|
||||
consumer {
|
||||
...
|
||||
clocks = <&vc5 1>;
|
||||
...
|
||||
}
|
||||
154
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
Normal file
154
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
Normal file
|
|
@ -0,0 +1,154 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
|
||||
|
||||
description: |
|
||||
The IDT VersaClock 5 and VersaClock 6 are programmable I2C
|
||||
clock generators providing from 3 to 12 output clocks.
|
||||
|
||||
When referencing the provided clock in the DT using phandle and clock
|
||||
specifier, the following mapping applies:
|
||||
|
||||
- 5P49V5923:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT2
|
||||
|
||||
- 5P49V5933:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT4
|
||||
|
||||
- other parts:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT2
|
||||
3 -- OUT3
|
||||
4 -- OUT4
|
||||
|
||||
maintainers:
|
||||
- Luca Ceresoli <luca@lucaceresoli.net>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- idt,5p49v5923
|
||||
- idt,5p49v5925
|
||||
- idt,5p49v5933
|
||||
- idt,5p49v5935
|
||||
- idt,5p49v6901
|
||||
- idt,5p49v6965
|
||||
|
||||
reg:
|
||||
description: I2C device address
|
||||
enum: [ 0x68, 0x6a ]
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^OUT[1-4]$":
|
||||
type: object
|
||||
description:
|
||||
Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
|
||||
Configuration" in the Versaclock 5/6/6E Family Register Description
|
||||
and Programming Guide.
|
||||
properties:
|
||||
idt,mode:
|
||||
description:
|
||||
The output drive mode. Values defined in dt-bindings/clk/versaclock.h
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 6
|
||||
idt,voltage-microvolt:
|
||||
description: The output drive voltage.
|
||||
enum: [ 1800000, 2500000, 3300000 ]
|
||||
idt,slew-percent:
|
||||
description: The Slew rate control for CMOS single-ended.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 80, 85, 90, 100 ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- idt,5p49v5933
|
||||
- idt,5p49v5935
|
||||
then:
|
||||
# Devices with builtin crystal + optional external input
|
||||
properties:
|
||||
clock-names:
|
||||
const: clkin
|
||||
clocks:
|
||||
maxItems: 1
|
||||
else:
|
||||
# Devices without builtin crystal
|
||||
properties:
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
enum: [ xin, clkin ]
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clk/versaclock.h>
|
||||
|
||||
/* 25MHz reference crystal */
|
||||
ref25: ref25m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
reg = <0x0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* IDT 5P49V5923 I2C clock generator */
|
||||
vc5: clock-generator@6a {
|
||||
compatible = "idt,5p49v5923";
|
||||
reg = <0x6a>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
/* Connect XIN input to 25MHz reference */
|
||||
clocks = <&ref25m>;
|
||||
clock-names = "xin";
|
||||
|
||||
OUT1 {
|
||||
idt,drive-mode = <VC5_CMOSD>;
|
||||
idt,voltage-microvolts = <1800000>;
|
||||
idt,slew-percent = <80>;
|
||||
};
|
||||
|
||||
OUT4 {
|
||||
idt,drive-mode = <VC5_LVDS>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Consumer referencing the 5P49V5923 pin OUT1 */
|
||||
consumer {
|
||||
/* ... */
|
||||
clocks = <&vc5 1>;
|
||||
/* ... */
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,23 +1,31 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-gpucc.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for SDM845
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on SDM845.
|
||||
power domains on SDM845/SC7180/SM8150/SM8250.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-sdm845.h.
|
||||
See also:
|
||||
dt-bindings/clock/qcom,gpucc-sdm845.h
|
||||
dt-bindings/clock/qcom,gpucc-sc7180.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8150.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8250.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-gpucc
|
||||
enum:
|
||||
- qcom,sdm845-gpucc
|
||||
- qcom,sc7180-gpucc
|
||||
- qcom,sm8150-gpucc
|
||||
- qcom,sm8250-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,kryocc.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/qcom,msm8996-apcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm clock controller for MSM8996 CPUs
|
||||
|
|
@ -46,11 +46,9 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Example for msm8996
|
||||
- |
|
||||
kryocc: clock-controller@6400000 {
|
||||
compatible = "qcom,msm8996-apcc";
|
||||
reg = <0x6400000 0x90000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -1,74 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-sc7180.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: gcc_gpu_gpll0_clk_src
|
||||
- const: gcc_gpu_gpll0_div_clk_src
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@5090000 {
|
||||
compatible = "qcom,sc7180-gpucc";
|
||||
reg = <0x05090000 0x9000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_gpu_gpll0_clk_src",
|
||||
"gcc_gpu_gpll0_div_clk_src";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm LPASS Core Clock Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm LPASS core clock control module which supports the clocks and
|
||||
power domains on SC7180.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,lpasscorecc-sc7180.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-lpasshm
|
||||
- qcom,sc7180-lpasscorecc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: gcc_lpass_sway clock from GCC
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bi_tcxo
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: lpass core cc register
|
||||
- description: lpass audio cc register
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: lpass_core_cc
|
||||
- const: lpass_audio_cc
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,sc7180-lpasshm
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
|
||||
clock-controller@63000000 {
|
||||
compatible = "qcom,sc7180-lpasshm";
|
||||
reg = <0x63000000 0x28>;
|
||||
clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
|
||||
clock-controller@62d00000 {
|
||||
compatible = "qcom,sc7180-lpasscorecc";
|
||||
reg = <0x62d00000 0x50000>, <0x62780000 0x30000>;
|
||||
reg-names = "lpass_core_cc", "lpass_audio_cc";
|
||||
clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "bi_tcxo";
|
||||
power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -4,9 +4,15 @@ The RK3288 clock controller generates and supplies clock to various
|
|||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
A revision of this SoC is available: rk3288w. The clock tree is a bit
|
||||
different so another dt-compatible is available. Noticed that it is only
|
||||
setting the difference but there is no automatic revision detection. This
|
||||
should be performed by bootloaders.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3288-cru"
|
||||
- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
|
||||
case of this revision of Rockchip rk3288.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ properties:
|
|||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
compatible :
|
||||
compatible:
|
||||
enum:
|
||||
- sprd,sc9863a-ap-clk
|
||||
- sprd,sc9863a-aon-clk
|
||||
|
|
|
|||
|
|
@ -32,8 +32,7 @@ properties:
|
|||
- const: hdmi
|
||||
|
||||
ddc:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/phandle
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: >
|
||||
Phandle of the I2C controller used for DDC EDID probing
|
||||
|
||||
|
|
|
|||
|
|
@ -163,7 +163,6 @@ additionalProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
|
||||
#include <dt-bindings/clock/imx8mq-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- dlink,dir-685-panel
|
||||
|
||||
- const: ilitek,ili9322
|
||||
|
||||
reset-gpios: true
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- bananapi,lhr050h41
|
||||
|
||||
- const: ilitek,ili9881c
|
||||
|
||||
backlight: true
|
||||
|
|
|
|||
|
|
@ -147,4 +147,3 @@ examples:
|
|||
|
||||
...
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -177,10 +177,10 @@ properties:
|
|||
dependencies:
|
||||
# 'vendor,bool-property' is only allowed when 'vendor,string-array-property'
|
||||
# is present
|
||||
vendor,bool-property: [ vendor,string-array-property ]
|
||||
vendor,bool-property: [ 'vendor,string-array-property' ]
|
||||
# Expressing 2 properties in both orders means all of the set of properties
|
||||
# must be present or none of them.
|
||||
vendor,string-array-property: [ vendor,bool-property ]
|
||||
vendor,string-array-property: [ 'vendor,bool-property' ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
|
|||
|
|
@ -19,10 +19,8 @@ properties:
|
|||
|
||||
reg:
|
||||
items:
|
||||
- description: the I/O address containing the GPIO controller
|
||||
registers.
|
||||
- description: the I/O address containing the Chip Common A interrupt
|
||||
registers.
|
||||
- description: the I/O address containing the GPIO controller registers.
|
||||
- description: the I/O address containing the Chip Common A interrupt registers.
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
|
|
|
|||
|
|
@ -26,7 +26,8 @@ properties:
|
|||
- description: AXI/master interface clock
|
||||
- description: GPU core clock
|
||||
- description: Shader clock (only required if GPU has feature PIPE_3D)
|
||||
- description: AHB/slave interface clock (only required if GPU can gate slave interface independently)
|
||||
- description: AHB/slave interface clock (only required if GPU can gate
|
||||
slave interface independently)
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
|
|
|
|||
|
|
@ -1,39 +0,0 @@
|
|||
Qualcomm Hardware Mutex Block:
|
||||
|
||||
The hardware block provides mutexes utilized between different processors on
|
||||
the SoC as part of the communication protocol used by these processors.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be one of:
|
||||
"qcom,sfpb-mutex",
|
||||
"qcom,tcsr-mutex"
|
||||
|
||||
- syscon:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: one cell containing:
|
||||
syscon phandle
|
||||
offset of the hwmutex block within the syscon
|
||||
stride of the hwmutex registers
|
||||
|
||||
- #hwlock-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 1, the specified cell represent the lock id
|
||||
(hwlock standard property, see hwlock.txt)
|
||||
|
||||
Example:
|
||||
|
||||
tcsr_mutex_block: syscon@fd484000 {
|
||||
compatible = "syscon";
|
||||
reg = <0xfd484000 0x2000>;
|
||||
};
|
||||
|
||||
hwlock@fd484000 {
|
||||
compatible = "qcom,tcsr-mutex";
|
||||
syscon = <&tcsr_mutex_block 0 0x80>;
|
||||
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/hwlock/qcom-hwspinlock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Hardware Mutex Block
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description:
|
||||
The hardware block provides mutexes utilized between different processors on
|
||||
the SoC as part of the communication protocol used by these processors.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sfpb-mutex
|
||||
- qcom,tcsr-mutex
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#hwlock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#hwlock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
tcsr_mutex: hwlock@1f40000 {
|
||||
compatible = "qcom,tcsr-mutex";
|
||||
reg = <0x01f40000 0x40000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -14,6 +14,7 @@ Required properties:
|
|||
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
|
||||
"mediatek,mt8173-i2c": for MediaTek MT8173
|
||||
"mediatek,mt8183-i2c": for MediaTek MT8183
|
||||
"mediatek,mt8192-i2c": for MediaTek MT8192
|
||||
"mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
|
||||
- reg: physical base address of the controller and dma base, length of memory
|
||||
mapped region.
|
||||
|
|
|
|||
|
|
@ -72,6 +72,16 @@ wants to support one of the below features, it should adapt these bindings.
|
|||
this information to adapt power management to keep the arbitration awake
|
||||
all the time, for example. Can not be combined with 'single-master'.
|
||||
|
||||
- pinctrl
|
||||
add extra pinctrl to configure SCL/SDA pins to GPIO function for bus
|
||||
recovery, call it "gpio" or "recovery" (deprecated) state
|
||||
|
||||
- scl-gpios
|
||||
specify the gpio related to SCL pin. Used for GPIO bus recovery.
|
||||
|
||||
- sda-gpios
|
||||
specify the gpio related to SDA pin. Optional for GPIO bus recovery.
|
||||
|
||||
- single-master
|
||||
states that there is no other master active on this bus. The OS can use
|
||||
this information to detect a stalled bus more reliably, for example.
|
||||
|
|
|
|||
|
|
@ -26,6 +26,9 @@ properties:
|
|||
- items:
|
||||
- const: allwinner,sun50i-a64-i2c
|
||||
- const: allwinner,sun6i-a31-i2c
|
||||
- items:
|
||||
- const: allwinner,sun50i-a100-i2c
|
||||
- const: allwinner,sun6i-a31-i2c
|
||||
- items:
|
||||
- const: allwinner,sun50i-h6-i2c
|
||||
- const: allwinner,sun6i-a31-i2c
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ Required properties:
|
|||
"renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC.
|
||||
"renesas,i2c-r8a774b1" if the device is a part of a R8A774B1 SoC.
|
||||
"renesas,i2c-r8a774c0" if the device is a part of a R8A774C0 SoC.
|
||||
"renesas,i2c-r8a774e1" if the device is a part of a R8A774E1 SoC.
|
||||
"renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
|
||||
"renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.
|
||||
"renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ Required properties:
|
|||
- "renesas,iic-r8a774a1" (RZ/G2M)
|
||||
- "renesas,iic-r8a774b1" (RZ/G2N)
|
||||
- "renesas,iic-r8a774c0" (RZ/G2E)
|
||||
- "renesas,iic-r8a774e1" (RZ/G2H)
|
||||
- "renesas,iic-r8a7790" (R-Car H2)
|
||||
- "renesas,iic-r8a7791" (R-Car M2-W)
|
||||
- "renesas,iic-r8a7792" (R-Car V2H)
|
||||
|
|
|
|||
|
|
@ -97,13 +97,11 @@ patternProperties:
|
|||
input signal is multiplied. For example, <1 3> indicates the signal is scaled
|
||||
down to 1/3 of its value before ADC measurement.
|
||||
If property is not found default value depending on chip will be used.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
oneOf:
|
||||
- items:
|
||||
- const: 1
|
||||
- enum: [ 1, 3, 4, 6, 20, 8, 10 ]
|
||||
|
||||
- items:
|
||||
- const: 10
|
||||
- const: 81
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: HMC425A 6-bit Digital Step Attenuator
|
||||
|
||||
maintainers:
|
||||
- Michael Hennerich <michael.hennerich@analog.com>
|
||||
- Beniamin Bia <beniamin.bia@analog.com>
|
||||
- Michael Hennerich <michael.hennerich@analog.com>
|
||||
- Beniamin Bia <beniamin.bia@analog.com>
|
||||
|
||||
description: |
|
||||
Digital Step Attenuator IIO device with gpio interface.
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ properties:
|
|||
description: Output range of the channel.
|
||||
items:
|
||||
- const: 0
|
||||
- enum: [ 140000, 250000 ]
|
||||
- enum: [140000, 250000]
|
||||
|
||||
channel@2:
|
||||
description: Represents an external channel which are
|
||||
|
|
@ -103,7 +103,7 @@ properties:
|
|||
description: Output range of the channel.
|
||||
items:
|
||||
- const: 0
|
||||
- enum: [ 55000, 150000 ]
|
||||
- enum: [55000, 150000]
|
||||
|
||||
patternProperties:
|
||||
"^channel@([3-5])$":
|
||||
|
|
@ -119,16 +119,16 @@ patternProperties:
|
|||
description: Output range of the channel.
|
||||
items:
|
||||
- const: 0
|
||||
- enum: [ 45000, 100000 ]
|
||||
- enum: [45000, 100000]
|
||||
|
||||
required:
|
||||
- reg
|
||||
- channel@0
|
||||
- channel@1
|
||||
- channel@2
|
||||
- channel@3
|
||||
- channel@4
|
||||
- channel@5
|
||||
- reg
|
||||
- channel@0
|
||||
- channel@1
|
||||
- channel@2
|
||||
- channel@3
|
||||
- channel@4
|
||||
- channel@5
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ required:
|
|||
- touchscreen-max-pressure
|
||||
|
||||
examples:
|
||||
- |
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,58 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/input/touchscreen/eeti,exc3000.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: EETI EXC3000 series touchscreen controller
|
||||
|
||||
maintainers:
|
||||
- Dmitry Torokhov <dmitry.torokhov@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: touchscreen.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- eeti,exc3000
|
||||
- eeti,exc80h60
|
||||
- eeti,exc80h84
|
||||
reg:
|
||||
const: 0x2a
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
touchscreen-size-x: true
|
||||
touchscreen-size-y: true
|
||||
touchscreen-inverted-x: true
|
||||
touchscreen-inverted-y: true
|
||||
touchscreen-swapped-x-y: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- touchscreen-size-x
|
||||
- touchscreen-size-y
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include "dt-bindings/interrupt-controller/irq.h"
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
touchscreen@2a {
|
||||
compatible = "eeti,exc3000";
|
||||
reg = <0x2a>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
|
||||
touchscreen-size-x = <4096>;
|
||||
touchscreen-size-y = <4096>;
|
||||
touchscreen-inverted-x;
|
||||
touchscreen-swapped-x-y;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
* EETI EXC3000 Multiple Touch Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "eeti,exc3000"
|
||||
- reg: i2c slave address
|
||||
- interrupts: touch controller interrupt
|
||||
- touchscreen-size-x: See touchscreen.txt
|
||||
- touchscreen-size-y: See touchscreen.txt
|
||||
|
||||
Optional properties:
|
||||
- touchscreen-inverted-x: See touchscreen.txt
|
||||
- touchscreen-inverted-y: See touchscreen.txt
|
||||
- touchscreen-swapped-x-y: See touchscreen.txt
|
||||
|
||||
Example:
|
||||
|
||||
touchscreen@2a {
|
||||
compatible = "eeti,exc3000";
|
||||
reg = <0x2a>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
|
||||
touchscreen-size-x = <4096>;
|
||||
touchscreen-size-y = <4096>;
|
||||
touchscreen-inverted-x;
|
||||
touchscreen-swapped-x-y;
|
||||
};
|
||||
|
|
@ -35,9 +35,8 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
irq-gpios:
|
||||
description: GPIO pin used for IRQ.
|
||||
The driver uses the interrupt gpio pin as
|
||||
output to reset the device.
|
||||
description: GPIO pin used for IRQ. The driver uses the interrupt gpio pin
|
||||
as output to reset the device.
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
|
|
|
|||
|
|
@ -33,8 +33,8 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
touchscreen-min-pressure:
|
||||
description: minimum pressure on the touchscreen to be achieved in order for the
|
||||
touchscreen driver to report a touch event.
|
||||
description: minimum pressure on the touchscreen to be achieved in order
|
||||
for the touchscreen driver to report a touch event.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
touchscreen-fuzz-x:
|
||||
|
|
@ -46,13 +46,13 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
touchscreen-fuzz-pressure:
|
||||
description: pressure noise value of the absolute input device (arbitrary range
|
||||
dependent on the controller)
|
||||
description: pressure noise value of the absolute input device (arbitrary
|
||||
range dependent on the controller)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
touchscreen-average-samples:
|
||||
description: Number of data samples which are averaged for each read (valid values
|
||||
dependent on the controller)
|
||||
description: Number of data samples which are averaged for each read (valid
|
||||
values dependent on the controller)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
touchscreen-inverted-x:
|
||||
|
|
|
|||
|
|
@ -42,9 +42,8 @@ properties:
|
|||
Specifies the list of CPU interrupt vectors to which the GIC may not
|
||||
route interrupts. This property is ignored if the CPU is started in EIC
|
||||
mode.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#definitions/uint32-array
|
||||
- minItems: 1
|
||||
$ref: /schemas/types.yaml#definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 6
|
||||
uniqueItems: true
|
||||
items:
|
||||
|
|
@ -57,9 +56,8 @@ properties:
|
|||
It accepts two values: the 1st is the starting interrupt and the 2nd is
|
||||
the size of the reserved range. If not specified, the driver will
|
||||
allocate the last (2 * number of VPEs in the system).
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#definitions/uint32-array
|
||||
- items:
|
||||
$ref: /schemas/types.yaml#definitions/uint32-array
|
||||
items:
|
||||
- minimum: 0
|
||||
maximum: 254
|
||||
- minimum: 2
|
||||
|
|
|
|||
|
|
@ -37,7 +37,18 @@ properties:
|
|||
- enum:
|
||||
- qcom,sc7180-smmu-500
|
||||
- qcom,sdm845-smmu-500
|
||||
- qcom,sm8150-smmu-500
|
||||
- qcom,sm8250-smmu-500
|
||||
- const: arm,mmu-500
|
||||
- description: Marvell SoCs implementing "arm,mmu-500"
|
||||
items:
|
||||
- const: marvell,ap806-smmu-500
|
||||
- const: arm,mmu-500
|
||||
- description: NVIDIA SoCs that program two ARM MMU-500s identically
|
||||
items:
|
||||
- enum:
|
||||
- nvidia,tegra194-smmu
|
||||
- const: nvidia,smmu-500
|
||||
- items:
|
||||
- const: arm,mmu-500
|
||||
- const: arm,smmu-v2
|
||||
|
|
@ -55,7 +66,8 @@ properties:
|
|||
- cavium,smmu-v2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
'#global-interrupts':
|
||||
description: The number of global interrupts exposed by the device.
|
||||
|
|
@ -138,6 +150,23 @@ required:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra194-smmu
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
examples:
|
||||
- |+
|
||||
/* SMMU with stream matching or stream indexing */
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@ Required properties:
|
|||
- compatible : must be one of the following string:
|
||||
"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
|
||||
"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
|
||||
"mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW.
|
||||
"mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
|
||||
generation one m4u HW.
|
||||
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
|
||||
|
|
@ -78,6 +79,7 @@ Required properties:
|
|||
Specifies the mtk_m4u_id as defined in
|
||||
dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
|
||||
dt-binding/memory/mt2712-larb-port.h for mt2712,
|
||||
dt-binding/memory/mt6779-larb-port.h for mt6779,
|
||||
dt-binding/memory/mt8173-larb-port.h for mt8173, and
|
||||
dt-binding/memory/mt8183-larb-port.h for mt8183.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@ properties:
|
|||
- renesas,ipmmu-r8a774c0 # RZ/G2E
|
||||
- renesas,ipmmu-r8a7795 # R-Car H3
|
||||
- renesas,ipmmu-r8a7796 # R-Car M3-W
|
||||
- renesas,ipmmu-r8a77961 # R-Car M3-W+
|
||||
- renesas,ipmmu-r8a77965 # R-Car M3-N
|
||||
- renesas,ipmmu-r8a77970 # R-Car V3M
|
||||
- renesas,ipmmu-r8a77980 # R-Car V3H
|
||||
|
|
|
|||
|
|
@ -79,7 +79,8 @@ properties:
|
|||
description: |
|
||||
kHz; switching frequency.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, 1600, 1920, 2400, 3200, 4800, 9600 ]
|
||||
enum: [ 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, 1600, 1920,
|
||||
2400, 3200, 4800, 9600 ]
|
||||
|
||||
qcom,ovp:
|
||||
description: |
|
||||
|
|
|
|||
|
|
@ -58,8 +58,7 @@ allOf:
|
|||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
enum:
|
||||
- adi,adv7180
|
||||
- adi,adv7182
|
||||
- adi,adv7280
|
||||
|
|
|
|||
|
|
@ -38,9 +38,8 @@ properties:
|
|||
dongwoon,aac-mode:
|
||||
description:
|
||||
Indication of AAC mode select.
|
||||
allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
- enum:
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
enum:
|
||||
- 1 # AAC2 mode(operation time# 0.48 x Tvib)
|
||||
- 2 # AAC3 mode(operation time# 0.70 x Tvib)
|
||||
- 3 # AAC4 mode(operation time# 0.75 x Tvib)
|
||||
|
|
@ -51,9 +50,8 @@ properties:
|
|||
description:
|
||||
Number of AAC Timing count that controlled by one 6-bit period of
|
||||
vibration register AACT[5:0], the unit of which is 100 us.
|
||||
allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
- default: 0x20
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
default: 0x20
|
||||
minimum: 0x00
|
||||
maximum: 0x3f
|
||||
|
||||
|
|
@ -61,9 +59,8 @@ properties:
|
|||
description:
|
||||
Indication of VCM internal clock dividing rate select, as one multiple
|
||||
factor to calculate VCM ring periodic time Tvib.
|
||||
allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
- enum:
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
enum:
|
||||
- 0 # Dividing Rate - 2
|
||||
- 1 # Dividing Rate - 1
|
||||
- 2 # Dividing Rate - 1/2
|
||||
|
|
|
|||
|
|
@ -139,3 +139,4 @@ examples:
|
|||
};
|
||||
};
|
||||
...
|
||||
|
||||
|
|
|
|||
|
|
@ -65,13 +65,12 @@ properties:
|
|||
0x2d - RAW14
|
||||
0x2e - RAW16
|
||||
0x2f - RAW20
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- anyOf:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
oneOf:
|
||||
- minimum: 0x1e
|
||||
- maximum: 0x24
|
||||
maximum: 0x24
|
||||
- minimum: 0x28
|
||||
- maximum: 0x2f
|
||||
maximum: 0x2f
|
||||
|
||||
xlnx,vfb:
|
||||
type: boolean
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
|
|||
Mediatek SMI have two generations of HW architecture, here is the list
|
||||
which generation the SoCs use:
|
||||
generation 1: mt2701 and mt7623.
|
||||
generation 2: mt2712, mt8173 and mt8183.
|
||||
generation 2: mt2712, mt6779, mt8173 and mt8183.
|
||||
|
||||
There's slight differences between the two SMI, for generation 2, the
|
||||
register which control the iommu port is at each larb's register base. But
|
||||
|
|
@ -18,6 +18,7 @@ Required properties:
|
|||
- compatible : must be one of :
|
||||
"mediatek,mt2701-smi-common"
|
||||
"mediatek,mt2712-smi-common"
|
||||
"mediatek,mt6779-smi-common"
|
||||
"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
|
||||
"mediatek,mt8173-smi-common"
|
||||
"mediatek,mt8183-smi-common"
|
||||
|
|
@ -35,7 +36,7 @@ Required properties:
|
|||
and these 2 option clocks for generation 2 smi HW:
|
||||
- "gals0": the path0 clock of GALS(Global Async Local Sync).
|
||||
- "gals1": the path1 clock of GALS(Global Async Local Sync).
|
||||
Here is the list which has this GALS: mt8183.
|
||||
Here is the list which has this GALS: mt6779 and mt8183.
|
||||
|
||||
Example:
|
||||
smi_common: smi@14022000 {
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ Required properties:
|
|||
- compatible : must be one of :
|
||||
"mediatek,mt2701-smi-larb"
|
||||
"mediatek,mt2712-smi-larb"
|
||||
"mediatek,mt6779-smi-larb"
|
||||
"mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
|
||||
"mediatek,mt8173-smi-larb"
|
||||
"mediatek,mt8183-smi-larb"
|
||||
|
|
@ -21,7 +22,7 @@ Required properties:
|
|||
- "gals": the clock for GALS(Global Async Local Sync).
|
||||
Here is the list which has this GALS: mt8183.
|
||||
|
||||
Required property for mt2701, mt2712 and mt7623:
|
||||
Required property for mt2701, mt2712, mt6779 and mt7623:
|
||||
- mediatek,larb-id :the hardware id of this larb.
|
||||
|
||||
Example:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,252 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
|
||||
|
||||
description: |
|
||||
The FMC2 functional block makes the interface with: synchronous and
|
||||
asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
|
||||
peripherals) and NAND flash memories.
|
||||
Its main purposes are:
|
||||
- to translate AXI transactions into the appropriate external device
|
||||
protocol
|
||||
- to meet the access time requirements of the external devices
|
||||
All external devices share the addresses, data and control signals with the
|
||||
controller. Each external device is accessed by means of a unique Chip
|
||||
Select. The FMC2 performs only one access at a time to an external device.
|
||||
|
||||
maintainers:
|
||||
- Christophe Kerello <christophe.kerello@st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32mp1-fmc2-ebi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 2
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
ranges:
|
||||
description: |
|
||||
Reflects the memory layout with four integer values per bank. Format:
|
||||
<bank-number> 0 <address of the bank> <size>
|
||||
|
||||
patternProperties:
|
||||
"^.*@[0-4],[a-f0-9]+$":
|
||||
type: object
|
||||
|
||||
properties:
|
||||
reg:
|
||||
description: Bank number, base address and size of the device.
|
||||
|
||||
st,fmc2-ebi-cs-transaction-type:
|
||||
description: |
|
||||
Select one of the transactions type supported
|
||||
0: Asynchronous mode 1 SRAM/FRAM.
|
||||
1: Asynchronous mode 1 PSRAM.
|
||||
2: Asynchronous mode A SRAM/FRAM.
|
||||
3: Asynchronous mode A PSRAM.
|
||||
4: Asynchronous mode 2 NOR.
|
||||
5: Asynchronous mode B NOR.
|
||||
6: Asynchronous mode C NOR.
|
||||
7: Asynchronous mode D NOR.
|
||||
8: Synchronous read synchronous write PSRAM.
|
||||
9: Synchronous read asynchronous write PSRAM.
|
||||
10: Synchronous read synchronous write NOR.
|
||||
11: Synchronous read asynchronous write NOR.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 11
|
||||
|
||||
st,fmc2-ebi-cs-cclk-enable:
|
||||
description: Continuous clock enable (first bank must be configured
|
||||
in synchronous mode). The FMC_CLK is generated continuously
|
||||
during asynchronous and synchronous access. By default, the
|
||||
FMC_CLK is only generated during synchronous access.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
st,fmc2-ebi-cs-mux-enable:
|
||||
description: Address/Data multiplexed on databus (valid only with
|
||||
NOR and PSRAM transactions type). By default, Address/Data
|
||||
are not multiplexed.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
st,fmc2-ebi-cs-buswidth:
|
||||
description: Data bus width
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 8, 16 ]
|
||||
default: 16
|
||||
|
||||
st,fmc2-ebi-cs-waitpol-high:
|
||||
description: Wait signal polarity (NWAIT signal active high).
|
||||
By default, NWAIT is active low.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
st,fmc2-ebi-cs-waitcfg-enable:
|
||||
description: The NWAIT signal indicates wheither the data from the
|
||||
device are valid or if a wait state must be inserted when accessing
|
||||
the device in synchronous mode. By default, the NWAIT signal is
|
||||
active one data cycle before wait state.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
st,fmc2-ebi-cs-wait-enable:
|
||||
description: The NWAIT signal is enabled (its level is taken into
|
||||
account after the programmed latency period to insert wait states
|
||||
if asserted). By default, the NWAIT signal is disabled.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
st,fmc2-ebi-cs-asyncwait-enable:
|
||||
description: The NWAIT signal is taken into account during asynchronous
|
||||
transactions. By default, the NWAIT signal is not taken into account
|
||||
during asynchronous transactions.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
st,fmc2-ebi-cs-cpsize:
|
||||
description: CRAM page size. The controller splits the burst access
|
||||
when the memory page is reached. By default, no burst split when
|
||||
crossing page boundary.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 0, 128, 256, 512, 1024 ]
|
||||
default: 0
|
||||
|
||||
st,fmc2-ebi-cs-byte-lane-setup-ns:
|
||||
description: This property configures the byte lane setup timing
|
||||
defined in nanoseconds from NBLx low to Chip Select NEx low.
|
||||
|
||||
st,fmc2-ebi-cs-address-setup-ns:
|
||||
description: This property defines the duration of the address setup
|
||||
phase in nanoseconds used for asynchronous read/write transactions.
|
||||
|
||||
st,fmc2-ebi-cs-address-hold-ns:
|
||||
description: This property defines the duration of the address hold
|
||||
phase in nanoseconds used for asynchronous multiplexed read/write
|
||||
transactions.
|
||||
|
||||
st,fmc2-ebi-cs-data-setup-ns:
|
||||
description: This property defines the duration of the data setup phase
|
||||
in nanoseconds used for asynchronous read/write transactions.
|
||||
|
||||
st,fmc2-ebi-cs-bus-turnaround-ns:
|
||||
description: This property defines the delay in nanoseconds between the
|
||||
end of current read/write transaction and the next transaction.
|
||||
|
||||
st,fmc2-ebi-cs-data-hold-ns:
|
||||
description: This property defines the duration of the data hold phase
|
||||
in nanoseconds used for asynchronous read/write transactions.
|
||||
|
||||
st,fmc2-ebi-cs-clk-period-ns:
|
||||
description: This property defines the FMC_CLK output signal period in
|
||||
nanoseconds.
|
||||
|
||||
st,fmc2-ebi-cs-data-latency-ns:
|
||||
description: This property defines the data latency before reading or
|
||||
writing the first data in nanoseconds.
|
||||
|
||||
st,fmc2_ebi-cs-write-address-setup-ns:
|
||||
description: This property defines the duration of the address setup
|
||||
phase in nanoseconds used for asynchronous write transactions.
|
||||
|
||||
st,fmc2-ebi-cs-write-address-hold-ns:
|
||||
description: This property defines the duration of the address hold
|
||||
phase in nanoseconds used for asynchronous multiplexed write
|
||||
transactions.
|
||||
|
||||
st,fmc2-ebi-cs-write-data-setup-ns:
|
||||
description: This property defines the duration of the data setup
|
||||
phase in nanoseconds used for asynchronous write transactions.
|
||||
|
||||
st,fmc2-ebi-cs-write-bus-turnaround-ns:
|
||||
description: This property defines the delay between the end of current
|
||||
write transaction and the next transaction in nanoseconds.
|
||||
|
||||
st,fmc2-ebi-cs-write-data-hold-ns:
|
||||
description: This property defines the duration of the data hold phase
|
||||
in nanoseconds used for asynchronous write transactions.
|
||||
|
||||
st,fmc2-ebi-cs-max-low-pulse-ns:
|
||||
description: This property defines the maximum chip select low pulse
|
||||
duration in nanoseconds for synchronous transactions. When this timing
|
||||
reaches 0, the controller splits the current access, toggles NE to
|
||||
allow device refresh and restarts a new access.
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
required:
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- ranges
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
memory-controller@58002000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp1-fmc2-ebi";
|
||||
reg = <0x58002000 0x1000>;
|
||||
clocks = <&rcc FMC_K>;
|
||||
resets = <&rcc FMC_R>;
|
||||
|
||||
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
|
||||
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
|
||||
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
|
||||
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
|
||||
<4 0 0x80000000 0x10000000>; /* NAND */
|
||||
|
||||
psram@0,0 {
|
||||
compatible = "mtd-ram";
|
||||
reg = <0 0x00000000 0x100000>;
|
||||
bank-width = <2>;
|
||||
|
||||
st,fmc2-ebi-cs-transaction-type = <1>;
|
||||
st,fmc2-ebi-cs-address-setup-ns = <60>;
|
||||
st,fmc2-ebi-cs-data-setup-ns = <30>;
|
||||
st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
|
||||
};
|
||||
|
||||
nand-controller@4,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32mp1-fmc2-nfc";
|
||||
reg = <4 0x00000000 0x1000>,
|
||||
<4 0x08010000 0x1000>,
|
||||
<4 0x08020000 0x1000>,
|
||||
<4 0x01000000 0x1000>,
|
||||
<4 0x09010000 0x1000>,
|
||||
<4 0x09020000 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
|
||||
<&mdma1 20 0x2 0x12000a08 0x0 0x0>,
|
||||
<&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
|
||||
dma-names = "tx", "rx", "ecc";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-on-flash-bbt;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
ChromeOS Embedded Controller
|
||||
|
||||
Google's ChromeOS EC is a Cortex-M device which talks to the AP and
|
||||
implements various function such as keyboard and battery charging.
|
||||
|
||||
The EC can be connect through various means (I2C, SPI, LPC, RPMSG) and the
|
||||
compatible string used depends on the interface. Each connection method has
|
||||
its own driver which connects to the top level interface-agnostic EC driver.
|
||||
Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to
|
||||
the top-level driver.
|
||||
|
||||
Required properties (I2C):
|
||||
- compatible: "google,cros-ec-i2c"
|
||||
- reg: I2C slave address
|
||||
|
||||
Required properties (SPI):
|
||||
- compatible: "google,cros-ec-spi"
|
||||
- reg: SPI chip select
|
||||
|
||||
Required properties (RPMSG):
|
||||
- compatible: "google,cros-ec-rpmsg"
|
||||
|
||||
Optional properties (SPI):
|
||||
- google,cros-ec-spi-pre-delay: Some implementations of the EC need a little
|
||||
time to wake up from sleep before they can receive SPI transfers at a high
|
||||
clock rate. This property specifies the delay, in usecs, between the
|
||||
assertion of the CS to the start of the first clock pulse.
|
||||
- google,cros-ec-spi-msg-delay: Some implementations of the EC require some
|
||||
additional processing time in order to accept new transactions. If the delay
|
||||
between transactions is not long enough the EC may not be able to respond
|
||||
properly to subsequent transactions and cause them to hang. This property
|
||||
specifies the delay, in usecs, introduced between transactions to account
|
||||
for the time required by the EC to get back into a state in which new data
|
||||
can be accepted.
|
||||
|
||||
Required properties (LPC):
|
||||
- compatible: "google,cros-ec-lpc"
|
||||
- reg: List of (IO address, size) pairs defining the interface uses
|
||||
|
||||
Optional properties (all):
|
||||
- google,has-vbc-nvram: Some implementations of the EC include a small
|
||||
nvram space used to store verified boot context data. This boolean flag
|
||||
is used to specify whether this nvram is present or not.
|
||||
|
||||
Example for I2C:
|
||||
|
||||
i2c@12ca0000 {
|
||||
cros-ec@1e {
|
||||
reg = <0x1e>;
|
||||
compatible = "google,cros-ec-i2c";
|
||||
interrupts = <14 0>;
|
||||
interrupt-parent = <&wakeup_eint>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
|
||||
Example for SPI:
|
||||
|
||||
spi@131b0000 {
|
||||
ec@0 {
|
||||
compatible = "google,cros-ec-spi";
|
||||
reg = <0x0>;
|
||||
interrupts = <14 0>;
|
||||
interrupt-parent = <&wakeup_eint>;
|
||||
wakeup-source;
|
||||
spi-max-frequency = <5000000>;
|
||||
controller-data {
|
||||
cs-gpio = <&gpf0 3 4 3 0>;
|
||||
samsung,spi-cs;
|
||||
samsung,spi-feedback-delay = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example for LPC is not supplied as it is not yet implemented.
|
||||
|
|
@ -79,11 +79,12 @@ properties:
|
|||
description: |
|
||||
conversion mode:
|
||||
0 - temperature, in C*10
|
||||
1 - pre-scaled voltage value
|
||||
1 - pre-scaled 24-bit voltage value
|
||||
2 - scaled voltage based on an optional resistor divider
|
||||
and optional offset
|
||||
3 - pre-scaled 16-bit voltage value
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2]
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
gw,voltage-divider-ohms:
|
||||
description: Values of resistors for divider on raw ADC input
|
||||
|
|
|
|||
129
Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
Normal file
129
Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ChromeOS Embedded Controller
|
||||
|
||||
maintainers:
|
||||
- Benson Leung <bleung@chromium.org>
|
||||
- Enric Balletbo i Serra <enric.balletbo@collabora.com>
|
||||
- Guenter Roeck <groeck@chromium.org>
|
||||
|
||||
description:
|
||||
Google's ChromeOS EC is a microcontroller which talks to the AP and
|
||||
implements various functions such as keyboard and battery charging.
|
||||
The EC can be connected through various interfaces (I2C, SPI, and others)
|
||||
and the compatible string specifies which interface is being used.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description:
|
||||
For implementations of the EC is connected through I2C.
|
||||
const: google,cros-ec-i2c
|
||||
- description:
|
||||
For implementations of the EC is connected through SPI.
|
||||
const: google,cros-ec-spi
|
||||
- description:
|
||||
For implementations of the EC is connected through RPMSG.
|
||||
const: google,cros-ec-rpmsg
|
||||
|
||||
google,cros-ec-spi-pre-delay:
|
||||
description:
|
||||
This property specifies the delay in usecs between the
|
||||
assertion of the CS and the first clock pulse.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- default: 0
|
||||
- minimum: 0
|
||||
|
||||
google,cros-ec-spi-msg-delay:
|
||||
description:
|
||||
This property specifies the delay in usecs between messages.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- default: 0
|
||||
- minimum: 0
|
||||
|
||||
google,has-vbc-nvram:
|
||||
description:
|
||||
Some implementations of the EC include a small nvram space used to
|
||||
store verified boot context data. This boolean flag is used to specify
|
||||
whether this nvram is present or not.
|
||||
type: boolean
|
||||
|
||||
spi-max-frequency:
|
||||
description: Maximum SPI frequency of the device in Hz.
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- google,cros-ec-i2c
|
||||
- google,cros-ec-rpmsg
|
||||
then:
|
||||
properties:
|
||||
google,cros-ec-spi-pre-delay: false
|
||||
google,cros-ec-spi-msg-delay: false
|
||||
spi-max-frequency: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Example for I2C
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cros-ec@1e {
|
||||
compatible = "google,cros-ec-i2c";
|
||||
reg = <0x1e>;
|
||||
interrupts = <6 0>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
};
|
||||
};
|
||||
|
||||
# Example for SPI
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
spi0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cros-ec@0 {
|
||||
compatible = "google,cros-ec-spi";
|
||||
reg = <0x0>;
|
||||
google,cros-ec-spi-msg-delay = <30>;
|
||||
google,cros-ec-spi-pre-delay = <10>;
|
||||
interrupts = <99 0>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
spi-max-frequency = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
# Example for RPMSG
|
||||
- |
|
||||
scp0 {
|
||||
cros-ec {
|
||||
compatible = "google,cros-ec-rpmsg";
|
||||
};
|
||||
};
|
||||
...
|
||||
44
Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
Normal file
44
Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mfd/khadas,mcu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Khadas on-board Microcontroller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
|
||||
description: |
|
||||
Khadas embeds a microcontroller on their VIM and Edge boards adding some
|
||||
system feature as PWM Fan control (for VIM2 rev14 or VIM3), User memory
|
||||
storage, IR/Key resume control, system power LED control and more.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- khadas,mcu # MCU revision is discoverable
|
||||
|
||||
"#cooling-cells": # Only needed for boards having FAN control feature
|
||||
const: 2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
khadas_mcu: system-controller@18 {
|
||||
compatible = "khadas,mcu";
|
||||
reg = <0x18>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -33,6 +33,9 @@ properties:
|
|||
items:
|
||||
- const: mux
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
|
|
@ -106,11 +109,13 @@ additionalProperties: false
|
|||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
timer@40002400 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x40002400 0x400>;
|
||||
clocks = <&timer_clk>;
|
||||
clock-names = "mux";
|
||||
interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
|
|||
122
Documentation/devicetree/bindings/mfd/st,stmfx.yaml
Normal file
122
Documentation/devicetree/bindings/mfd/st,stmfx.yaml
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mfd/st,stmfx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectonics Multi-Function eXpander (STMFX) bindings
|
||||
|
||||
description: ST Multi-Function eXpander (STMFX) is a slave controller using I2C for
|
||||
communication with the main MCU. Its main features are GPIO expansion,
|
||||
main MCU IDD measurement (IDD is the amount of current that flows
|
||||
through VDD) and resistive touchscreen controller.
|
||||
|
||||
maintainers:
|
||||
- Amelie Delaunay <amelie.delaunay@st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stmfx-0300
|
||||
|
||||
reg:
|
||||
enum: [ 0x42, 0x43 ]
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
drive-open-drain: true
|
||||
|
||||
vdd-supply:
|
||||
maxItems: 1
|
||||
|
||||
pinctrl:
|
||||
type: object
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stmfx-0300-pinctrl
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
gpio-ranges:
|
||||
description: if all STMFX pins[24:0] are available (no other STMFX function in use),
|
||||
you should use gpio-ranges = <&stmfx_pinctrl 0 0 24>;
|
||||
if agpio[3:0] are not available (STMFX Touchscreen function in use),
|
||||
you should use gpio-ranges = <&stmfx_pinctrl 0 0 16>, <&stmfx_pinctrl 20 20 4>;
|
||||
if agpio[7:4] are not available (STMFX IDD function in use),
|
||||
you should use gpio-ranges = <&stmfx_pinctrl 0 0 20>;
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
"^[a-zA-Z]*-pins$":
|
||||
type: object
|
||||
|
||||
allOf:
|
||||
- $ref: ../pinctrl/pinmux-node.yaml
|
||||
|
||||
properties:
|
||||
pins: true
|
||||
bias-disable: true
|
||||
bias-pull-up: true
|
||||
bias-pull-pin-default: true
|
||||
bias-pull-down: true
|
||||
drive-open-drain: true
|
||||
drive-push-pull: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#gpio-cells"
|
||||
- "#interrupt-cells"
|
||||
- gpio-controller
|
||||
- interrupt-controller
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
stmfx@42 {
|
||||
compatible = "st,stmfx-0300";
|
||||
reg = <0x42>;
|
||||
interrupts = <8 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-parent = <&gpioi>;
|
||||
vdd-supply = <&v3v3>;
|
||||
|
||||
stmfx_pinctrl: pinctrl {
|
||||
compatible = "st,stmfx-0300-pinctrl";
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
gpio-ranges = <&stmfx_pinctrl 0 0 24>;
|
||||
|
||||
joystick_pins: joystick-pins {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -113,8 +113,8 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
st,mask-reset:
|
||||
description: mask reset for this regulator,
|
||||
the regulator configuration is maintained during pmic reset.
|
||||
description: mask reset for this regulator, the regulator configuration
|
||||
is maintained during pmic reset.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
regulator-name: true
|
||||
|
|
@ -135,8 +135,8 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
st,mask-reset:
|
||||
description: mask reset for this regulator,
|
||||
the regulator configuration is maintained during pmic reset.
|
||||
description: mask reset for this regulator, the regulator configuration
|
||||
is maintained during pmic reset.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
regulator-name: true
|
||||
|
|
@ -154,8 +154,8 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
st,mask-reset:
|
||||
description: mask reset for this regulator,
|
||||
the regulator configuration is maintained during pmic reset.
|
||||
description: mask reset for this regulator, the regulator configuration
|
||||
is maintained during pmic reset.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
regulator-name: true
|
||||
|
|
@ -172,8 +172,8 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
st,mask-reset:
|
||||
description: mask reset for this regulator,
|
||||
the regulator configuration is maintained during pmic reset.
|
||||
description: mask reset for this regulator, the regulator configuration
|
||||
is maintained during pmic reset.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
regulator-name: true
|
||||
|
|
@ -198,8 +198,8 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
st,mask-reset:
|
||||
description: mask reset for this regulator,
|
||||
the regulator configuration is maintained during pmic reset.
|
||||
description: mask reset for this regulator, the regulator configuration
|
||||
is maintained during pmic reset.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
regulator-name: true
|
||||
|
|
@ -220,8 +220,8 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
st,mask-reset:
|
||||
description: mask reset for this regulator,
|
||||
the regulator configuration is maintained during pmic reset.
|
||||
description: mask reset for this regulator, the regulator configuration
|
||||
is maintained during pmic reset.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
regulator-name: true
|
||||
|
|
|
|||
|
|
@ -1,28 +0,0 @@
|
|||
STMicroelectonics Multi-Function eXpander (STMFX) Core bindings
|
||||
|
||||
ST Multi-Function eXpander (STMFX) is a slave controller using I2C for
|
||||
communication with the main MCU. Its main features are GPIO expansion, main
|
||||
MCU IDD measurement (IDD is the amount of current that flows through VDD) and
|
||||
resistive touchscreen controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "st,stmfx-0300".
|
||||
- reg: I2C slave address of the device.
|
||||
- interrupts: interrupt specifier triggered by MFX_IRQ_OUT signal.
|
||||
Please refer to ../interrupt-controller/interrupt.txt
|
||||
|
||||
Optional properties:
|
||||
- drive-open-drain: configure MFX_IRQ_OUT as open drain.
|
||||
- vdd-supply: phandle of the regulator supplying STMFX.
|
||||
|
||||
Example:
|
||||
|
||||
stmfx: stmfx@42 {
|
||||
compatible = "st,stmfx-0300";
|
||||
reg = <0x42>;
|
||||
interrupts = <8 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-parent = <&gpioi>;
|
||||
vdd-supply = <&v3v3>;
|
||||
};
|
||||
|
||||
Please refer to ../pinctrl/pinctrl-stmfx.txt for STMFX GPIO expander function bindings.
|
||||
|
|
@ -24,8 +24,7 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
anyOf:
|
||||
- items:
|
||||
items:
|
||||
- enum:
|
||||
- ti,j721e-system-controller
|
||||
- const: syscon
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ Optional node:
|
|||
Example:
|
||||
/*
|
||||
* Integrated Power Management Chip
|
||||
* http://www.ti.com/lit/ds/symlink/twl6030.pdf
|
||||
* https://www.ti.com/lit/ds/symlink/twl6030.pdf
|
||||
*/
|
||||
twl@48 {
|
||||
compatible = "ti,twl6030";
|
||||
|
|
|
|||
|
|
@ -14,12 +14,10 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
items:
|
||||
- enum:
|
||||
- xlnx,zynqmp-nand-controller
|
||||
- enum:
|
||||
- arasan,nfc-v3p10
|
||||
- const: arasan,nfc-v3p10
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@ This file provides information, what the device node for the davinci/keystone
|
|||
NAND interface contains.
|
||||
|
||||
Documentation:
|
||||
Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
|
||||
Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
|
||||
Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
|
||||
Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
|
||||
|
||||
Required properties:
|
||||
|
||||
|
|
|
|||
|
|
@ -7,14 +7,16 @@ Required properties:
|
|||
- fsl,upm-cmd-offset : UPM pattern offset for the command latch.
|
||||
|
||||
Optional properties:
|
||||
- fsl,upm-wait-flags : add chip-dependent short delays after running the
|
||||
UPM pattern (0x1), after writing a data byte (0x2) or after
|
||||
writing out a buffer (0x4).
|
||||
- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
|
||||
The corresponding address lines are used to select the chip.
|
||||
- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
|
||||
(R/B#). For multi-chip devices, "n" GPIO definitions are required
|
||||
according to the number of chips.
|
||||
|
||||
Deprecated properties:
|
||||
- fsl,upm-wait-flags : add chip-dependent short delays after running the
|
||||
UPM pattern (0x1), after writing a data byte (0x2) or after
|
||||
writing out a buffer (0x4).
|
||||
- chip-delay : chip dependent delay for transferring data from array to
|
||||
read registers (tR). Required if property "gpios" is not used
|
||||
(R/B# pins not connected).
|
||||
|
|
@ -52,8 +54,6 @@ upm@3,0 {
|
|||
fsl,upm-cmd-offset = <0x08>;
|
||||
/* Multi-chip NAND device */
|
||||
fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
|
||||
fsl,upm-wait-flags = <0x5>;
|
||||
chip-delay = <25>; // in micro-seconds
|
||||
|
||||
nand@0 {
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -114,6 +114,13 @@ patternProperties:
|
|||
description:
|
||||
Contains the native Ready/Busy IDs.
|
||||
|
||||
rb-gpios:
|
||||
description:
|
||||
Contains one or more GPIO descriptor (the numper of descriptor
|
||||
depends on the number of R/B pins exposed by the flash) for the
|
||||
Ready/Busy pins. Active state refers to the NAND ready state and
|
||||
should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
|
|
|
|||
|
|
@ -9,32 +9,19 @@ title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
|
|||
maintainers:
|
||||
- Christophe Kerello <christophe.kerello@st.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "nand-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32mp15-fmc2
|
||||
enum:
|
||||
- st,stm32mp15-fmc2
|
||||
- st,stm32mp1-fmc2-nfc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Registers
|
||||
- description: Chip select 0 data
|
||||
- description: Chip select 0 command
|
||||
- description: Chip select 0 address space
|
||||
- description: Chip select 1 data
|
||||
- description: Chip select 1 command
|
||||
- description: Chip select 1 address space
|
||||
minItems: 6
|
||||
maxItems: 7
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: tx DMA channel
|
||||
|
|
@ -55,13 +42,57 @@ patternProperties:
|
|||
const: 512
|
||||
|
||||
nand-ecc-strength:
|
||||
enum: [1, 4 ,8 ]
|
||||
enum: [1, 4, 8]
|
||||
|
||||
allOf:
|
||||
- $ref: "nand-controller.yaml#"
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: st,stm32mp15-fmc2
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: Registers
|
||||
- description: Chip select 0 data
|
||||
- description: Chip select 0 command
|
||||
- description: Chip select 0 address space
|
||||
- description: Chip select 1 data
|
||||
- description: Chip select 1 command
|
||||
- description: Chip select 1 address space
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: st,stm32mp1-fmc2-nfc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: Chip select 0 data
|
||||
- description: Chip select 0 command
|
||||
- description: Chip select 0 address space
|
||||
- description: Chip select 1 data
|
||||
- description: Chip select 1 command
|
||||
- description: Chip select 1 address space
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
@ -78,9 +109,9 @@ examples:
|
|||
<0x89010000 0x1000>,
|
||||
<0x89020000 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
|
||||
<&mdma1 20 0x10 0x12000a08 0x0 0x0>,
|
||||
<&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
|
||||
dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
|
||||
<&mdma1 20 0x2 0x12000a08 0x0 0x0>,
|
||||
<&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
|
||||
dma-names = "tx", "rx", "ecc";
|
||||
clocks = <&rcc FMC_K>;
|
||||
resets = <&rcc FMC_R>;
|
||||
|
|
|
|||
|
|
@ -31,8 +31,7 @@ properties:
|
|||
ti,syscon-pcie-ctrl:
|
||||
description: Phandle to the SYSCON entry required for configuring PCIe mode
|
||||
and link speed.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/phandle
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -31,8 +31,7 @@ properties:
|
|||
ti,syscon-pcie-ctrl:
|
||||
description: Phandle to the SYSCON entry required for configuring PCIe mode
|
||||
and link speed.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/phandle
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -73,8 +73,7 @@ properties:
|
|||
|
||||
vddp-ref-clk-supply:
|
||||
description:
|
||||
Phandle to a regulator supply to any specific refclk
|
||||
pll block.
|
||||
Phandle to a regulator supply to any specific refclk pll block.
|
||||
|
||||
#Required nodes:
|
||||
patternProperties:
|
||||
|
|
|
|||
|
|
@ -70,8 +70,7 @@ properties:
|
|||
|
||||
vddp-ref-clk-supply:
|
||||
description:
|
||||
Phandle to a regulator supply to any specific refclk
|
||||
pll block.
|
||||
Phandle to a regulator supply to any specific refclk pll block.
|
||||
|
||||
#Required nodes:
|
||||
patternProperties:
|
||||
|
|
|
|||
|
|
@ -203,7 +203,8 @@ examples:
|
|||
};
|
||||
|
||||
refclk-dig {
|
||||
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
|
||||
<&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz0_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 292 11>;
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ patternProperties:
|
|||
patternProperties:
|
||||
"^function|groups$":
|
||||
$ref: "/schemas/types.yaml#/definitions/string"
|
||||
enum: [ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
|
||||
enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
|
||||
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
|
||||
EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0,
|
||||
GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4,
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ patternProperties:
|
|||
patternProperties:
|
||||
"^function|groups$":
|
||||
$ref: "/schemas/types.yaml#/definitions/string"
|
||||
enum: [ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
|
||||
enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
|
||||
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
|
||||
ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2,
|
||||
GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5,
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ patternProperties:
|
|||
properties:
|
||||
function:
|
||||
$ref: "/schemas/types.yaml#/definitions/string"
|
||||
enum: [ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
|
||||
enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
|
||||
ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT,
|
||||
FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
|
||||
GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5,
|
||||
|
|
@ -52,11 +52,11 @@ patternProperties:
|
|||
TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0,
|
||||
THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12,
|
||||
UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
|
||||
USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4]
|
||||
USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ]
|
||||
|
||||
groups:
|
||||
$ref: "/schemas/types.yaml#/definitions/string"
|
||||
enum: [ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
|
||||
enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
|
||||
ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4,
|
||||
EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWQSPID, FWSPIWP,
|
||||
GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
|
||||
|
|
|
|||
|
|
@ -1,81 +0,0 @@
|
|||
Ingenic XBurst pin controller
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
|
||||
be used as GPIOs, multiplexed device functions are configured within the
|
||||
GPIO port configuration registers and it is typical to refer to pins using the
|
||||
naming scheme "PxN" where x is a character identifying the GPIO port with
|
||||
which the pin is associated and N is an integer from 0 to 31 identifying the
|
||||
pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
|
||||
PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
|
||||
contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
|
||||
jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
|
||||
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
|
||||
- compatible: One of:
|
||||
- "ingenic,jz4740-pinctrl"
|
||||
- "ingenic,jz4725b-pinctrl"
|
||||
- "ingenic,jz4760-pinctrl"
|
||||
- "ingenic,jz4760b-pinctrl"
|
||||
- "ingenic,jz4770-pinctrl"
|
||||
- "ingenic,jz4780-pinctrl"
|
||||
- "ingenic,x1000-pinctrl"
|
||||
- "ingenic,x1000e-pinctrl"
|
||||
- "ingenic,x1500-pinctrl"
|
||||
- "ingenic,x1830-pinctrl"
|
||||
- reg: Address range of the pinctrl registers.
|
||||
|
||||
|
||||
Required properties for sub-nodes (GPIO chips):
|
||||
-----------------------------------------------
|
||||
|
||||
- compatible: Must contain one of:
|
||||
- "ingenic,jz4740-gpio"
|
||||
- "ingenic,jz4760-gpio"
|
||||
- "ingenic,jz4770-gpio"
|
||||
- "ingenic,jz4780-gpio"
|
||||
- "ingenic,x1000-gpio"
|
||||
- "ingenic,x1830-gpio"
|
||||
- reg: The GPIO bank number.
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- interrupts: Interrupt specifier for the controllers interrupt.
|
||||
- #interrupt-cells: Should be 2. Refer to
|
||||
../interrupt-controller/interrupts.txt for more details.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
|
||||
cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
|
||||
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
|
||||
- gpio-ranges: Range of pins managed by the GPIO controller. Refer to
|
||||
../gpio/gpio.txt for more details.
|
||||
|
||||
|
||||
Example:
|
||||
--------
|
||||
|
||||
pinctrl: pin-controller@10010000 {
|
||||
compatible = "ingenic,jz4740-pinctrl";
|
||||
reg = <0x10010000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpa: gpio@0 {
|
||||
compatible = "ingenic,jz4740-gpio";
|
||||
reg = <0>;
|
||||
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <28>;
|
||||
};
|
||||
};
|
||||
176
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
Normal file
176
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
Normal file
|
|
@ -0,0 +1,176 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Ingenic SoCs pin controller devicetree bindings
|
||||
|
||||
description: >
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins
|
||||
may be used as GPIOs, multiplexed device functions are configured within the
|
||||
GPIO port configuration registers and it is typical to refer to pins using the
|
||||
naming scheme "PxN" where x is a character identifying the GPIO port with
|
||||
which the pin is associated and N is an integer from 0 to 31 identifying the
|
||||
pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
|
||||
and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and the X1830
|
||||
contains 4 GPIO ports, PA to PD, for a total of 128 pins. The JZ4760, the
|
||||
JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total of 192
|
||||
pins.
|
||||
|
||||
maintainers:
|
||||
- Paul Cercueil <paul@crapouillou.net>
|
||||
|
||||
properties:
|
||||
nodename:
|
||||
pattern: "^pinctrl@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- ingenic,jz4740-pinctrl
|
||||
- ingenic,jz4725b-pinctrl
|
||||
- ingenic,jz4760-pinctrl
|
||||
- ingenic,jz4770-pinctrl
|
||||
- ingenic,jz4780-pinctrl
|
||||
- ingenic,x1000-pinctrl
|
||||
- ingenic,x1500-pinctrl
|
||||
- ingenic,x1830-pinctrl
|
||||
- items:
|
||||
- const: ingenic,jz4760b-pinctrl
|
||||
- const: ingenic,jz4760-pinctrl
|
||||
- items:
|
||||
- const: ingenic,x1000e-pinctrl
|
||||
- const: ingenic,x1000-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^gpio@[0-9]$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ingenic,jz4740-gpio
|
||||
- ingenic,jz4725b-gpio
|
||||
- ingenic,jz4760-gpio
|
||||
- ingenic,jz4770-gpio
|
||||
- ingenic,jz4780-gpio
|
||||
- ingenic,x1000-gpio
|
||||
- ingenic,x1500-gpio
|
||||
- ingenic,x1830-gpio
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: The GPIO bank number
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
description:
|
||||
Refer to ../interrupt-controller/interrupts.txt for more details.
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- gpio-controller
|
||||
- "#gpio-cells"
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- "#interrupt-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
additionalProperties:
|
||||
anyOf:
|
||||
- type: object
|
||||
allOf:
|
||||
- $ref: pincfg-node.yaml#
|
||||
- $ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
phandle: true
|
||||
function: true
|
||||
groups: true
|
||||
pins: true
|
||||
bias-disable: true
|
||||
bias-pull-up: true
|
||||
bias-pull-down: true
|
||||
output-low: true
|
||||
output-high: true
|
||||
additionalProperties: false
|
||||
|
||||
- type: object
|
||||
properties:
|
||||
phandle: true
|
||||
additionalProperties:
|
||||
type: object
|
||||
allOf:
|
||||
- $ref: pincfg-node.yaml#
|
||||
- $ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
phandle: true
|
||||
function: true
|
||||
groups: true
|
||||
pins: true
|
||||
bias-disable: true
|
||||
bias-pull-up: true
|
||||
bias-pull-down: true
|
||||
output-low: true
|
||||
output-high: true
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pin-controller@10010000 {
|
||||
compatible = "ingenic,jz4770-pinctrl";
|
||||
reg = <0x10010000 0x600>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpio@0 {
|
||||
compatible = "ingenic,jz4770-gpio";
|
||||
reg = <0>;
|
||||
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <17>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek MT6779 Pin Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Andy Teng <andy.teng@mediatek.com>
|
||||
|
||||
description: |+
|
||||
The pin controller node should be the child of a syscon node with the
|
||||
required property:
|
||||
- compatible: "syscon"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt6779-pinctrl
|
||||
|
||||
reg:
|
||||
minItems: 9
|
||||
maxItems: 9
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: "gpio"
|
||||
- const: "iocfg_rm"
|
||||
- const: "iocfg_br"
|
||||
- const: "iocfg_lm"
|
||||
- const: "iocfg_lb"
|
||||
- const: "iocfg_rt"
|
||||
- const: "iocfg_lt"
|
||||
- const: "iocfg_tl"
|
||||
- const: "eint"
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
description: |
|
||||
Number of cells in GPIO specifier. Since the generic GPIO
|
||||
binding is used, the amount of cells must be specified as 2. See the below
|
||||
mentioned gpio binding representation for description of particular cells.
|
||||
|
||||
gpio-ranges:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
description: |
|
||||
GPIO valid number range.
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description: |
|
||||
Specifies the summary IRQ.
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- gpio-controller
|
||||
- "#gpio-cells"
|
||||
- gpio-ranges
|
||||
- interrupt-controller
|
||||
- interrupts
|
||||
- "#interrupt-cells"
|
||||
|
||||
patternProperties:
|
||||
'-[0-9]*$':
|
||||
type: object
|
||||
patternProperties:
|
||||
'-pins*$':
|
||||
type: object
|
||||
description: |
|
||||
A pinctrl node should contain at least one subnodes representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and input schmitt.
|
||||
$ref: "/schemas/pinctrl/pincfg-node.yaml"
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
description:
|
||||
integer array, represents gpio pin number and mux setting.
|
||||
Supported pin number and mux varies for different SoCs, and are defined
|
||||
as macros in boot/dts/<soc>-pinfunc.h directly.
|
||||
|
||||
bias-disable: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
output-low: true
|
||||
|
||||
output-high: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
mediatek,pull-up-adv:
|
||||
description: |
|
||||
Pull up setings for 2 pull resistors, R0 and R1. User can
|
||||
configure those special pins. Valid arguments are described as below:
|
||||
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
|
||||
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
|
||||
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
|
||||
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
mediatek,pull-down-adv:
|
||||
description: |
|
||||
Pull down settings for 2 pull resistors, R0 and R1. User can
|
||||
configure those special pins. Valid arguments are described as below:
|
||||
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
|
||||
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
|
||||
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
|
||||
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
required:
|
||||
- pinmux
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/mt6779-pinfunc.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt6779-pinctrl";
|
||||
reg = <0 0x10005000 0 0x1000>,
|
||||
<0 0x11c20000 0 0x1000>,
|
||||
<0 0x11d10000 0 0x1000>,
|
||||
<0 0x11e20000 0 0x1000>,
|
||||
<0 0x11e70000 0 0x1000>,
|
||||
<0 0x11ea0000 0 0x1000>,
|
||||
<0 0x11f20000 0 0x1000>,
|
||||
<0 0x11f30000 0 0x1000>,
|
||||
<0 0x1000b000 0 0x1000>;
|
||||
reg-names = "gpio", "iocfg_rm",
|
||||
"iocfg_br", "iocfg_lm",
|
||||
"iocfg_lb", "iocfg_rt",
|
||||
"iocfg_lt", "iocfg_tl",
|
||||
"eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 210>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
mmc0_pins_default: mmc0-0 {
|
||||
cmd-dat-pins {
|
||||
pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
|
||||
<PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
|
||||
<PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
|
||||
<PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
|
||||
<PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
|
||||
<PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
|
||||
<PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
|
||||
<PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
|
||||
<PINMUX_GPIO167__FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
mediatek,pull-up-adv = <1>;
|
||||
};
|
||||
clk-pins {
|
||||
pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
|
||||
mediatek,pull-down-adv = <2>;
|
||||
};
|
||||
rst-pins {
|
||||
pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
|
||||
mediatek,pull-up-adv = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mmc0 {
|
||||
pinctrl-0 = <&mmc0_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
|
@ -1,116 +0,0 @@
|
|||
STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander bindings
|
||||
|
||||
ST Multi-Function eXpander (STMFX) offers up to 24 GPIOs expansion.
|
||||
Please refer to ../mfd/stmfx.txt for STMFX Core bindings.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "st,stmfx-0300-pinctrl".
|
||||
- #gpio-cells: should be <2>, the first cell is the GPIO number and the second
|
||||
cell is the gpio flags in accordance with <dt-bindings/gpio/gpio.h>.
|
||||
- gpio-controller: marks the device as a GPIO controller.
|
||||
- #interrupt-cells: should be <2>, the first cell is the GPIO number and the
|
||||
second cell is the interrupt flags in accordance with
|
||||
<dt-bindings/interrupt-controller/irq.h>.
|
||||
- interrupt-controller: marks the device as an interrupt controller.
|
||||
- gpio-ranges: specifies the mapping between gpio controller and pin
|
||||
controller pins. Check "Concerning gpio-ranges property" below.
|
||||
Please refer to ../gpio/gpio.txt.
|
||||
|
||||
Please refer to pinctrl-bindings.txt for pin configuration.
|
||||
|
||||
Required properties for pin configuration sub-nodes:
|
||||
- pins: list of pins to which the configuration applies.
|
||||
|
||||
Optional properties for pin configuration sub-nodes (pinconf-generic ones):
|
||||
- bias-disable: disable any bias on the pin.
|
||||
- bias-pull-up: the pin will be pulled up.
|
||||
- bias-pull-pin-default: use the pin-default pull state.
|
||||
- bias-pull-down: the pin will be pulled down.
|
||||
- drive-open-drain: the pin will be driven with open drain.
|
||||
- drive-push-pull: the pin will be driven actively high and low.
|
||||
- output-high: the pin will be configured as an output driving high level.
|
||||
- output-low: the pin will be configured as an output driving low level.
|
||||
|
||||
Note that STMFX pins[15:0] are called "gpio[15:0]", and STMFX pins[23:16] are
|
||||
called "agpio[7:0]". Example, to refer to pin 18 of STMFX, use "agpio2".
|
||||
|
||||
Concerning gpio-ranges property:
|
||||
- if all STMFX pins[24:0] are available (no other STMFX function in use), you
|
||||
should use gpio-ranges = <&stmfx_pinctrl 0 0 24>;
|
||||
- if agpio[3:0] are not available (STMFX Touchscreen function in use), you
|
||||
should use gpio-ranges = <&stmfx_pinctrl 0 0 16>, <&stmfx_pinctrl 20 20 4>;
|
||||
- if agpio[7:4] are not available (STMFX IDD function in use), you
|
||||
should use gpio-ranges = <&stmfx_pinctrl 0 0 20>;
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
stmfx: stmfx@42 {
|
||||
...
|
||||
|
||||
stmfx_pinctrl: stmfx-pin-controller {
|
||||
compatible = "st,stmfx-0300-pinctrl";
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
gpio-ranges = <&stmfx_pinctrl 0 0 24>;
|
||||
|
||||
joystick_pins: joystick {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example of STMFX GPIO consumers:
|
||||
|
||||
joystick {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&joystick_pins>;
|
||||
pinctrl-names = "default";
|
||||
button-0 {
|
||||
label = "JoySel";
|
||||
linux,code = <KEY_ENTER>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <0 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
button-1 {
|
||||
label = "JoyDown";
|
||||
linux,code = <KEY_DOWN>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
button-2 {
|
||||
label = "JoyLeft";
|
||||
linux,code = <KEY_LEFT>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <2 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
button-3 {
|
||||
label = "JoyRight";
|
||||
linux,code = <KEY_RIGHT>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
button-4 {
|
||||
label = "JoyUp";
|
||||
linux,code = <KEY_UP>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
orange {
|
||||
gpios = <&stmfx_pinctrl 17 1>;
|
||||
};
|
||||
|
||||
blue {
|
||||
gpios = <&stmfx_pinctrl 19 1>;
|
||||
};
|
||||
}
|
||||
|
|
@ -44,7 +44,8 @@ information about e.g. the mux function.
|
|||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength.
|
||||
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
|
||||
drive-strength.
|
||||
|
||||
Non-empty subnodes must specify the 'pins' property.
|
||||
Note that not all properties are valid for all pins.
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@ PMIC's from Qualcomm.
|
|||
"qcom,pmi8994-gpio"
|
||||
"qcom,pmi8998-gpio"
|
||||
"qcom,pms405-gpio"
|
||||
"qcom,pm660-gpio"
|
||||
"qcom,pm660l-gpio"
|
||||
"qcom,pm8150-gpio"
|
||||
"qcom,pm8150b-gpio"
|
||||
"qcom,pm6150-gpio"
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ Required Properties:
|
|||
- "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller.
|
||||
- "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller.
|
||||
- "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller.
|
||||
- "renesas,pfc-r8a774e1": for R8A774E1 (RZ/G2H) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
|
||||
|
|
|
|||
|
|
@ -1,87 +0,0 @@
|
|||
Renesas RZ/A2 combined Pin and GPIO controller
|
||||
|
||||
The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller.
|
||||
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
|
||||
Each port features up to 8 pins, each of them configurable for GPIO
|
||||
function (port mode) or in alternate function mode.
|
||||
Up to 8 different alternate function modes exist for each single pin.
|
||||
|
||||
Pin controller node
|
||||
-------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be:
|
||||
- "renesas,r7s9210-pinctrl": for RZ/A2M
|
||||
- reg
|
||||
Address base and length of the memory area where the pin controller
|
||||
hardware is mapped to.
|
||||
- gpio-controller
|
||||
This pin controller also controls pins as GPIO
|
||||
- #gpio-cells
|
||||
Must be 2
|
||||
- gpio-ranges
|
||||
Expresses the total number of GPIO ports/pins in this SoC
|
||||
|
||||
Example: Pin controller node for RZ/A2M SoC (r7s9210)
|
||||
|
||||
pinctrl: pin-controller@fcffe000 {
|
||||
compatible = "renesas,r7s9210-pinctrl";
|
||||
reg = <0xfcffe000 0x1000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl 0 0 176>;
|
||||
};
|
||||
|
||||
Sub-nodes
|
||||
---------
|
||||
|
||||
The child nodes of the pin controller designate pins to be used for
|
||||
specific peripheral functions or as GPIO.
|
||||
|
||||
- Pin multiplexing sub-nodes:
|
||||
A pin multiplexing sub-node describes how to configure a set of
|
||||
(or a single) pin in some desired alternate function mode.
|
||||
The values for the pinmux properties are a combination of port name, pin
|
||||
number and the desired function index. Use the RZA2_PINMUX macro located
|
||||
in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these.
|
||||
For assigning GPIO pins, use the macro RZA2_PIN also in r7s9210-pinctrl.h
|
||||
to express the desired port pin.
|
||||
|
||||
Required properties:
|
||||
- pinmux:
|
||||
integer array representing pin number and pin multiplexing configuration.
|
||||
When a pin has to be configured in alternate function mode, use this
|
||||
property to identify the pin by its global index, and provide its
|
||||
alternate function configuration number along with it.
|
||||
When multiple pins are required to be configured as part of the same
|
||||
alternate function they shall be specified as members of the same
|
||||
argument list of a single "pinmux" property.
|
||||
Helper macros to ease assembling the pin index from its position
|
||||
(port where it sits on and pin number) and alternate function identifier
|
||||
are provided by the pin controller header file at:
|
||||
<dt-bindings/pinctrl/r7s9210-pinctrl.h>
|
||||
Integers values in "pinmux" argument list are assembled as:
|
||||
((PORT * 8 + PIN) | MUX_FUNC << 16)
|
||||
|
||||
Example: Board specific pins configuration
|
||||
|
||||
&pinctrl {
|
||||
/* Serial Console */
|
||||
scif4_pins: serial4 {
|
||||
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
|
||||
<RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
|
||||
};
|
||||
};
|
||||
|
||||
Example: Assigning a GPIO:
|
||||
|
||||
leds {
|
||||
status = "okay";
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led0 {
|
||||
/* P6_0 */
|
||||
gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/A2 combined Pin and GPIO controller
|
||||
|
||||
maintainers:
|
||||
- Chris Brandt <chris.brandt@renesas.com>
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description:
|
||||
The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
|
||||
controller.
|
||||
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
|
||||
Each port features up to 8 pins, each of them configurable for GPIO function
|
||||
(port mode) or in alternate function mode.
|
||||
Up to 8 different alternate function modes exist for each single pin.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: "renesas,r7s9210-pinctrl" # RZ/A2M
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
const: 2
|
||||
description:
|
||||
The first cell contains the global GPIO port index, constructed using the
|
||||
RZA2_PIN() helper macro in r7s9210-pinctrl.h.
|
||||
E.g. "RZA2_PIN(PORT6, 0)" for P6_0.
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
"^.*$":
|
||||
if:
|
||||
type: object
|
||||
then:
|
||||
allOf:
|
||||
- $ref: pincfg-node.yaml#
|
||||
- $ref: pinmux-node.yaml#
|
||||
description:
|
||||
The child nodes of the pin controller designate pins to be used for
|
||||
specific peripheral functions or as GPIO.
|
||||
|
||||
A pin multiplexing sub-node describes how to configure a set of
|
||||
(or a single) pin in some desired alternate function mode.
|
||||
The values for the pinmux properties are a combination of port name,
|
||||
pin number and the desired function index. Use the RZA2_PINMUX macro
|
||||
located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily
|
||||
define these.
|
||||
For assigning GPIO pins, use the macro RZA2_PIN also in
|
||||
to express the desired port pin.
|
||||
|
||||
properties:
|
||||
phandle: true
|
||||
|
||||
pinmux:
|
||||
description:
|
||||
Values are constructed from GPIO port number, pin number, and
|
||||
alternate function configuration number using the RZA2_PINMUX()
|
||||
helper macro in r7s9210-pinctrl.h.
|
||||
|
||||
required:
|
||||
- pinmux
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
|
||||
pinctrl: pin-controller@fcffe000 {
|
||||
compatible = "renesas,r7s9210-pinctrl";
|
||||
reg = <0xfcffe000 0x1000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl 0 0 176>;
|
||||
|
||||
/* Serial Console */
|
||||
scif4_pins: serial4 {
|
||||
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
|
||||
<RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
|
||||
};
|
||||
};
|
||||
|
|
@ -76,8 +76,7 @@ patternProperties:
|
|||
|
||||
"^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$":
|
||||
description: List of regulators and its properties
|
||||
allOf:
|
||||
- $ref: regulator.yaml#
|
||||
$ref: regulator.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,44 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/remoteproc/qcom,pil-info.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm peripheral image loader relocation info binding
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description:
|
||||
The Qualcomm peripheral image loader relocation memory region, in IMEM, is
|
||||
used for communicating remoteproc relocation information to post mortem
|
||||
debugging tools.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pil-reloc-info
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
imem@146bf000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x146bf000 0x1000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0 0x146bf000 0x1000>;
|
||||
|
||||
pil-reloc@94c {
|
||||
compatible = "qcom,pil-reloc-info";
|
||||
reg = <0x94c 0xc8>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI K3 DSP devices
|
||||
|
||||
maintainers:
|
||||
- Suman Anna <s-anna@ti.com>
|
||||
|
||||
description: |
|
||||
The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
|
||||
that are used to offload some of the processor-intensive tasks or algorithms,
|
||||
for achieving various system level goals.
|
||||
|
||||
These processor sub-systems usually contain additional sub-modules like
|
||||
L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
|
||||
controller, a dedicated local power/sleep controller etc. The DSP processor
|
||||
cores in the K3 SoCs are usually either a TMS320C66x CorePac processor or a
|
||||
TMS320C71x CorePac processor.
|
||||
|
||||
Each DSP Core sub-system is represented as a single DT node. Each node has a
|
||||
number of required or optional properties that enable the OS running on the
|
||||
host processor (Arm CorePac) to perform the device management of the remote
|
||||
processor and to communicate with the remote processor.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,j721e-c66-dsp
|
||||
- ti,j721e-c71-dsp
|
||||
description:
|
||||
Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs
|
||||
Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs
|
||||
|
||||
resets:
|
||||
description: |
|
||||
Should contain the phandle to the reset controller node managing the
|
||||
local resets for this device, and a reset specifier.
|
||||
maxItems: 1
|
||||
|
||||
firmware-name:
|
||||
description: |
|
||||
Should contain the name of the default firmware image
|
||||
file located on the firmware search path
|
||||
|
||||
mboxes:
|
||||
description: |
|
||||
OMAP Mailbox specifier denoting the sub-mailbox, to be used for
|
||||
communication with the remote processor. This property should match
|
||||
with the sub-mailbox node used in the firmware image.
|
||||
maxItems: 1
|
||||
|
||||
memory-region:
|
||||
minItems: 2
|
||||
maxItems: 8
|
||||
description: |
|
||||
phandle to the reserved memory nodes to be associated with the remoteproc
|
||||
device. There should be at least two reserved memory nodes defined. The
|
||||
reserved memory nodes should be carveout nodes, and should be defined as
|
||||
per the bindings in
|
||||
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
|
||||
items:
|
||||
- description: region used for dynamic DMA allocations like vrings and
|
||||
vring buffers
|
||||
- description: region reserved for firmware image sections
|
||||
additionalItems: true
|
||||
|
||||
# Optional properties:
|
||||
# --------------------
|
||||
|
||||
sram:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
description: |
|
||||
phandles to one or more reserved on-chip SRAM regions. The regions
|
||||
should be defined as child nodes of the respective SRAM node, and
|
||||
should be defined as per the generic bindings in,
|
||||
Documentation/devicetree/bindings/sram/sram.yaml
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,j721e-c66-dsp
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: Address and Size of the L2 SRAM internal memory region
|
||||
- description: Address and Size of the L1 PRAM internal memory region
|
||||
- description: Address and Size of the L1 DRAM internal memory region
|
||||
reg-names:
|
||||
items:
|
||||
- const: l2sram
|
||||
- const: l1pram
|
||||
- const: l1dram
|
||||
else:
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,j721e-c71-dsp
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: Address and Size of the L2 SRAM internal memory region
|
||||
- description: Address and Size of the L1 DRAM internal memory region
|
||||
reg-names:
|
||||
items:
|
||||
- const: l2sram
|
||||
- const: l1dram
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- ti,sci
|
||||
- ti,sci-dev-id
|
||||
- ti,sci-proc-ids
|
||||
- resets
|
||||
- firmware-name
|
||||
- mboxes
|
||||
- memory-region
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
/ {
|
||||
model = "Texas Instruments K3 J721E SoC";
|
||||
compatible = "ti,j721e";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus@100000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
|
||||
<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
|
||||
<0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
|
||||
|
||||
/* J721E C66_0 DSP node */
|
||||
dsp@4d80800000 {
|
||||
compatible = "ti,j721e-c66-dsp";
|
||||
reg = <0x4d 0x80800000 0x00 0x00048000>,
|
||||
<0x4d 0x80e00000 0x00 0x00008000>,
|
||||
<0x4d 0x80f00000 0x00 0x00008000>;
|
||||
reg-names = "l2sram", "l1pram", "l1dram";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <142>;
|
||||
ti,sci-proc-ids = <0x03 0xFF>;
|
||||
resets = <&k3_reset 142 1>;
|
||||
firmware-name = "j7-c66_0-fw";
|
||||
memory-region = <&c66_0_dma_memory_region>,
|
||||
<&c66_0_memory_region>;
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
|
||||
};
|
||||
|
||||
/* J721E C71_0 DSP node */
|
||||
c71_0: dsp@64800000 {
|
||||
compatible = "ti,j721e-c71-dsp";
|
||||
reg = <0x00 0x64800000 0x00 0x00080000>,
|
||||
<0x00 0x64e00000 0x00 0x0000c000>;
|
||||
reg-names = "l2sram", "l1dram";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <15>;
|
||||
ti,sci-proc-ids = <0x30 0xFF>;
|
||||
resets = <&k3_reset 15 1>;
|
||||
firmware-name = "j7-c71_0-fw";
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -52,6 +52,8 @@ properties:
|
|||
- nxp,pcf2127
|
||||
# Real-time clock
|
||||
- nxp,pcf2129
|
||||
# Real-time clock
|
||||
- nxp,pca2129
|
||||
# Real-time Clock Module
|
||||
- pericom,pt7c4338
|
||||
# I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
|
||||
|
|
|
|||
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Reference in New Issue
Block a user