forked from luck/tmp_suning_uos_patched
Qualcomm ARM64 Updates for v4.5
* Add fixed rate oscillators to dts * Fixup PMIC alias and properties * Change 8916-MTP compatible to be compliant with new scheme * Fix 8x16 UART pinctrl configuration * Add SMEM, RPM/SMD, and PM8916 support on MSM8916 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWckTvAAoJEFKiBbHx2RXVAH0QAIOVo46P/LtOQk8J+A8lUyM3 eui/kuJG5H9iKf+r7maPCnWQbkdRfAevHFBixDfqq3WLK6muNAsWlAeTWasBG2AR mMqg/0pkVCJHHxJ9xeMqdo7RkAPDgmk/CiR+kD+SA19N+OegU+fExI7RyEd9LQ/B sQgbebZxB5VBQPIPlJorFP4UPG6T/sbV4FjsQ65GMGxZ321EV4OsApJHbEK9bzO7 8fFAU6OX9wRcqkQ9K5aLTo312ZzE1TvgyPLfSfZmAVAmgrWSC99nqKzd3u1qeCOC jAzcv9yGMx4bfCMZcTuHp2OIGHbxFE9S0vBHfZrlzYxn8gniKBepGIr8w09TZgEq TfDl2pzzfOsLF2sh1UAA3Is/i88zgf/EXt4q+1qgSZAGG66BvNUHDZP3uXVItRcY GvugxN/96v5eszrG/0d+0IYQzYvFqXAbFfuYi5ax4+B4eah5YNPjSufJnWbHKogt Eg3DVnvlilMBDpqc8zMCR5AnLsFFxGZEtsd8WTofE3Gd8wtkqCMS95Hh5PkNxkyC bp1WXKEarMPjJ0X3YtAhQo7M5eFMYsZPxblhCr1CPmuVFzbwlyMkpqdaX23H93Ni it+geo3aRKFdtxIX11bqCO6S6f2en7ZGg1bsychxqk+oN309EAqJkQAyNGYpo2h3 aWGLpsxVEC3/NHNh9aRg =mu4g -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64 Qualcomm ARM64 Updates for v4.5 * Add fixed rate oscillators to dts * Fixup PMIC alias and properties * Change 8916-MTP compatible to be compliant with new scheme * Fix 8x16 UART pinctrl configuration * Add SMEM, RPM/SMD, and PM8916 support on MSM8916 * tag 'qcom-arm64-for-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: arm64: dts: Add PM8916 support on MSM8916 arm64: dts: qcom: Add RPM/SMD support on MSM8916 arm64: dts: qcom: Add MSM8916 SMEM nodes arm64: dts: set the default i2c pin drive strength to 16mA arm64: dts: fix the i2c aliasing to match to schematics. arm64: dts: qcom: msm8916: Add fixed rate on-board oscillators arm64: dts: qcom: Alias pm8916 on msm8916 devices arm64: dts: qcom: Make msm8916-mtp compatible string compliant arm64: dts: qcom: 8x16: UART1 and UART2 use DMA for RX and TX arm64: dts: qcom: 8x16: UART1 add CTS_N, RTS_N pin configurations Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
1c5d795704
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@ -20,6 +20,10 @@ / {
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aliases {
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serial0 = &blsp1_uart2;
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serial1 = &blsp1_uart1;
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usid0 = &pm8916_0;
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i2c0 = &blsp_i2c2;
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i2c1 = &blsp_i2c6;
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i2c3 = &blsp_i2c4;
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};
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chosen {
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@ -17,6 +17,6 @@
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/ {
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model = "Qualcomm Technologies, Inc. MSM 8916 MTP";
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compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360",
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compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1",
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"qcom,msm8916", "qcom,mtp";
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};
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@ -17,6 +17,7 @@
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/ {
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aliases {
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serial0 = &blsp1_uart2;
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usid0 = &pm8916_0;
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};
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chosen {
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@ -16,10 +16,13 @@ &msmgpio {
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blsp1_uart1_default: blsp1_uart1_default {
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pinmux {
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function = "blsp_uart1";
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pins = "gpio0", "gpio1";
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// TX, RX, CTS_N, RTS_N
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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};
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pinconf {
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pins = "gpio0", "gpio1";
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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drive-strength = <16>;
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bias-disable;
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};
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@ -28,10 +31,12 @@ pinconf {
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blsp1_uart1_sleep: blsp1_uart1_sleep {
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pinmux {
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function = "gpio";
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pins = "gpio0", "gpio1";
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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};
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pinconf {
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pins = "gpio0", "gpio1";
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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drive-strength = <2>;
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bias-pull-down;
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};
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@ -272,7 +277,7 @@ pinmux {
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};
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pinconf {
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pins = "gpio6", "gpio7";
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drive-strength = <2>;
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drive-strength = <16>;
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bias-disable = <0>;
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};
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};
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@ -296,7 +301,7 @@ pinmux {
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};
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pinconf {
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pins = "gpio14", "gpio15";
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drive-strength = <2>;
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drive-strength = <16>;
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bias-disable = <0>;
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};
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};
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@ -320,7 +325,7 @@ pinmux {
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};
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pinconf {
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pins = "gpio22", "gpio23";
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drive-strength = <2>;
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drive-strength = <16>;
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bias-disable = <0>;
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};
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};
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@ -37,6 +37,22 @@ memory {
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reg = <0 0 0 0>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reserve_aligned@86000000 {
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reg = <0x0 0x86000000 0x0 0x0300000>;
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no-map;
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};
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smem_mem: smem_region@86300000 {
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reg = <0x0 0x86300000 0x0 0x0100000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -74,6 +90,29 @@ timer {
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -103,21 +142,46 @@ gcc: qcom,gcc@1800000 {
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reg = <0x1800000 0x80000>;
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};
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tcsr_mutex_regs: syscon@1905000 {
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compatible = "syscon";
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reg = <0x1905000 0x20000>;
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_regs 0 0x1000>;
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#hwlock-cells = <1>;
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};
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rpm_msg_ram: memory@60000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0x60000 0x8000>;
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};
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 1>, <&blsp_dma 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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apcs: syscon@b011000 {
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compatible = "syscon";
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reg = <0x0b011000 0x1000>;
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};
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blsp1_uart2: serial@78b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b0000 0x200>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 3>, <&blsp_dma 2>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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@ -438,6 +502,49 @@ rng@22000 {
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clock-names = "core";
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};
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};
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smd {
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compatible = "qcom,smd";
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rpm {
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interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 8 0>;
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qcom,smd-edge = <15>;
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rpm_requests {
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compatible = "qcom,rpm-msm8916";
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qcom,smd-channels = "rpm_requests";
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pm8916-regulators {
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compatible = "qcom,rpm-pm8916-regulators";
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pm8916_s1: s1 {};
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pm8916_s2: s2 {};
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pm8916_s3: s3 {};
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pm8916_s4: s4 {};
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pm8916_l1: l1 {};
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pm8916_l2: l2 {};
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pm8916_l3: l3 {};
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pm8916_l4: l4 {};
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pm8916_l5: l5 {};
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pm8916_l6: l6 {};
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pm8916_l7: l7 {};
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pm8916_l8: l8 {};
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pm8916_l9: l9 {};
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pm8916_l10: l10 {};
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pm8916_l11: l11 {};
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pm8916_l12: l12 {};
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pm8916_l13: l13 {};
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pm8916_l14: l14 {};
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pm8916_l15: l15 {};
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pm8916_l16: l16 {};
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pm8916_l17: l17 {};
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pm8916_l18: l18 {};
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};
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};
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};
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};
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};
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#include "msm8916-pins.dtsi"
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@ -4,8 +4,8 @@
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&spmi_bus {
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usid0: pm8916@0 {
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compatible = "qcom,spmi-pmic";
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pm8916_0: pm8916@0 {
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compatible = "qcom,pm8916", "qcom,spmi-pmic";
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reg = <0x0 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -90,7 +90,7 @@ ref_vdd {
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};
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};
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usid1: pm8916@1 {
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pm8916_1: pm8916@1 {
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compatible = "qcom,spmi-pmic";
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reg = <0x1 SPMI_USID>;
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#address-cells = <1>;
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