forked from luck/tmp_suning_uos_patched
Qualcomm ARM64 Updates for v5.5
* Add thermal IRQ support on MSM8916, SDM845, MSM8996, and QCS404 * Fix thermal HW ids for cpus on MSM8916 * Add blsp1 UART3 and blsp1 BAM on MSM8998 * Add volume buttons and WCNSS for Wifi and BT on MSM8916 LongCheer-l8150 * Fixup load on l21 for SD on apq8096-db820c * Enable LVS1/2, APSS watchdog, and select UFS reset gpio for SDM845 * Disable coresight by default on MSM8998 * Enable bluetooth and remove retention idle state on MSM8998-clamshell * Enable adsp, cdsp, and mpss on C630 * Enable bluetooth on MSM8998-mtp * Delete zap shader on SDM845-cheza * Add tactile buttons and hall sensor on MSM8916-Samsung-A2015 * Add Interconnect nodes, watchdog, and sleep clk on QCS404 * Override Iris compatible on MSM8916-Samsung-A5U * Enable WCNSS Wifi and bluetooth on MSM8916-Samsung-A2015 * Fixup cooling states for the aoss warming devices -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJdwQS2AAoJEFKiBbHx2RXVsTIQALz7tNsuZ+CGpzUKxUfQmd0I TDk5xMeoeOLc+zT9GkAo0pf4De91D9qHLv9LjYZT7ukL1RjF/LrtC9Mv9qj7dp+r jrOd1MdXJqC+6w3uW4c7mP0Ov+obdkU8seN9lTN7eBbskDgEurjHncU49XUuRjCF 1YECywNkqTieG71fcil3Wi65A+x6fttfrmlpFdIuDrlfh2IAQeHrueAG4cBe0E3l ajfU6yON26DeEVY09SnJwlc7RWvkUF1gjZDKEe1ELOrydsTvJHhZfs44ilnoTkJL wkY5unNX8KgjdZBpNAD10otVZp7lOmsCKOaVzB9e7n9/iG1vd08QWFeTK1xxGSoT Mo03WxxFxuSweOrB/oe4e2R16RbzccprniVNM6SuC5Md+sYvZKxzWrnvl5jdK+j2 0351A4UgMvY5UCT3DvZxosbp80T+DaU9mubuqG2lrytWMiTAupsCQabzxTGYl78B B6lr4QQQ1lWJTOuw2qhzKA48mUzcrgbweJSXXWPeipRmUbL2bF8KpDgb2hxjZvKN TpjZ7qVGhNrKdEixp2krOwX074bckuBonyxDyuDvNvDnGPG4/cswVF6Ik3v5PiAO tswk1hUQ6VDEhfXD0us157DtmeqC+LwG5XtU0LcWEjgunqJxBbo9FqmYgxVnliSL fPP9v91WyTfD0Neuyy7M =jkQc -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt Qualcomm ARM64 Updates for v5.5 * Add thermal IRQ support on MSM8916, SDM845, MSM8996, and QCS404 * Fix thermal HW ids for cpus on MSM8916 * Add blsp1 UART3 and blsp1 BAM on MSM8998 * Add volume buttons and WCNSS for Wifi and BT on MSM8916 LongCheer-l8150 * Fixup load on l21 for SD on apq8096-db820c * Enable LVS1/2, APSS watchdog, and select UFS reset gpio for SDM845 * Disable coresight by default on MSM8998 * Enable bluetooth and remove retention idle state on MSM8998-clamshell * Enable adsp, cdsp, and mpss on C630 * Enable bluetooth on MSM8998-mtp * Delete zap shader on SDM845-cheza * Add tactile buttons and hall sensor on MSM8916-Samsung-A2015 * Add Interconnect nodes, watchdog, and sleep clk on QCS404 * Override Iris compatible on MSM8916-Samsung-A5U * Enable WCNSS Wifi and bluetooth on MSM8916-Samsung-A2015 * Fixup cooling states for the aoss warming devices * tag 'qcom-arm64-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (26 commits) arm64: dts: qcom: db845c: Enable LVS 1 and 2 arm64: dts: qcom: msm8998: Disable coresight by default arm64: dts: qcom: msm8998-clamshell: Remove retention idle state arm64: dts: qcom: sdm845-cheza: delete zap-shader arm64: dts: msm8916: thermal: Fixup HW ids for cpu sensors arm64: dts: sdm845: thermal: Add interrupt support arm64: dts: msm8996: thermal: Add interrupt support arm64: dts: msm8998: thermal: Add interrupt support arm64: dts: qcs404: thermal: Add interrupt support arm64: dts: qcom: sdm845: Add APSS watchdog node arm64: dts: qcom: c630: Enable adsp, cdsp and mpss arm64: dts: qcom: msm8998-clamshell: Enable bluetooth arm64: dts: qcom: msm8998-mtp: Enable bluetooth arm64: dts: qcom: msm8998: Add blsp1_uart3 arm64: dts: qcom: msm8998: Add blsp1 BAM arm64: dts: msm8916-longcheer-l8150: Add Volume buttons arm64: dts: msm8916-longcheer-l8150: Enable WCNSS for WiFi and BT soc: qcom: Invert the cooling states for the aoss warming devices arm64: dts: apq8096-db820c: Increase load on l21 for SDCARD arm64: dts: msm8916-samsung-a2015: add tactile buttons and hall sensor ... Link: https://lore.kernel.org/r/1573068840-13098-2-git-send-email-agross@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
1d16a9172c
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@ -623,6 +623,8 @@ l20 {
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l21 {
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regulator-min-microvolt = <2950000>;
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regulator-max-microvolt = <2950000>;
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regulator-allow-set-load;
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regulator-system-load = <200000>;
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};
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l22 {
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regulator-min-microvolt = <3300000>;
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@ -5,6 +5,7 @@
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#include "msm8916.dtsi"
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#include "pm8916.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "Longcheer L8150";
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@ -18,6 +19,16 @@ chosen {
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stdout-path = "serial0";
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};
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reserved-memory {
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// wcnss.mdt is not relocatable, so it must be loaded at 0x8b600000
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/delete-node/ wcnss@89300000;
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wcnss_mem: wcnss@8b600000 {
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reg = <0x0 0x8b600000 0x0 0x600000>;
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no-map;
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};
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};
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soc {
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sdhci@7824000 {
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status = "okay";
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@ -68,6 +79,10 @@ phy {
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};
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};
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wcnss@a21b000 {
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status = "okay";
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};
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/*
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* Attempting to enable these devices causes a "synchronous
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* external abort". Suspected cause is that the debug power
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@ -99,9 +114,36 @@ usb_vbus: usb-vbus {
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pinctrl-names = "default";
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pinctrl-0 = <&usb_vbus_default>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&gpio_keys_default>;
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label = "GPIO Buttons";
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volume-up {
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label = "Volume Up";
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gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_VOLUMEUP>;
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};
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};
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};
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&msmgpio {
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gpio_keys_default: gpio_keys_default {
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pinmux {
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function = "gpio";
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pins = "gpio107";
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};
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pinconf {
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pins = "gpio107";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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usb_vbus_default: usb-vbus-default {
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pinmux {
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function = "gpio";
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@ -114,6 +156,19 @@ pinconf {
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};
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};
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&spmi_bus {
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pm8916@0 {
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pon@800 {
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volume-down {
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compatible = "qcom,pm8941-resin";
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interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
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bias-pull-up;
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linux,code = <KEY_VOLUMEDOWN>;
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};
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};
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};
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};
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&smd_rpm_regulators {
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vdd_l1_l2_l3-supply = <&pm8916_s3>;
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vdd_l4_l5_l6-supply = <&pm8916_s4>;
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@ -3,6 +3,7 @@
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#include "msm8916.dtsi"
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#include "pm8916.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@ -63,6 +64,10 @@ phy {
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};
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};
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wcnss@a21b000 {
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status = "okay";
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};
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/*
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* Attempting to enable these devices causes a "synchronous
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* external abort". Suspected cause is that the debug power
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@ -87,6 +92,44 @@ phy {
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etm@85f000 { status = "disabled"; };
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&gpio_keys_default>;
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label = "GPIO Buttons";
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volume-up {
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label = "Volume Up";
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gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_VOLUMEUP>;
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};
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home {
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label = "Home";
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gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_HOMEPAGE>;
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};
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};
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gpio-hall-sensor {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&gpio_hall_sensor_default>;
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label = "GPIO Hall Effect Sensor";
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hall-sensor {
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label = "Hall Effect Sensor";
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gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>;
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linux,input-type = <EV_SW>;
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linux,code = <SW_LID>;
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linux,can-disable;
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};
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};
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i2c-muic {
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compatible = "i2c-gpio";
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sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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@ -109,6 +152,30 @@ muic: sm5502@25 {
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};
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&msmgpio {
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gpio_keys_default: gpio_keys_default {
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pinmux {
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function = "gpio";
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pins = "gpio107", "gpio109";
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};
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pinconf {
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pins = "gpio107", "gpio109";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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gpio_hall_sensor_default: gpio_hall_sensor_default {
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pinmux {
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function = "gpio";
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pins = "gpio52";
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};
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pinconf {
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pins = "gpio52";
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drive-strength = <2>;
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bias-disable;
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};
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};
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muic_int_default: muic_int_default {
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pinmux {
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function = "gpio";
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@ -234,3 +301,16 @@ l18 {
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regulator-max-microvolt = <2700000>;
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};
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};
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&spmi_bus {
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pm8916@0 {
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pon@800 {
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volume-down {
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compatible = "qcom,pm8941-resin";
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interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
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bias-pull-up;
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linux,code = <KEY_VOLUMEDOWN>;
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};
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};
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};
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};
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@ -8,3 +8,9 @@ / {
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model = "Samsung Galaxy A5U (EUR)";
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compatible = "samsung,a5u-eur", "qcom,msm8916";
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};
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&pronto {
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iris {
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compatible = "qcom,wcn3680";
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};
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};
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@ -179,7 +179,7 @@ cpu0_1-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 4>;
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thermal-sensors = <&tsens 5>;
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trips {
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cpu0_1_alert0: trip-point@0 {
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@ -209,7 +209,7 @@ cpu2_3-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 3>;
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thermal-sensors = <&tsens 4>;
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trips {
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cpu2_3_alert0: trip-point@0 {
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@ -591,6 +591,8 @@ tsens0: thermal-sensor@4a9000 {
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reg = <0x4a9000 0x1000>, /* TM */
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<0x4a8000 0x1000>; /* SROT */
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#qcom,sensors = <13>;
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interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uplow";
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#thermal-sensor-cells = <1>;
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};
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@ -599,6 +601,8 @@ tsens1: thermal-sensor@4ad000 {
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reg = <0x4ad000 0x1000>, /* TM */
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<0x4ac000 0x1000>; /* SROT */
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#qcom,sensors = <8>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uplow";
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#thermal-sensor-cells = <1>;
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};
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@ -23,6 +23,57 @@ vph_pwr: vph-pwr-regulator {
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};
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};
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&blsp1_uart3 {
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status = "okay";
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bluetooth {
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compatible = "qcom,wcn3990-bt";
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vddio-supply = <&vreg_s4a_1p8>;
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vddxo-supply = <&vreg_l7a_1p8>;
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vddrf-supply = <&vreg_l17a_1p3>;
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vddch0-supply = <&vreg_l25a_3p3>;
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max-speed = <3200000>;
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};
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};
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/*
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* The laptop FW does not appear to support the retention state as it is
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* not advertised as enabled in ACPI, and enabling it in DT can cause boot
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* hangs.
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*/
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&CPU0 {
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cpu-idle-states = <&LITTLE_CPU_SLEEP_1>;
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};
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&CPU1 {
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cpu-idle-states = <&LITTLE_CPU_SLEEP_1>;
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};
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&CPU2 {
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cpu-idle-states = <&LITTLE_CPU_SLEEP_1>;
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};
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&CPU3 {
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cpu-idle-states = <&LITTLE_CPU_SLEEP_1>;
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};
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&CPU4 {
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cpu-idle-states = <&BIG_CPU_SLEEP_1>;
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};
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&CPU5 {
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cpu-idle-states = <&BIG_CPU_SLEEP_1>;
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};
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&CPU6 {
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cpu-idle-states = <&BIG_CPU_SLEEP_1>;
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};
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&CPU7 {
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cpu-idle-states = <&BIG_CPU_SLEEP_1>;
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};
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&qusb2phy {
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status = "okay";
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@ -104,6 +155,7 @@ vreg_l6a_1p8: l6 {
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vreg_l7a_1p8: l7 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-allow-set-load;
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};
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vreg_l8a_1p2: l8 {
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regulator-min-microvolt = <1200000>;
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@ -144,6 +196,7 @@ vreg_l16a_2p7: l16 {
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vreg_l17a_1p3: l17 {
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regulator-min-microvolt = <1304000>;
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regulator-max-microvolt = <1304000>;
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regulator-allow-set-load;
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};
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vreg_l18a_2p7: l18 {
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regulator-min-microvolt = <2704000>;
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@ -179,6 +232,7 @@ vreg_l24a_3p075: l24 {
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vreg_l25a_3p3: l25 {
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regulator-min-microvolt = <3104000>;
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regulator-max-microvolt = <3312000>;
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regulator-allow-set-load;
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};
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vreg_l26a_1p2: l26 {
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regulator-min-microvolt = <1200000>;
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|
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@ -23,10 +23,84 @@ vph_pwr: vph-pwr-regulator {
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};
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||||
};
|
||||
|
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&blsp1_uart3 {
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status = "okay";
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|
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bluetooth {
|
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compatible = "qcom,wcn3990-bt";
|
||||
|
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vddio-supply = <&vreg_s4a_1p8>;
|
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vddxo-supply = <&vreg_l7a_1p8>;
|
||||
vddrf-supply = <&vreg_l17a_1p3>;
|
||||
vddch0-supply = <&vreg_l25a_3p3>;
|
||||
max-speed = <3200000>;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp2_uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etf {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etm4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etm5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etm6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etm7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etm8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etr {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&funnel1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&funnel2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&funnel3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&funnel4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&funnel5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8005_lsid1 {
|
||||
pm8005-regulators {
|
||||
compatible = "qcom,pm8005-regulators";
|
||||
|
|
@ -51,6 +125,10 @@ &qusb2phy {
|
|||
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
|
||||
};
|
||||
|
||||
&replicator1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rpm_requests {
|
||||
pm8998-regulators {
|
||||
compatible = "qcom,rpm-pm8998-regulators";
|
||||
|
|
@ -249,6 +327,10 @@ &sdhc2 {
|
|||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
|
||||
};
|
||||
|
||||
&stm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufshc {
|
||||
vcc-supply = <&vreg_l20a_2p95>;
|
||||
vccq-supply = <&vreg_l26a_1p2>;
|
||||
|
|
|
|||
|
|
@ -75,4 +75,17 @@ config {
|
|||
drive-strength = <2>; /* 2 mA */
|
||||
};
|
||||
};
|
||||
|
||||
blsp1_uart3_on: blsp1_uart3_on {
|
||||
mux {
|
||||
pins = "gpio45", "gpio46", "gpio47", "gpio48";
|
||||
function = "blsp_uart3_a";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio45", "gpio46", "gpio47", "gpio48";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -816,8 +816,9 @@ tsens0: thermal@10ab000 {
|
|||
compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
|
||||
reg = <0x010ab000 0x1000>, /* TM */
|
||||
<0x010aa000 0x1000>; /* SROT */
|
||||
|
||||
#qcom,sensors = <14>;
|
||||
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
|
|
@ -825,8 +826,9 @@ tsens1: thermal@10ae000 {
|
|||
compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
|
||||
reg = <0x010ae000 0x1000>, /* TM */
|
||||
<0x010ad000 0x1000>; /* SROT */
|
||||
|
||||
#qcom,sensors = <8>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
|
|
@ -998,11 +1000,12 @@ tlmm: pinctrl@3400000 {
|
|||
#interrupt-cells = <0x2>;
|
||||
};
|
||||
|
||||
stm@6002000 {
|
||||
stm: stm@6002000 {
|
||||
compatible = "arm,coresight-stm", "arm,primecell";
|
||||
reg = <0x06002000 0x1000>,
|
||||
<0x16280000 0x180000>;
|
||||
reg-names = "stm-base", "stm-data-base";
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1016,9 +1019,10 @@ stm_out: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
funnel@6041000 {
|
||||
funnel1: funnel@6041000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0x06041000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1045,9 +1049,10 @@ funnel0_in7: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
funnel@6042000 {
|
||||
funnel2: funnel@6042000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0x06042000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1075,9 +1080,10 @@ funnel1_in6: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
funnel@6045000 {
|
||||
funnel3: funnel@6045000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0x06045000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1113,9 +1119,10 @@ merge_funnel_in1: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
replicator@6046000 {
|
||||
replicator1: replicator@6046000 {
|
||||
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
||||
reg = <0x06046000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1137,9 +1144,10 @@ replicator_in: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
etf@6047000 {
|
||||
etf: etf@6047000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0x06047000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1163,9 +1171,10 @@ etf_in: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
etr@6048000 {
|
||||
etr: etr@6048000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0x06048000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1181,9 +1190,10 @@ etr_in: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
etm@7840000 {
|
||||
etm1: etm@7840000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0x07840000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1200,9 +1210,10 @@ etm0_out: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
etm@7940000 {
|
||||
etm2: etm@7940000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0x07940000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1219,9 +1230,10 @@ etm1_out: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
etm@7a40000 {
|
||||
etm3: etm@7a40000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0x07a40000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1238,9 +1250,10 @@ etm2_out: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
etm@7b40000 {
|
||||
etm4: etm@7b40000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0x07b40000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1257,9 +1270,10 @@ etm3_out: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
funnel@7b60000 { /* APSS Funnel */
|
||||
funnel4: funnel@7b60000 { /* APSS Funnel */
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0x07b60000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1343,9 +1357,10 @@ apss_funnel_in7: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
funnel@7b70000 {
|
||||
funnel5: funnel@7b70000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0x07b70000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1369,9 +1384,10 @@ apss_merge_funnel_in: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
etm@7c40000 {
|
||||
etm5: etm@7c40000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0x07c40000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1385,9 +1401,10 @@ etm4_out: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
etm@7d40000 {
|
||||
etm6: etm@7d40000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0x07d40000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1401,9 +1418,10 @@ etm5_out: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
etm@7e40000 {
|
||||
etm7: etm@7e40000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0x07e40000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1417,9 +1435,10 @@ etm6_out: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
etm@7f40000 {
|
||||
etm8: etm@7f40000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0x07f40000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
|
@ -1556,6 +1575,33 @@ sdhc2: sdhci@c0a4900 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_dma: dma@c144000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x0c144000 0x25000>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
qcom,controlled-remotely;
|
||||
num-channels = <18>;
|
||||
qcom,num-ees = <4>;
|
||||
};
|
||||
|
||||
blsp1_uart3: serial@c171000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x0c171000 0x1000>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_uart3_on>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_i2c1: i2c@c175000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x0c175000 0x600>;
|
||||
|
|
|
|||
|
|
@ -22,6 +22,12 @@ xo_board: xo-board {
|
|||
#clock-cells = <0>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
sleep_clk: sleep-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -283,6 +289,15 @@ rng: rng@e3000 {
|
|||
clock-names = "core";
|
||||
};
|
||||
|
||||
bimc: interconnect@400000 {
|
||||
reg = <0x00400000 0x80000>;
|
||||
compatible = "qcom,qcs404-bimc";
|
||||
#interconnect-cells = <1>;
|
||||
clock-names = "bus", "bus_a";
|
||||
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
|
||||
<&rpmcc RPM_SMD_BIMC_A_CLK>;
|
||||
};
|
||||
|
||||
tsens: thermal-sensor@4a9000 {
|
||||
compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
|
||||
reg = <0x004a9000 0x1000>, /* TM */
|
||||
|
|
@ -290,9 +305,29 @@ tsens: thermal-sensor@4a9000 {
|
|||
nvmem-cells = <&tsens_caldata>;
|
||||
nvmem-cell-names = "calib";
|
||||
#qcom,sensors = <10>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
pcnoc: interconnect@500000 {
|
||||
reg = <0x00500000 0x15080>;
|
||||
compatible = "qcom,qcs404-pcnoc";
|
||||
#interconnect-cells = <1>;
|
||||
clock-names = "bus", "bus_a";
|
||||
clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
|
||||
<&rpmcc RPM_SMD_PNOC_A_CLK>;
|
||||
};
|
||||
|
||||
snoc: interconnect@580000 {
|
||||
reg = <0x00580000 0x23080>;
|
||||
compatible = "qcom,qcs404-snoc";
|
||||
#interconnect-cells = <1>;
|
||||
clock-names = "bus", "bus_a";
|
||||
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
|
||||
<&rpmcc RPM_SMD_SNOC_A_CLK>;
|
||||
};
|
||||
|
||||
remoteproc_cdsp: remoteproc@b00000 {
|
||||
compatible = "qcom,qcs404-cdsp-pas";
|
||||
reg = <0x00b00000 0x4040>;
|
||||
|
|
@ -869,6 +904,12 @@ apcs_glb: mailbox@b011000 {
|
|||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
compatible = "qcom,kpss-wdt";
|
||||
reg = <0x0b017000 0x1000>;
|
||||
clocks = <&sleep_clk>;
|
||||
};
|
||||
|
||||
timer@b120000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -165,6 +165,8 @@ panel_in_edp: endpoint {
|
|||
/delete-node/ &venus_mem;
|
||||
/delete-node/ &cdsp_mem;
|
||||
/delete-node/ &cdsp_pas;
|
||||
/delete-node/ &zap_shader;
|
||||
/delete-node/ &gpu_mem;
|
||||
|
||||
/* Increase the size from 120 MB to 128 MB */
|
||||
&mpss_region {
|
||||
|
|
@ -701,9 +703,8 @@ &uart9 {
|
|||
|
||||
&ufs_mem_hc {
|
||||
status = "okay";
|
||||
pinctrl-names = "init", "default";
|
||||
pinctrl-0 = <&ufs_dev_reset_assert>;
|
||||
pinctrl-1 = <&ufs_dev_reset_deassert>;
|
||||
|
||||
reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vcc-supply = <&src_pp2950_l20a>;
|
||||
vcc-max-microamp = <600000>;
|
||||
|
|
@ -1258,52 +1259,6 @@ pinconf {
|
|||
};
|
||||
};
|
||||
|
||||
ufs_dev_reset_assert: ufs_dev_reset_assert {
|
||||
config {
|
||||
pins = "ufs_reset";
|
||||
bias-pull-down; /* default: pull down */
|
||||
/*
|
||||
* UFS_RESET driver strengths are having
|
||||
* different values/steps compared to typical
|
||||
* GPIO drive strengths.
|
||||
*
|
||||
* Following table clarifies:
|
||||
*
|
||||
* HDRV value | UFS_RESET | Typical GPIO
|
||||
* (dec) | (mA) | (mA)
|
||||
* 0 | 0.8 | 2
|
||||
* 1 | 1.55 | 4
|
||||
* 2 | 2.35 | 6
|
||||
* 3 | 3.1 | 8
|
||||
* 4 | 3.9 | 10
|
||||
* 5 | 4.65 | 12
|
||||
* 6 | 5.4 | 14
|
||||
* 7 | 6.15 | 16
|
||||
*
|
||||
* POR value for UFS_RESET HDRV is 3 which means
|
||||
* 3.1mA and we want to use that. Hence just
|
||||
* specify 8mA to "drive-strength" binding and
|
||||
* that should result into writing 3 to HDRV
|
||||
* field.
|
||||
*/
|
||||
drive-strength = <8>; /* default: 3.1 mA */
|
||||
output-low; /* active low reset */
|
||||
};
|
||||
};
|
||||
|
||||
ufs_dev_reset_deassert: ufs_dev_reset_deassert {
|
||||
config {
|
||||
pins = "ufs_reset";
|
||||
bias-pull-down; /* default: pull down */
|
||||
/*
|
||||
* default: 3.1 mA
|
||||
* check comments under ufs_dev_reset_assert
|
||||
*/
|
||||
drive-strength = <8>;
|
||||
output-high; /* active low reset */
|
||||
};
|
||||
};
|
||||
|
||||
ap_suspend_l_assert: ap_suspend_l_assert {
|
||||
config {
|
||||
pins = "gpio126";
|
||||
|
|
|
|||
|
|
@ -312,6 +312,18 @@ vreg_l26a_1p2: ldo26 {
|
|||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_lvs1a_1p8: lvs1 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vreg_lvs2a_1p8: lvs2 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
pmi8998-rpmh-regulators {
|
||||
|
|
|
|||
|
|
@ -2824,7 +2824,7 @@ gpu@5000000 {
|
|||
|
||||
qcom,gmu = <&gmu>;
|
||||
|
||||
zap-shader {
|
||||
zap_shader: zap-shader {
|
||||
memory-region = <&gpu_mem>;
|
||||
};
|
||||
|
||||
|
|
@ -2950,6 +2950,8 @@ tsens0: thermal-sensor@c263000 {
|
|||
reg = <0 0x0c263000 0 0x1ff>, /* TM */
|
||||
<0 0x0c222000 0 0x1ff>; /* SROT */
|
||||
#qcom,sensors = <13>;
|
||||
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
|
|
@ -2958,6 +2960,8 @@ tsens1: thermal-sensor@c265000 {
|
|||
reg = <0 0x0c265000 0 0x1ff>, /* TM */
|
||||
<0 0x0c223000 0 0x1ff>; /* SROT */
|
||||
#qcom,sensors = <8>;
|
||||
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
|
|
@ -3084,6 +3088,12 @@ lpasscc: clock-controller@17014000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog@17980000 {
|
||||
compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
|
||||
reg = <0 0x17980000 0 0x1000>;
|
||||
clocks = <&sleep_clk>;
|
||||
};
|
||||
|
||||
apss_shared: mailbox@17990000 {
|
||||
compatible = "qcom,sdm845-apss-shared";
|
||||
reg = <0 0x17990000 0 0x1000>;
|
||||
|
|
|
|||
|
|
@ -20,6 +20,11 @@ aliases {
|
|||
};
|
||||
};
|
||||
|
||||
&adsp_pas {
|
||||
firmware-name = "qcom/LENOVO/81JL/qcadsp850.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
pm8998-rpmh-regulators {
|
||||
compatible = "qcom,pm8998-rpmh-regulators";
|
||||
|
|
@ -229,6 +234,11 @@ &apps_smmu {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdsp_pas {
|
||||
firmware-name = "qcom/LENOVO/81JL/qccdsp850.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
|
|
@ -296,6 +306,10 @@ hid@5c {
|
|||
};
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
firmware-name = "qcom/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/LENOVO/81JL/qcdsp2850.mbn";
|
||||
};
|
||||
|
||||
&qup_i2c12_default {
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
|
||||
#define QMP_NUM_COOLING_RESOURCES 2
|
||||
|
||||
static bool qmp_cdev_init_state = 1;
|
||||
static bool qmp_cdev_max_state = 1;
|
||||
|
||||
struct qmp_cooling_device {
|
||||
struct thermal_cooling_device *cdev;
|
||||
|
|
@ -402,7 +402,7 @@ static void qmp_pd_remove(struct qmp *qmp)
|
|||
static int qmp_cdev_get_max_state(struct thermal_cooling_device *cdev,
|
||||
unsigned long *state)
|
||||
{
|
||||
*state = qmp_cdev_init_state;
|
||||
*state = qmp_cdev_max_state;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -432,7 +432,7 @@ static int qmp_cdev_set_cur_state(struct thermal_cooling_device *cdev,
|
|||
snprintf(buf, sizeof(buf),
|
||||
"{class: volt_flr, event:zero_temp, res:%s, value:%s}",
|
||||
qmp_cdev->name,
|
||||
cdev_state ? "off" : "on");
|
||||
cdev_state ? "on" : "off");
|
||||
|
||||
ret = qmp_send(qmp_cdev->qmp, buf, sizeof(buf));
|
||||
|
||||
|
|
@ -455,7 +455,7 @@ static int qmp_cooling_device_add(struct qmp *qmp,
|
|||
char *cdev_name = (char *)node->name;
|
||||
|
||||
qmp_cdev->qmp = qmp;
|
||||
qmp_cdev->state = qmp_cdev_init_state;
|
||||
qmp_cdev->state = !qmp_cdev_max_state;
|
||||
qmp_cdev->name = cdev_name;
|
||||
qmp_cdev->cdev = devm_thermal_of_cooling_device_register
|
||||
(qmp->dev, node,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user