forked from luck/tmp_suning_uos_patched
MIPS: c-r4k: Extend way_string array
The L2 cache in the I6400 core has 16 ways, so extend the way_string array to take such caches into account. [ralf@linux-mips.org: Other already supported CPUs are free to support more than 8 ways of cache as well.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10640/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -945,7 +945,9 @@ static void b5k_instruction_hazard(void)
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}
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static char *way_string[] = { NULL, "direct mapped", "2-way",
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"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
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"3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
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"9-way", "10-way", "11-way", "12-way",
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"13-way", "14-way", "15-way", "16-way",
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};
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static void probe_pcache(void)
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