forked from luck/tmp_suning_uos_patched
thermal: stm32: Disable interrupts at probe
In case of CPU reset, the interrupts could be enabled at boot time. Disable interrupts and clear flags. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200110101605.24984-4-p.paillet@st.com
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@ -51,6 +51,12 @@
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/* DTS_DR register mask definitions */
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#define TS1_MFREQ_MASK GENMASK(15, 0)
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/* DTS_ITENR register mask definitions */
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#define ITENR_MASK (GENMASK(2, 0) | GENMASK(6, 4))
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/* DTS_ICIFR register mask definitions */
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#define ICIFR_MASK (GENMASK(2, 0) | GENMASK(6, 4))
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/* Less significant bit position definitions */
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#define TS1_T0_POS 16
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#define TS1_SMP_TIME_POS 16
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@ -330,12 +336,10 @@ static int stm_disable_irq(struct stm_thermal_sensor *sensor)
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{
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u32 value;
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/* Disable IT generation for low and high thresholds */
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/* Disable IT generation */
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value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET);
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writel_relaxed(value & ~(LOW_THRESHOLD | HIGH_THRESHOLD),
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sensor->base + DTS_ITENR_OFFSET);
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dev_dbg(sensor->dev, "%s: IT disabled on sensor side", __func__);
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value &= ~ITENR_MASK;
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writel_relaxed(value, sensor->base + DTS_ITENR_OFFSET);
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return 0;
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}
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@ -645,6 +649,11 @@ static int stm_thermal_probe(struct platform_device *pdev)
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return PTR_ERR(sensor->clk);
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}
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stm_disable_irq(sensor);
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/* Clear irq flags */
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writel_relaxed(ICIFR_MASK, sensor->base + DTS_ICIFR_OFFSET);
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/* Register IRQ into GIC */
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ret = stm_register_irq(sensor);
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if (ret)
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