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scsi: qla2xxx: Fix endianness annotations in header files

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Annotate members of FC protocol and firmware dump data structures as big
endian. Annotate members of RISC control structures as little endian.
Annotate mailbox registers as little endian. Annotate the mb[] arrays as
CPU-endian because communication of the mb[] values with the hardware
happens through the readw() and writew() functions. readw() converts from
__le16 to u16 and writew() converts from u16 to __le16. Annotate 'handles'
as CPU-endian because for the firmware these are opaque values.

Link: https://lore.kernel.org/r/20200518211712.11395-15-bvanassche@acm.org
CC: Hannes Reinecke <hare@suse.de>
Cc: Nilesh Javali <njavali@marvell.com>
Cc: Quinn Tran <qutran@marvell.com>
Cc: Martin Wilck <mwilck@suse.com>
Cc: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Daniel Wagner <dwagner@suse.de>
Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com>
Signed-off-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Bart Van Assche 2020-05-18 14:17:11 -07:00 committed by Martin K. Petersen
parent 2a4b684ab0
commit 21038b0900
9 changed files with 1097 additions and 1097 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

444
drivers/scsi/qla2xxx/qla_dbg.h
View File

@ -12,205 +12,205 @@
*/
struct qla2300_fw_dump {
uint16_t hccr;
uint16_t pbiu_reg[8];
uint16_t risc_host_reg[8];
uint16_t mailbox_reg[32];
uint16_t resp_dma_reg[32];
uint16_t dma_reg[48];
uint16_t risc_hdw_reg[16];
uint16_t risc_gp0_reg[16];
uint16_t risc_gp1_reg[16];
uint16_t risc_gp2_reg[16];
uint16_t risc_gp3_reg[16];
uint16_t risc_gp4_reg[16];
uint16_t risc_gp5_reg[16];
uint16_t risc_gp6_reg[16];
uint16_t risc_gp7_reg[16];
uint16_t frame_buf_hdw_reg[64];
uint16_t fpm_b0_reg[64];
uint16_t fpm_b1_reg[64];
uint16_t risc_ram[0xf800];
uint16_t stack_ram[0x1000];
uint16_t data_ram[1];
__be16 hccr;
__be16 pbiu_reg[8];
__be16 risc_host_reg[8];
__be16 mailbox_reg[32];
__be16 resp_dma_reg[32];
__be16 dma_reg[48];
__be16 risc_hdw_reg[16];
__be16 risc_gp0_reg[16];
__be16 risc_gp1_reg[16];
__be16 risc_gp2_reg[16];
__be16 risc_gp3_reg[16];
__be16 risc_gp4_reg[16];
__be16 risc_gp5_reg[16];
__be16 risc_gp6_reg[16];
__be16 risc_gp7_reg[16];
__be16 frame_buf_hdw_reg[64];
__be16 fpm_b0_reg[64];
__be16 fpm_b1_reg[64];
__be16 risc_ram[0xf800];
__be16 stack_ram[0x1000];
__be16 data_ram[1];
};
struct qla2100_fw_dump {
uint16_t hccr;
uint16_t pbiu_reg[8];
uint16_t mailbox_reg[32];
uint16_t dma_reg[48];
uint16_t risc_hdw_reg[16];
uint16_t risc_gp0_reg[16];
uint16_t risc_gp1_reg[16];
uint16_t risc_gp2_reg[16];
uint16_t risc_gp3_reg[16];
uint16_t risc_gp4_reg[16];
uint16_t risc_gp5_reg[16];
uint16_t risc_gp6_reg[16];
uint16_t risc_gp7_reg[16];
uint16_t frame_buf_hdw_reg[16];
uint16_t fpm_b0_reg[64];
uint16_t fpm_b1_reg[64];
uint16_t risc_ram[0xf000];
__be16 hccr;
__be16 pbiu_reg[8];
__be16 mailbox_reg[32];
__be16 dma_reg[48];
__be16 risc_hdw_reg[16];
__be16 risc_gp0_reg[16];
__be16 risc_gp1_reg[16];
__be16 risc_gp2_reg[16];
__be16 risc_gp3_reg[16];
__be16 risc_gp4_reg[16];
__be16 risc_gp5_reg[16];
__be16 risc_gp6_reg[16];
__be16 risc_gp7_reg[16];
__be16 frame_buf_hdw_reg[16];
__be16 fpm_b0_reg[64];
__be16 fpm_b1_reg[64];
__be16 risc_ram[0xf000];
};
struct qla24xx_fw_dump {
uint32_t host_status;
uint32_t host_reg[32];
uint32_t shadow_reg[7];
uint16_t mailbox_reg[32];
uint32_t xseq_gp_reg[128];
uint32_t xseq_0_reg[16];
uint32_t xseq_1_reg[16];
uint32_t rseq_gp_reg[128];
uint32_t rseq_0_reg[16];
uint32_t rseq_1_reg[16];
uint32_t rseq_2_reg[16];
uint32_t cmd_dma_reg[16];
uint32_t req0_dma_reg[15];
uint32_t resp0_dma_reg[15];
uint32_t req1_dma_reg[15];
uint32_t xmt0_dma_reg[32];
uint32_t xmt1_dma_reg[32];
uint32_t xmt2_dma_reg[32];
uint32_t xmt3_dma_reg[32];
uint32_t xmt4_dma_reg[32];
uint32_t xmt_data_dma_reg[16];
uint32_t rcvt0_data_dma_reg[32];
uint32_t rcvt1_data_dma_reg[32];
uint32_t risc_gp_reg[128];
uint32_t lmc_reg[112];
uint32_t fpm_hdw_reg[192];
uint32_t fb_hdw_reg[176];
uint32_t code_ram[0x2000];
uint32_t ext_mem[1];
__be32 host_status;
__be32 host_reg[32];
__be32 shadow_reg[7];
__be16 mailbox_reg[32];
__be32 xseq_gp_reg[128];
__be32 xseq_0_reg[16];
__be32 xseq_1_reg[16];
__be32 rseq_gp_reg[128];
__be32 rseq_0_reg[16];
__be32 rseq_1_reg[16];
__be32 rseq_2_reg[16];
__be32 cmd_dma_reg[16];
__be32 req0_dma_reg[15];
__be32 resp0_dma_reg[15];
__be32 req1_dma_reg[15];
__be32 xmt0_dma_reg[32];
__be32 xmt1_dma_reg[32];
__be32 xmt2_dma_reg[32];
__be32 xmt3_dma_reg[32];
__be32 xmt4_dma_reg[32];
__be32 xmt_data_dma_reg[16];
__be32 rcvt0_data_dma_reg[32];
__be32 rcvt1_data_dma_reg[32];
__be32 risc_gp_reg[128];
__be32 lmc_reg[112];
__be32 fpm_hdw_reg[192];
__be32 fb_hdw_reg[176];
__be32 code_ram[0x2000];
__be32 ext_mem[1];
};
struct qla25xx_fw_dump {
uint32_t host_status;
uint32_t host_risc_reg[32];
uint32_t pcie_regs[4];
uint32_t host_reg[32];
uint32_t shadow_reg[11];
uint32_t risc_io_reg;
uint16_t mailbox_reg[32];
uint32_t xseq_gp_reg[128];
uint32_t xseq_0_reg[48];
uint32_t xseq_1_reg[16];
uint32_t rseq_gp_reg[128];
uint32_t rseq_0_reg[32];
uint32_t rseq_1_reg[16];
uint32_t rseq_2_reg[16];
uint32_t aseq_gp_reg[128];
uint32_t aseq_0_reg[32];
uint32_t aseq_1_reg[16];
uint32_t aseq_2_reg[16];
uint32_t cmd_dma_reg[16];
uint32_t req0_dma_reg[15];
uint32_t resp0_dma_reg[15];
uint32_t req1_dma_reg[15];
uint32_t xmt0_dma_reg[32];
uint32_t xmt1_dma_reg[32];
uint32_t xmt2_dma_reg[32];
uint32_t xmt3_dma_reg[32];
uint32_t xmt4_dma_reg[32];
uint32_t xmt_data_dma_reg[16];
uint32_t rcvt0_data_dma_reg[32];
uint32_t rcvt1_data_dma_reg[32];
uint32_t risc_gp_reg[128];
uint32_t lmc_reg[128];
uint32_t fpm_hdw_reg[192];
uint32_t fb_hdw_reg[192];
uint32_t code_ram[0x2000];
uint32_t ext_mem[1];
__be32 host_status;
__be32 host_risc_reg[32];
__be32 pcie_regs[4];
__be32 host_reg[32];
__be32 shadow_reg[11];
__be32 risc_io_reg;
__be16 mailbox_reg[32];
__be32 xseq_gp_reg[128];
__be32 xseq_0_reg[48];
__be32 xseq_1_reg[16];
__be32 rseq_gp_reg[128];
__be32 rseq_0_reg[32];
__be32 rseq_1_reg[16];
__be32 rseq_2_reg[16];
__be32 aseq_gp_reg[128];
__be32 aseq_0_reg[32];
__be32 aseq_1_reg[16];
__be32 aseq_2_reg[16];
__be32 cmd_dma_reg[16];
__be32 req0_dma_reg[15];
__be32 resp0_dma_reg[15];
__be32 req1_dma_reg[15];
__be32 xmt0_dma_reg[32];
__be32 xmt1_dma_reg[32];
__be32 xmt2_dma_reg[32];
__be32 xmt3_dma_reg[32];
__be32 xmt4_dma_reg[32];
__be32 xmt_data_dma_reg[16];
__be32 rcvt0_data_dma_reg[32];
__be32 rcvt1_data_dma_reg[32];
__be32 risc_gp_reg[128];
__be32 lmc_reg[128];
__be32 fpm_hdw_reg[192];
__be32 fb_hdw_reg[192];
__be32 code_ram[0x2000];
__be32 ext_mem[1];
};
struct qla81xx_fw_dump {
uint32_t host_status;
uint32_t host_risc_reg[32];
uint32_t pcie_regs[4];
uint32_t host_reg[32];
uint32_t shadow_reg[11];
uint32_t risc_io_reg;
uint16_t mailbox_reg[32];
uint32_t xseq_gp_reg[128];
uint32_t xseq_0_reg[48];
uint32_t xseq_1_reg[16];
uint32_t rseq_gp_reg[128];
uint32_t rseq_0_reg[32];
uint32_t rseq_1_reg[16];
uint32_t rseq_2_reg[16];
uint32_t aseq_gp_reg[128];
uint32_t aseq_0_reg[32];
uint32_t aseq_1_reg[16];
uint32_t aseq_2_reg[16];
uint32_t cmd_dma_reg[16];
uint32_t req0_dma_reg[15];
uint32_t resp0_dma_reg[15];
uint32_t req1_dma_reg[15];
uint32_t xmt0_dma_reg[32];
uint32_t xmt1_dma_reg[32];
uint32_t xmt2_dma_reg[32];
uint32_t xmt3_dma_reg[32];
uint32_t xmt4_dma_reg[32];
uint32_t xmt_data_dma_reg[16];
uint32_t rcvt0_data_dma_reg[32];
uint32_t rcvt1_data_dma_reg[32];
uint32_t risc_gp_reg[128];
uint32_t lmc_reg[128];
uint32_t fpm_hdw_reg[224];
uint32_t fb_hdw_reg[208];
uint32_t code_ram[0x2000];
uint32_t ext_mem[1];
__be32 host_status;
__be32 host_risc_reg[32];
__be32 pcie_regs[4];
__be32 host_reg[32];
__be32 shadow_reg[11];
__be32 risc_io_reg;
__be16 mailbox_reg[32];
__be32 xseq_gp_reg[128];
__be32 xseq_0_reg[48];
__be32 xseq_1_reg[16];
__be32 rseq_gp_reg[128];
__be32 rseq_0_reg[32];
__be32 rseq_1_reg[16];
__be32 rseq_2_reg[16];
__be32 aseq_gp_reg[128];
__be32 aseq_0_reg[32];
__be32 aseq_1_reg[16];
__be32 aseq_2_reg[16];
__be32 cmd_dma_reg[16];
__be32 req0_dma_reg[15];
__be32 resp0_dma_reg[15];
__be32 req1_dma_reg[15];
__be32 xmt0_dma_reg[32];
__be32 xmt1_dma_reg[32];
__be32 xmt2_dma_reg[32];
__be32 xmt3_dma_reg[32];
__be32 xmt4_dma_reg[32];
__be32 xmt_data_dma_reg[16];
__be32 rcvt0_data_dma_reg[32];
__be32 rcvt1_data_dma_reg[32];
__be32 risc_gp_reg[128];
__be32 lmc_reg[128];
__be32 fpm_hdw_reg[224];
__be32 fb_hdw_reg[208];
__be32 code_ram[0x2000];
__be32 ext_mem[1];
};
struct qla83xx_fw_dump {
uint32_t host_status;
uint32_t host_risc_reg[48];
uint32_t pcie_regs[4];
uint32_t host_reg[32];
uint32_t shadow_reg[11];
uint32_t risc_io_reg;
uint16_t mailbox_reg[32];
uint32_t xseq_gp_reg[256];
uint32_t xseq_0_reg[48];
uint32_t xseq_1_reg[16];
uint32_t xseq_2_reg[16];
uint32_t rseq_gp_reg[256];
uint32_t rseq_0_reg[32];
uint32_t rseq_1_reg[16];
uint32_t rseq_2_reg[16];
uint32_t rseq_3_reg[16];
uint32_t aseq_gp_reg[256];
uint32_t aseq_0_reg[32];
uint32_t aseq_1_reg[16];
uint32_t aseq_2_reg[16];
uint32_t aseq_3_reg[16];
uint32_t cmd_dma_reg[64];
uint32_t req0_dma_reg[15];
uint32_t resp0_dma_reg[15];
uint32_t req1_dma_reg[15];
uint32_t xmt0_dma_reg[32];
uint32_t xmt1_dma_reg[32];
uint32_t xmt2_dma_reg[32];
uint32_t xmt3_dma_reg[32];
uint32_t xmt4_dma_reg[32];
uint32_t xmt_data_dma_reg[16];
uint32_t rcvt0_data_dma_reg[32];
uint32_t rcvt1_data_dma_reg[32];
uint32_t risc_gp_reg[128];
uint32_t lmc_reg[128];
uint32_t fpm_hdw_reg[256];
uint32_t rq0_array_reg[256];
uint32_t rq1_array_reg[256];
uint32_t rp0_array_reg[256];
uint32_t rp1_array_reg[256];
uint32_t queue_control_reg[16];
uint32_t fb_hdw_reg[432];
uint32_t at0_array_reg[128];
uint32_t code_ram[0x2400];
uint32_t ext_mem[1];
__be32 host_status;
__be32 host_risc_reg[48];
__be32 pcie_regs[4];
__be32 host_reg[32];
__be32 shadow_reg[11];
__be32 risc_io_reg;
__be16 mailbox_reg[32];
__be32 xseq_gp_reg[256];
__be32 xseq_0_reg[48];
__be32 xseq_1_reg[16];
__be32 xseq_2_reg[16];
__be32 rseq_gp_reg[256];
__be32 rseq_0_reg[32];
__be32 rseq_1_reg[16];
__be32 rseq_2_reg[16];
__be32 rseq_3_reg[16];
__be32 aseq_gp_reg[256];
__be32 aseq_0_reg[32];
__be32 aseq_1_reg[16];
__be32 aseq_2_reg[16];
__be32 aseq_3_reg[16];
__be32 cmd_dma_reg[64];
__be32 req0_dma_reg[15];
__be32 resp0_dma_reg[15];
__be32 req1_dma_reg[15];
__be32 xmt0_dma_reg[32];
__be32 xmt1_dma_reg[32];
__be32 xmt2_dma_reg[32];
__be32 xmt3_dma_reg[32];
__be32 xmt4_dma_reg[32];
__be32 xmt_data_dma_reg[16];
__be32 rcvt0_data_dma_reg[32];
__be32 rcvt1_data_dma_reg[32];
__be32 risc_gp_reg[128];
__be32 lmc_reg[128];
__be32 fpm_hdw_reg[256];
__be32 rq0_array_reg[256];
__be32 rq1_array_reg[256];
__be32 rp0_array_reg[256];
__be32 rp1_array_reg[256];
__be32 queue_control_reg[16];
__be32 fb_hdw_reg[432];
__be32 at0_array_reg[128];
__be32 code_ram[0x2400];
__be32 ext_mem[1];
};
#define EFT_NUM_BUFFERS 4
@ -223,45 +223,45 @@ struct qla83xx_fw_dump {
#define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b))
struct qla2xxx_fce_chain {
uint32_t type;
uint32_t chain_size;
__be32 type;
__be32 chain_size;
uint32_t size;
uint32_t addr_l;
uint32_t addr_h;
uint32_t eregs[8];
__be32 size;
__be32 addr_l;
__be32 addr_h;
__be32 eregs[8];
};
/* used by exchange off load and extended login offload */
struct qla2xxx_offld_chain {
uint32_t type;
uint32_t chain_size;
__be32 type;
__be32 chain_size;
uint32_t size;
uint32_t reserved;
u64 addr;
__be32 size;
__be32 reserved;
__be64 addr;
};
struct qla2xxx_mq_chain {
uint32_t type;
uint32_t chain_size;
__be32 type;
__be32 chain_size;
uint32_t count;
uint32_t qregs[4 * QLA_MQ_SIZE];
__be32 count;
__be32 qregs[4 * QLA_MQ_SIZE];
};
struct qla2xxx_mqueue_header {
uint32_t queue;
__be32 queue;
#define TYPE_REQUEST_QUEUE 0x1
#define TYPE_RESPONSE_QUEUE 0x2
#define TYPE_ATIO_QUEUE 0x3
uint32_t number;
uint32_t size;
__be32 number;
__be32 size;
};
struct qla2xxx_mqueue_chain {
uint32_t type;
uint32_t chain_size;
__be32 type;
__be32 chain_size;
};
#define DUMP_CHAIN_VARIANT 0x80000000
@ -274,28 +274,28 @@ struct qla2xxx_mqueue_chain {
struct qla2xxx_fw_dump {
uint8_t signature[4];
uint32_t version;
__be32 version;
uint32_t fw_major_version;
uint32_t fw_minor_version;
uint32_t fw_subminor_version;
uint32_t fw_attributes;
__be32 fw_major_version;
__be32 fw_minor_version;
__be32 fw_subminor_version;
__be32 fw_attributes;
uint32_t vendor;
uint32_t device;
uint32_t subsystem_vendor;
uint32_t subsystem_device;
__be32 vendor;
__be32 device;
__be32 subsystem_vendor;
__be32 subsystem_device;
uint32_t fixed_size;
uint32_t mem_size;
uint32_t req_q_size;
uint32_t rsp_q_size;
__be32 fixed_size;
__be32 mem_size;
__be32 req_q_size;
__be32 rsp_q_size;
uint32_t eft_size;
uint32_t eft_addr_l;
uint32_t eft_addr_h;
__be32 eft_size;
__be32 eft_addr_l;
__be32 eft_addr_h;
uint32_t header_size;
__be32 header_size;
union {
struct qla2100_fw_dump isp21;
@ -370,7 +370,7 @@ ql_log_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *,
uint32_t, void **);
extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *,
extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, __be32 *,
uint32_t, void **);
extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *,
struct qla_hw_data *);

652
drivers/scsi/qla2xxx/qla_def.h
View File

File diff suppressed because it is too large Load Diff

754
drivers/scsi/qla2xxx/qla_fw.h
View File

File diff suppressed because it is too large Load Diff

2
drivers/scsi/qla2xxx/qla_inline.h
View File

@ -40,7 +40,7 @@ qla24xx_calc_iocbs(scsi_qla_host_t *vha, uint16_t dsds)
* register value.
*/
static __inline__ uint16_t
qla2x00_debounce_register(volatile uint16_t __iomem *addr)
qla2x00_debounce_register(volatile __le16 __iomem *addr)
{
volatile uint16_t first;
volatile uint16_t second;

8
drivers/scsi/qla2xxx/qla_mr.h
View File

@ -96,7 +96,7 @@ struct tsk_mgmt_entry_fx00 {
uint8_t sys_define;
uint8_t entry_status; /* Entry Status. */
__le32 handle; /* System handle. */
uint32_t handle; /* System handle. */
uint32_t reserved_0;
@ -121,13 +121,13 @@ struct abort_iocb_entry_fx00 {
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
__le32 handle; /* System handle. */
uint32_t handle; /* System handle. */
__le32 reserved_0;
__le16 tgt_id_sts; /* Completion status. */
__le16 options;
__le32 abort_handle; /* System handle. */
uint32_t abort_handle; /* System handle. */
__le32 reserved_2;
__le16 req_que_no;
@ -166,7 +166,7 @@ struct fxdisc_entry_fx00 {
uint8_t sys_define; /* System Defined. */
uint8_t entry_status; /* Entry Status. */
__le32 handle; /* System handle. */
uint32_t handle; /* System handle. */
__le32 reserved_0; /* System handle. */
__le16 func_num;

64
drivers/scsi/qla2xxx/qla_nvme.h
View File

@ -48,26 +48,26 @@ struct cmd_nvme {
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
uint16_t nport_handle; /* N_PORT handle. */
uint16_t timeout; /* Command timeout. */
__le16 nport_handle; /* N_PORT handle. */
__le16 timeout; /* Command timeout. */
uint16_t dseg_count; /* Data segment count. */
uint16_t nvme_rsp_dsd_len; /* NVMe RSP DSD length */
__le16 dseg_count; /* Data segment count. */
__le16 nvme_rsp_dsd_len; /* NVMe RSP DSD length */
uint64_t rsvd;
uint16_t control_flags; /* Control Flags */
__le16 control_flags; /* Control Flags */
#define CF_NVME_FIRST_BURST_ENABLE BIT_11
#define CF_DIF_SEG_DESCR_ENABLE BIT_3
#define CF_DATA_SEG_DESCR_ENABLE BIT_2
#define CF_READ_DATA BIT_1
#define CF_WRITE_DATA BIT_0
uint16_t nvme_cmnd_dseg_len; /* Data segment length. */
__le16 nvme_cmnd_dseg_len; /* Data segment length. */
__le64 nvme_cmnd_dseg_address __packed;/* Data segment address. */
__le64 nvme_rsp_dseg_address __packed; /* Data segment address. */
uint32_t byte_count; /* Total byte count. */
__le32 byte_count; /* Total byte count. */
uint8_t port_id[3]; /* PortID of destination port. */
uint8_t vp_index;
@ -82,24 +82,24 @@ struct pt_ls4_request {
uint8_t sys_define;
uint8_t entry_status;
uint32_t handle;
uint16_t status;
uint16_t nport_handle;
uint16_t tx_dseg_count;
__le16 status;
__le16 nport_handle;
__le16 tx_dseg_count;
uint8_t vp_index;
uint8_t rsvd;
uint16_t timeout;
uint16_t control_flags;
__le16 timeout;
__le16 control_flags;
#define CF_LS4_SHIFT 13
#define CF_LS4_ORIGINATOR 0
#define CF_LS4_RESPONDER 1
#define CF_LS4_RESPONDER_TERM 2
uint16_t rx_dseg_count;
uint16_t rsvd2;
uint32_t exchange_address;
uint32_t rsvd3;
uint32_t rx_byte_count;
uint32_t tx_byte_count;
__le16 rx_dseg_count;
__le16 rsvd2;
__le32 exchange_address;
__le32 rsvd3;
__le32 rx_byte_count;
__le32 tx_byte_count;
struct dsd64 dsd[2];
};
@ -107,32 +107,32 @@ struct pt_ls4_request {
struct pt_ls4_rx_unsol {
uint8_t entry_type;
uint8_t entry_count;
uint16_t rsvd0;
uint16_t rsvd1;
__le16 rsvd0;
__le16 rsvd1;
uint8_t vp_index;
uint8_t rsvd2;
uint16_t rsvd3;
uint16_t nport_handle;
uint16_t frame_size;
uint16_t rsvd4;
uint32_t exchange_address;
__le16 rsvd3;
__le16 nport_handle;
__le16 frame_size;
__le16 rsvd4;
__le32 exchange_address;
uint8_t d_id[3];
uint8_t r_ctl;
be_id_t s_id;
uint8_t cs_ctl;
uint8_t f_ctl[3];
uint8_t type;
uint16_t seq_cnt;
__le16 seq_cnt;
uint8_t df_ctl;
uint8_t seq_id;
uint16_t rx_id;
uint16_t ox_id;
uint32_t param;
uint32_t desc0;
__le16 rx_id;
__le16 ox_id;
__le32 param;
__le32 desc0;
#define PT_LS4_PAYLOAD_OFFSET 0x2c
#define PT_LS4_FIRST_PACKET_LEN 20
uint32_t desc_len;
uint32_t payload[3];
__le32 desc_len;
__le32 payload[3];
};
/*

36
drivers/scsi/qla2xxx/qla_nx.h
View File

@ -800,16 +800,16 @@ struct qla82xx_legacy_intr_set {
#define QLA82XX_URI_FIRMWARE_IDX_OFF 29
struct qla82xx_uri_table_desc{
uint32_t findex;
uint32_t num_entries;
uint32_t entry_size;
uint32_t reserved[5];
__le32 findex;
__le32 num_entries;
__le32 entry_size;
__le32 reserved[5];
};
struct qla82xx_uri_data_desc{
uint32_t findex;
uint32_t size;
uint32_t reserved[5];
__le32 findex;
__le32 size;
__le32 reserved[5];
};
/* UNIFIED ROMIMAGE END */
@ -829,22 +829,22 @@ struct qla82xx_uri_data_desc{
* ISP 8021 I/O Register Set structure definitions.
*/
struct device_reg_82xx {
uint32_t req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */
uint32_t rsp_q_in[64]; /* Response Queue In-Pointer. */
uint32_t rsp_q_out[64]; /* Response Queue Out-Pointer. */
__le32 req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */
__le32 rsp_q_in[64]; /* Response Queue In-Pointer. */
__le32 rsp_q_out[64]; /* Response Queue Out-Pointer. */
uint16_t mailbox_in[32]; /* Mail box In registers */
uint16_t unused_1[32];
uint32_t hint; /* Host interrupt register */
__le16 mailbox_in[32]; /* Mailbox In registers */
__le16 unused_1[32];
__le32 hint; /* Host interrupt register */
#define HINT_MBX_INT_PENDING BIT_0
uint16_t unused_2[62];
uint16_t mailbox_out[32]; /* Mail box Out registers */
uint32_t unused_3[48];
__le16 unused_2[62];
__le16 mailbox_out[32]; /* Mailbox Out registers */
__le32 unused_3[48];
uint32_t host_status; /* host status */
__le32 host_status; /* host status */
#define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
#define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
uint32_t host_int; /* Interrupt status. */
__le32 host_int; /* Interrupt status. */
#define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */
};

232
drivers/scsi/qla2xxx/qla_target.h
View File

@ -135,37 +135,37 @@ struct nack_to_isp {
uint8_t entry_status; /* Entry Status. */
union {
struct {
uint32_t sys_define_2; /* System defined. */
__le32 sys_define_2; /* System defined. */
target_id_t target;
uint8_t target_id;
uint8_t reserved_1;
uint16_t flags;
uint16_t resp_code;
uint16_t status;
uint16_t task_flags;
uint16_t seq_id;
uint16_t srr_rx_id;
uint32_t srr_rel_offs;
uint16_t srr_ui;
uint16_t srr_flags;
uint16_t srr_reject_code;
__le16 flags;
__le16 resp_code;
__le16 status;
__le16 task_flags;
__le16 seq_id;
__le16 srr_rx_id;
__le32 srr_rel_offs;
__le16 srr_ui;
__le16 srr_flags;
__le16 srr_reject_code;
uint8_t srr_reject_vendor_uniq;
uint8_t srr_reject_code_expl;
uint8_t reserved_2[24];
} isp2x;
struct {
uint32_t handle;
uint16_t nport_handle;
__le16 nport_handle;
uint16_t reserved_1;
uint16_t flags;
uint16_t srr_rx_id;
uint16_t status;
__le16 flags;
__le16 srr_rx_id;
__le16 status;
uint8_t status_subcode;
uint8_t fw_handle;
uint32_t exchange_address;
uint32_t srr_rel_offs;
uint16_t srr_ui;
uint16_t srr_flags;
__le32 exchange_address;
__le32 srr_rel_offs;
__le16 srr_ui;
__le16 srr_flags;
uint8_t reserved_4[19];
uint8_t vp_index;
uint8_t srr_reject_vendor_uniq;
@ -175,7 +175,7 @@ struct nack_to_isp {
} isp24;
} u;
uint8_t reserved[2];
uint16_t ox_id;
__le16 ox_id;
} __packed;
#define NOTIFY_ACK_FLAGS_TERMINATE BIT_3
#define NOTIFY_ACK_SRR_FLAGS_ACCEPT 0
@ -206,16 +206,16 @@ struct ctio_to_2xxx {
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System defined handle */
target_id_t target;
uint16_t rx_id;
uint16_t flags;
uint16_t status;
uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
uint16_t dseg_count; /* Data segment count. */
uint32_t relative_offset;
uint32_t residual;
uint16_t reserved_1[3];
uint16_t scsi_status;
uint32_t transfer_length;
__le16 rx_id;
__le16 flags;
__le16 status;
__le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
__le16 dseg_count; /* Data segment count. */
__le32 relative_offset;
__le32 residual;
__le16 reserved_1[3];
__le16 scsi_status;
__le32 transfer_length;
struct dsd32 dsd[3];
} __packed;
#define ATIO_PATH_INVALID 0x07
@ -257,7 +257,7 @@ struct fcp_hdr {
uint16_t seq_cnt;
__be16 ox_id;
uint16_t rx_id;
uint32_t parameter;
__le32 parameter;
} __packed;
struct fcp_hdr_le {
@ -267,12 +267,12 @@ struct fcp_hdr_le {
uint8_t cs_ctl;
uint8_t f_ctl[3];
uint8_t type;
uint16_t seq_cnt;
__le16 seq_cnt;
uint8_t df_ctl;
uint8_t seq_id;
uint16_t rx_id;
uint16_t ox_id;
uint32_t parameter;
__le16 rx_id;
__le16 ox_id;
__le32 parameter;
} __packed;
#define F_CTL_EXCH_CONTEXT_RESP BIT_23
@ -306,7 +306,7 @@ struct atio7_fcp_cmnd {
* BUILD_BUG_ON in qlt_init().
*/
uint8_t add_cdb[4];
/* uint32_t data_length; */
/* __le32 data_length; */
} __packed;
/*
@ -316,31 +316,31 @@ struct atio7_fcp_cmnd {
struct atio_from_isp {
union {
struct {
uint16_t entry_hdr;
__le16 entry_hdr;
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t sys_define_2; /* System defined. */
__le32 sys_define_2; /* System defined. */
target_id_t target;
uint16_t rx_id;
uint16_t flags;
uint16_t status;
__le16 rx_id;
__le16 flags;
__le16 status;
uint8_t command_ref;
uint8_t task_codes;
uint8_t task_flags;
uint8_t execution_codes;
uint8_t cdb[MAX_CMDSZ];
uint32_t data_length;
uint16_t lun;
__le32 data_length;
__le16 lun;
uint8_t initiator_port_name[WWN_SIZE]; /* on qla23xx */
uint16_t reserved_32[6];
uint16_t ox_id;
__le16 reserved_32[6];
__le16 ox_id;
} isp2x;
struct {
uint16_t entry_hdr;
__le16 entry_hdr;
uint8_t fcp_cmnd_len_low;
uint8_t fcp_cmnd_len_high:4;
uint8_t attr:4;
uint32_t exchange_addr;
__le32 exchange_addr;
#define ATIO_EXCHANGE_ADDRESS_UNKNOWN 0xFFFFFFFF
struct fcp_hdr fcp_hdr;
struct atio7_fcp_cmnd fcp_cmnd;
@ -352,7 +352,7 @@ struct atio_from_isp {
#define FCP_CMD_LENGTH_MASK 0x0fff
#define FCP_CMD_LENGTH_MIN 0x38
uint8_t data[56];
uint32_t signature;
__le32 signature;
#define ATIO_PROCESSED 0xDEADDEAD /* Signature */
} raw;
} u;
@ -395,36 +395,36 @@ struct ctio7_to_24xx {
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System defined handle */
uint16_t nport_handle;
__le16 nport_handle;
#define CTIO7_NHANDLE_UNRECOGNIZED 0xFFFF
uint16_t timeout;
uint16_t dseg_count; /* Data segment count. */
__le16 timeout;
__le16 dseg_count; /* Data segment count. */
uint8_t vp_index;
uint8_t add_flags;
le_id_t initiator_id;
uint8_t reserved;
uint32_t exchange_addr;
__le32 exchange_addr;
union {
struct {
uint16_t reserved1;
__le16 reserved1;
__le16 flags;
uint32_t residual;
__le32 residual;
__le16 ox_id;
uint16_t scsi_status;
uint32_t relative_offset;
uint32_t reserved2;
uint32_t transfer_length;
uint32_t reserved3;
__le16 scsi_status;
__le32 relative_offset;
__le32 reserved2;
__le32 transfer_length;
__le32 reserved3;
struct dsd64 dsd;
} status0;
struct {
uint16_t sense_length;
__le16 sense_length;
__le16 flags;
uint32_t residual;
__le32 residual;
__le16 ox_id;
uint16_t scsi_status;
uint16_t response_len;
uint16_t reserved;
__le16 scsi_status;
__le16 response_len;
__le16 reserved;
uint8_t sense_data[24];
} status1;
} u;
@ -440,18 +440,18 @@ struct ctio7_from_24xx {
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System defined handle */
uint16_t status;
uint16_t timeout;
uint16_t dseg_count; /* Data segment count. */
__le16 status;
__le16 timeout;
__le16 dseg_count; /* Data segment count. */
uint8_t vp_index;
uint8_t reserved1[5];
uint32_t exchange_address;
uint16_t reserved2;
uint16_t flags;
uint32_t residual;
uint16_t ox_id;
uint16_t reserved3;
uint32_t relative_offset;
__le32 exchange_address;
__le16 reserved2;
__le16 flags;
__le32 residual;
__le16 ox_id;
__le16 reserved3;
__le32 relative_offset;
uint8_t reserved4[24];
} __packed;
@ -489,29 +489,29 @@ struct ctio_crc2_to_fw {
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
uint16_t nport_handle; /* N_PORT handle. */
__le16 nport_handle; /* N_PORT handle. */
__le16 timeout; /* Command timeout. */
uint16_t dseg_count; /* Data segment count. */
__le16 dseg_count; /* Data segment count. */
uint8_t vp_index;
uint8_t add_flags; /* additional flags */
#define CTIO_CRC2_AF_DIF_DSD_ENA BIT_3
le_id_t initiator_id; /* initiator ID */
uint8_t reserved1;
uint32_t exchange_addr; /* rcv exchange address */
uint16_t reserved2;
__le32 exchange_addr; /* rcv exchange address */
__le16 reserved2;
__le16 flags; /* refer to CTIO7 flags values */
uint32_t residual;
__le32 residual;
__le16 ox_id;
uint16_t scsi_status;
__le16 scsi_status;
__le32 relative_offset;
uint32_t reserved5;
__le32 reserved5;
__le32 transfer_length; /* total fc transfer length */
uint32_t reserved6;
__le32 reserved6;
__le64 crc_context_address __packed; /* Data segment address. */
uint16_t crc_context_len; /* Data segment length. */
uint16_t reserved_1; /* MUST be set to 0. */
__le16 crc_context_len; /* Data segment length. */
__le16 reserved_1; /* MUST be set to 0. */
};
/* CTIO Type CRC_x Status IOCB */
@ -522,20 +522,20 @@ struct ctio_crc_from_fw {
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
uint16_t status;
uint16_t timeout; /* Command timeout. */
uint16_t dseg_count; /* Data segment count. */
uint32_t reserved1;
uint16_t state_flags;
__le16 status;
__le16 timeout; /* Command timeout. */
__le16 dseg_count; /* Data segment count. */
__le32 reserved1;
__le16 state_flags;
#define CTIO_CRC_SF_DIF_CHOPPED BIT_4
uint32_t exchange_address; /* rcv exchange address */
uint16_t reserved2;
uint16_t flags;
uint32_t resid_xfer_length;
uint16_t ox_id;
__le32 exchange_address; /* rcv exchange address */
__le16 reserved2;
__le16 flags;
__le32 resid_xfer_length;
__le16 ox_id;
uint8_t reserved3[12];
uint16_t runt_guard; /* reported runt blk guard */
__le16 runt_guard; /* reported runt blk guard */
uint8_t actual_dif[8];
uint8_t expected_dif[8];
} __packed;
@ -558,29 +558,29 @@ struct abts_recv_from_24xx {
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint8_t reserved_1[6];
uint16_t nport_handle;
__le16 nport_handle;
uint8_t reserved_2[2];
uint8_t vp_index;
uint8_t reserved_3:4;
uint8_t sof_type:4;
uint32_t exchange_address;
__le32 exchange_address;
struct fcp_hdr_le fcp_hdr_le;
uint8_t reserved_4[16];
uint32_t exchange_addr_to_abort;
__le32 exchange_addr_to_abort;
} __packed;
#define ABTS_PARAM_ABORT_SEQ BIT_0
struct ba_acc_le {
uint16_t reserved;
__le16 reserved;
uint8_t seq_id_last;
uint8_t seq_id_valid;
#define SEQ_ID_VALID 0x80
#define SEQ_ID_INVALID 0x00
uint16_t rx_id;
uint16_t ox_id;
uint16_t high_seq_cnt;
uint16_t low_seq_cnt;
__le16 rx_id;
__le16 ox_id;
__le16 high_seq_cnt;
__le16 low_seq_cnt;
} __packed;
struct ba_rjt_le {
@ -604,21 +604,21 @@ struct abts_resp_to_24xx {
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle;
uint16_t reserved_1;
uint16_t nport_handle;
uint16_t control_flags;
__le16 reserved_1;
__le16 nport_handle;
__le16 control_flags;
#define ABTS_CONTR_FLG_TERM_EXCHG BIT_0
uint8_t vp_index;
uint8_t reserved_3:4;
uint8_t sof_type:4;
uint32_t exchange_address;
__le32 exchange_address;
struct fcp_hdr_le fcp_hdr_le;
union {
struct ba_acc_le ba_acct;
struct ba_rjt_le ba_rjt;
} __packed payload;
uint32_t reserved_4;
uint32_t exchange_addr_to_abort;
__le32 reserved_4;
__le32 exchange_addr_to_abort;
} __packed;
/*
@ -634,21 +634,21 @@ struct abts_resp_from_24xx_fw {
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle;
uint16_t compl_status;
__le16 compl_status;
#define ABTS_RESP_COMPL_SUCCESS 0
#define ABTS_RESP_COMPL_SUBCODE_ERROR 0x31
uint16_t nport_handle;
uint16_t reserved_1;
__le16 nport_handle;
__le16 reserved_1;
uint8_t reserved_2;
uint8_t reserved_3:4;
uint8_t sof_type:4;
uint32_t exchange_address;
__le32 exchange_address;
struct fcp_hdr_le fcp_hdr_le;
uint8_t reserved_4[8];
uint32_t error_subcode1;
__le32 error_subcode1;
#define ABTS_RESP_SUBCODE_ERR_ABORTED_EXCH_NOT_TERM 0x1E
uint32_t error_subcode2;
uint32_t exchange_addr_to_abort;
__le32 error_subcode2;
__le32 exchange_addr_to_abort;
} __packed;
/********************************************************************\

2
drivers/scsi/qla2xxx/qla_tmpl.h
View File

@ -27,7 +27,7 @@ struct __packed qla27xx_fwdt_template {
uint32_t saved_state[16];
uint32_t reserved_3[8];
uint32_t firmware_version[5];
__le32 firmware_version[5];
};
#define TEMPLATE_TYPE_FWDUMP 99