AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

A number of fixes for this release, but mostly:

Browse Source 
- A fixup for the A10 CSI DT binding merged during the 5.4-rc1 window
   - A fix for a dt-binding error
   - Addition of phy regulator delays
   - The PMU on the A64 was found to be non-functional, so we've dropped it for now
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXa/4RQAKCRDj7w1vZxhR
 xU3XAQDYuCixpCCftKIhjcz+oultXqAJysDEE44dATwT1YfINgD/eBSwBw1l/Ni7
 yOumUvRZ1fJC3NO8e7vh9cYN9yy5tgw=
 =3/ru
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-fixes-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes

A number of fixes for this release, but mostly:
  - A fixup for the A10 CSI DT binding merged during the 5.4-rc1 window
  - A fix for a dt-binding error
  - Addition of phy regulator delays
  - The PMU on the A64 was found to be non-functional, so we've dropped it for now

* tag 'sunxi-fixes-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: dts: sun7i: Drop the module clock from the device tree
  dt-bindings: media: sun4i-csi: Drop the module clock
  media: dt-bindings: Fix building error for dt_binding_check
  arm64: dts: allwinner: a64: sopine-baseboard: Add PHY regulator delay
  arm64: dts: allwinner: a64: Drop PMU node
  arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator delay

Link: https://lore.kernel.org/r/80085a57-c40f-4bed-a9c3-19858d87564e.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-10-23 08:34:08 -07:00
commit 21397ae00f
5 changed files with 20 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/allwinner,sun4i-a10-csi.yaml#
$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings
@ -27,14 +27,12 @@ properties:
clocks:
items:
- description: The CSI interface clock
- description: The CSI module clock
- description: The CSI ISP clock
- description: The CSI DRAM clock
clock-names:
items:
- const: bus
- const: mod
- const: isp
- const: ram
@ -89,9 +87,8 @@ examples:
compatible = "allwinner,sun7i-a20-csi0";
reg = <0x01c09000 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
<&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
clock-names = "bus", "mod", "isp", "ram";
clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
clock-names = "bus", "isp", "ram";
resets = <&ccu RST_CSI0>;
port {

5
arch/arm/boot/dts/sun7i-a20.dtsi
View File

@ -380,9 +380,8 @@ csi0: csi@1c09000 {
compatible = "allwinner,sun7i-a20-csi0";
reg = <0x01c09000 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
<&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
clock-names = "bus", "mod", "isp", "ram";
clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
clock-names = "bus", "isp", "ram";
resets = <&ccu RST_CSI0>;
status = "disabled";
};

9
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
View File

@ -63,3 +63,12 @@ ext_rgmii_phy: ethernet-phy@1 {
reg = <1>;
};
};
&reg_dc1sw {
/*
* Ethernet PHY needs 30ms to properly power up and some more
* to initialize. 100ms should be plenty of time to finish
* whole process.
*/
regulator-enable-ramp-delay = <100000>;
};

6
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
View File

@ -159,6 +159,12 @@ &ohci1 {
};
&reg_dc1sw {
/*
* Ethernet PHY needs 30ms to properly power up and some more
* to initialize. 100ms should be plenty of time to finish
* whole process.
*/
regulator-enable-ramp-delay = <100000>;
regulator-name = "vcc-phy";
};

9
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -142,15 +142,6 @@ osc32k: osc32k_clk {
clock-output-names = "ext-osc32k";
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";